2. 4th semester Spring 2008
3rd semester Fall 2007
·Modern Communication Theory •VLSI ASIC design
·CMOS Mixed Signal IC Design
5th semester Spring 2009
•Instrumentation Circuits
•Modem Design
Projects in third semester of MS:
MODERN COMMUNICATION THEORY PROJECTS:
1.ZigBee™ Protocol Physical Layer Simulation
Description:
ZigBeeTM is the architecture developed on top of the IEEE 802.15.4 reference stack model and takes advantage of its
powerful physical radio layer(PHY). IEEE 802.15.4 physical layer specifies differential binary phase shift
keying(DBPSK) for 868 MHz , 915 MHz carrier frequencies and Offset Quadrature phase shift keying (OQPSK)
with for 2.4 GHZ carrier. The DBPSK and OQPSK are implemented along with direct sequence spread spectrum
DSSS. Mat lab simulation excludes the RF modulation part of the physical layer and only takes care of baseband
modulation. Transmitter, channel and receiver blocks are simulated for each modulation type in an attempt to
analyze and compare BER Vs SNR performance.
2. BER Vs SNR performance comparisons of modulation techniques such as BPSK,DBPSK,QPSK,16-QAM ect.
CMOS MIXED SIGNAL IC DESIGN PROJECTS:
1.HSPICE simulations and Layouts of Biasing circuits for short channel devices .
Description:
Aim of the project was to design Biasing circuit using and generation of reference drive voltages . Simulation was
done using netlist to check the required specifications using HSPICE taking AMI 05 as the reference model. The
circuit layout was also done using the layout tool ELDO and netlist with parasitics was also extracted and
simulated to compare the effects of parasitic on the circuit design.
2.Design and HSPICE simulations of two stage amplifier (source follower/push-pull topology as second stage)
Description:
Two stage amplifier was designed by making trade offs between bandwidth and the gain of the amplifier to drive
10K Ohm load.
3. Design and HSPICE simulations of three stage amplifier
Description:
Two stage amplifier was designed to achieve a unity frequency of 150MHz and to drive10K Ohm resistor and 10
micro farads capacitor load. Compensation techniques were also used to stabilize the amplifier.
Projects in Second semester of MS:
1. Development of ALU unit of ARM processor.
Description:
A behavioral model in VHDL of ARM ALU was developed using Xilinx ISE 9iwith vertex-300 as the target device.
ALU was tested for its proper behavior by checking the simulation results and using Xilinx ISE 9i tool the
occupancy of the ALU on target device was observed.
2. Development of 4 stage pipelined RISC processor :
Description:
3. A 4 stage Pipelined RISC processor with 16 bit data-path was modeled in VHDL and a set of subroutines for 8 bit
multiplication, 16 bit multiplication and 16 bit division were successfully tested for the proper functionality.
Techniques to overcome Data hazards, Stalls in pipelining were also implemented.
Projects in the First semester of MS:
1. Layout Development of 4:1 MUX using Complex gates (Use MOSIS SCMOS n-well layout rules for
ami05 process.)
Description:
The objectives of this project were to understand the elements involved in generating mask layers for fabrication of
IC standard cells, to understand the origin of IC parasitic elements, and to examine the layout for a professionally
generated cell. Prepare the layouts for implementation using either n-well technology and no more than 2 metal
levels include latch-up protection in all cells. Each cell was put through a DRC (Design Rule) check for
scalable CMOS (ADK) design rules.
2) Transistor level Development of Pulse Position Detector
Description:
The objectives of this project were to understand the elements involved in generating transistor level development of
a small system ,and check for proper functionality using Transistor Level Timing Simulation Using ELDO Transient
Analysis Tool.
The system consists of a pulse generating circuitry , A 8:1 MUX,, And a decoder made of pass transistors. The pulse
was selected using the MUX using its select inputs and the decoder will have only one of its output HIGH
corresponding to the position of the pulse .
