1. SMIT A. PATEL
209, P Square Apartment, Spice Garden,
Marathahalli, Bengaluru/Bangalore - 560037
(M) +91 9650401664
13mecc12@nirmauni.ac.in,smitpatel9624@gmail.com
OBJECTIVE
Seeking for challenging position in Analog & Mixed Signal Layout Design where I can employ my technical
skills, learn new things and work towards Organization goal that offers Professional growth.
CORE COMPETENCY
• Exposure of technology by undergoing additional training in VLSI
• Familiar with ASIC Design and Full-Custom flow
• Experience in Standard cell layout design, Analog layout design and Memory layout design
• Hands on experience with advanced technology nodes like 28nm, 90nm & 180nm
• Hands on experience in analog matching techniques and Analog signal routing
• Practical knowledge of IC verification terminologies like DRC, LVS, Compatibility rules
• Familiar with reliability issues such as EM, Latchup, Self-heating, Hot carriers and Overvoltage failure
• Understanding of DFM considerations such as antenna effect, density checks, via doubling and signal in-
tegrity
• Familiar with deep submicron effects like WPE, STI, LOD and OPC
• Familiar with setup and hold timing concept
• Hands-on experience on different tools like :- IC Studio, PYXIS R Circuit and Layout Editor (Mentor
Graphics), Calibre R for DRC and LVS, Virtuoso (Cadence) and Eldo (Mentor Graphics)
EXPERIENCE
Technical Intern - RV - VLSI Design Center, Bangalore, India October’15 - April’16
Key Role: Floorplanning and designing compact layouts of SRAM memory leaf cells, Analog blocks using
analog device matching technique and Standard cell layout with DRC, LVS and Compatibility
clean.
Project Title: Layout of 32*32 bit SRAM Memory Cell in 28nm Technology
Description: Project involves floorplaning and layout designing of basic block of SRAM which includes
Sense amplifier, Pre-charge & mux, Scan block, Control block, Pre-Decoders (3:8 row decoder
and 2:4 column decoder), Final decoder array, Data_in and Data_out according to given top
level schematic and constraints.
Challenges: 1. Floor Planning of some blocks were challenging since, area of pre-charge & mux, width of
sense amplifier, Data_in and Data_out was fixed and height of final decoder array was fixed
2. Block level nets and pins were to be routed and placed considering top level placement
3. Avoiding metal crossing over Analog Block (Sense amplifier) during top level routing
4. Routing using lower metal was challenging because lower metal are present in block level
Tools Used: IC Studio, PYXIS R Circuit and Layout Editor (Mentor Graphics), Calibre R for DRC and LVS

2. Project Title: Layout design of Two stage Op-Amp in 180nm Technology
Description: Project involves study of Analog concepts, Analog Matching techniques like common centroid
& interdigitation and layout design of two stage op-amp according to given schematic.
Challenges: 1. Floor Planning considering matching of differential pair and current mirrors using common
centroid technique
2. Achieving symmetrical routing of nets avoiding routing over active poly maintaining compact
layout
Tools Used: IC Studio, PYXIS R Circuit and Layout Editor (Mentor Graphics), Calibre R for DRC and LVS
Project Title: Layout design of 9 track standard cells in 28nm technology
Description: To deliver DRC/LVS clean layout for multiple logic gates in standard cell layout that can be used
as hard macros in physical design.
Challenges: 1. Optimization of layout by diffusion sharing and placing metal pins on grid by maintaining
proper coordinates by undergoing compatibility checks.
2. Special rules to make sure seamless usage in PNR tool area efficient layouts including well
sharing and transistor folding techniques.
Project Title: Layout design of 9 track standard cells in 90nm technology
Description: To deliver DRC/LVS clean layout for Basic Logic circuits like logic gates (NAND2X1, NAND2x2,
NAND2x4, NOR3X1, NOR3X4, AND2X1, OR3X1, OR3X2, OR3X4), Combinational Logics (Half
Adder – HADDX2, Mux – MUX21X2, Decode – DEC21X1) and Sequential Logics (D – Flip flops:-
DFFX1 DFFX2) with multiple drive strengths according to given specification and constraints.
Challenges: 1. Understanding and fixing LVS errors like shorts, Opens, missing instance, missing ports and
missing nets.
2. Fitting the layout in the given PR Boundary and minimizing area was challenging in case of
sequential and combinational circuits
3. Reducing parasitics
Technical Intern - ST Microelectronics, Greater Noida, India July’14-July’15
Key Role: 1. Development of SPICE command file for IO Ring Validation
2. Generating SPICE Netlist from Cadence for IO Test-Chip
3. Extracting Leakage Currents from IO Test-Chip
4. Electrical characterization of Analog IP’s (Post-Silicon Validation)
Project Title: Analog, IO Test-Chip Validation (Pre and Post – Silicon Validation)
• Simulation and Characterization of Input/Output (IO) analog buffers with a driver and a receiver model
for 28nm FDSOI, CMOS032 and CMOS040 technology libraries
• Spice Netlist generation, Eldo model simulation, Circuit extraction and input Stimulus commands using
various measures for TT, FFA, SS, FSA and SFA corner case analysis in Eldo and Cadence Virtuoso
• Validation of various Analog IPs (Post – Silicon Validation)
• Testing behavior of analog IPs for different voltage and temperature conditions
• Determining current consumption of IPs
• Determining whether the obtained results are within specifications

3. ACADEMIC DETAILS
M.Tech,Communication Engineering June’13-June’15
Nirma University(NU),Gujarat,India CGPA: 7.37/10
BE,Electronics & Communication Engineering Aug’09-May’13
Gujarat Technological University(GTU),Gujarat,India CGPA: 7.40/10
HSC June’09
GSHSEB,Gujarat,India Percentage:58%
SSC June’07
GSHSEB,Gujarat,India Percentage:83.31%
SKILLS
Operating System: Windows, Unix
Scripting Language: SPICE, Perl (beginner), Shell (beginner)
Tools Used: IC Studio, Pyxis Circuit and Layout Editor, Calibre for DRC and LVS, Virtuoso, Eldo
PERSONAL DETAILS
Name: Smit A. Patel
Date of Birth: 14th
, August 1992
Gender: Male
Marital Status: Single
Languages Known: English, Hindi, Gujarati
Nationality: Indian
DECLARATION
I, Smit A. Patel, hereby declare that the information furnished above is true to the best of my knowledge.
- Smit A. Patel