MATLAB and Simulink for Communications System Design (Design Conference 2013)

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This session will show how Model-Based Design with MATLAB® and Simulink® can be used to model, simulate, and implement communications systems. Attendees will learn how multidomain modeling with continuous verification and automatic code generation can dramatically reduce system design time. A QPSK receiver model will be used as an example to highlight the design flow.

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MATLAB and Simulink for Communications System Design (Design Conference 2013)

  1. 1. MATLAB and Simulink forCommunications System DesignReference Designs and System Applications
  2. 2. ©2013 The Mathworks, Inc.Today’s AgendaAccelerating System Development with Model-Based DesignModel-Based Design for CommunicationsAutomatic Code Generation for System Deployment2
  3. 3. ©2013 The Mathworks, Inc.The System Design ChallengeHow Can We: Verify our hardware implementationmatches system specification? Iterate our designs faster?3Algorithm and System DesignFPGAFPGA / MCUHDL / C / C++
  4. 4. ©2013 The Mathworks, Inc.Solution: Model-Based DesignDesign, simulate, and validatealgorithms and system modelsin MATLAB® and Simulink ®Automatically generate HDLand C codeVerify the hardwareimplementation against thesystem model4MATLAB and SimulinkAlgorithm Design and System DesignFPGAAutomatic CodeGenerationFPGA / MCUHDL / C / C++VerifyGenerate
  5. 5. ©2013 The Mathworks, Inc.Model-Based Design Overview5INTEGRATIONIMPLEMENTATIONDESIGNTEST&VERIFICATIONRESEARCH REQUIREMENTSARM FPGAVHDL, VerilogC, C++Environment ModelsPhysical ComponentsAlgorithms
  6. 6. ©2013 The Mathworks, Inc.Model-Based Design OverviewDesign and simulateapplication behaviorusing expansive libraryof existing IP for signalprocessing, communications,motor control, image andvideo processing, analog,and RFThe MATLAB language canbe used for scripting,testing, debugging, andalgorithm developmentIncorporate Xilinx SystemGenerator IP or custom IP inC/C++ or RTL6INTEGRATIONRESEARCH REQUIREMENTSIMPLEMENTATIONARM FPGAVHDL, VerilogC, C++DESIGNEnvironment ModelsPhysical ComponentsAlgorithmsTEST&VERIFICATION
  7. 7. ©2013 The Mathworks, Inc.Model-Based Design Overview Explore design partitionsbetween hardware andsoftware components AXI P-core generation forFPGA ARM-9 Neon instructionreplacements for software Automation scripts for systemassembly in Xilinx PlatformStudio, Bitgen, and for deviceprogramming Hardware-in-the-loopsimulation as free-running orsynchronized Integration with Xilinx tools fordesign iteration7INTEGRATIONRESEARCH REQUIREMENTSIMPLEMENTATIONARM FPGAVHDL, VerilogC, C++DESIGNEnvironment ModelsPhysical ComponentsAlgorithmsTEST&VERIFICATION
  8. 8. ©2013 The Mathworks, Inc.Model-Based Design forCommunicationsTargeting the Zynq SDR Platform8
  9. 9. ©2013 The Mathworks, Inc.Design Flow9XPSMATLAB andSimulinkTop-Level ModelSDKCreate FSBL& BOOT.BINBITELFSDR Reference DesignSubsystemASubsystemB
  10. 10. ©2013 The Mathworks, Inc.System Design Components10Library of building blocksIntegration with RFIncorporate MATLABfunctionsInteractivity and visualization
  11. 11. ©2013 The Mathworks, Inc.Digital Up/Down ConverterBaseband simulation model, no carrier modulationAssume no channel effects except low-pass filterFocus on practical FPGA implementation11
  12. 12. ©2013 The Mathworks, Inc.Top-Level Model12
  13. 13. ©2013 The Mathworks, Inc.Automatic Code Generation13
  14. 14. ©2013 The Mathworks, Inc.Why Use Automatic Code Generation?Continuous tool flow from algorithm design to implementationEliminates hand-coding errorsSpec/model updates automatically accounted forEnables fast deployment on hardware14
  15. 15. ©2013 The Mathworks, Inc.Xilinx System Generator IntegrationIn1 Out1Xilinx System Generator Subsystem Simulink SubsystemIn1Out1Out2Out3Out4Out5In1In2In3In4In5Out11 1Out1In115
  16. 16. ©2013 The Mathworks, Inc.Xilinx System Generator Subsystem ExampleGateway In BlockGateway Out BlocksXilinx System Generator Subsystem16
  17. 17. ©2013 The Mathworks, Inc.Xilinx System Generator/MathWorks HDLCoder InteroperabilityHigh-level abstraction + device-optimized quality of resultsValidate algorithms on hardware using real-world analog dataHDL Coder• Native Simulink blocks• Abstract data types• Floating-to-fixed conversion• Design exploration• HW/SW partitioningSystem Generator for DSP• Xilinx DSP blockset• Analog data acquisition• Ethernet HW cosimulationHigh-Level Design and ModelingOptimized Design Using Xilinx DSP BlocksetTool Interoperability17
  18. 18. ©2013 The Mathworks, Inc.What We CoveredSystem Development with Model-Based DesignVerification through SimulationAutomatic Code Generation for FPGA and SoC Implementation18
  19. 19. ©2013 The Mathworks, Inc.Topics for Further StudyAnalog and RF device modeling and simulation tovalidate algorithm operation with specific device models Help to determine the right interface devices for your designHardware co-simulation to verify algorithm operationwith real-world signalsHDL code verification and FPGA-in-the-loop test benches19
  20. 20. ©2013 The Mathworks, Inc.More Information on Model-Based Design forCommunications Systems Development MATLAB Central: Communication Systems Reference Curvesby Idin Motedayen-Aval Pilot Directed Continuous Sync of OFDMby Dick Benson MathWorks Book Program Contemporary Communication SystemsUsing MATLAB and Simulink, 2e ,Proakis/Salehi/Bauch Digital Communications: A Discrete-TimeApproach, Rice Multirate Signal Processing forCommunication Systems , Harris Communications System ToolboxDemos US MIL-STD-188-110B BasebandEnd-to-End Link IEEE 802.16-2004 OFDM PHY Link IEEE 802.11a WLAN Physical Layer20
  21. 21. ©2013 The Mathworks, Inc.MathWorks DSP Package for the Zynq-7000 SoC/Analog Devices Software-Defined Radio KitHardware Avnet ZedBoard 7020 Analog Devices AD-FMCOMMS1-EBZ FMC ModuleSoftware MathWorks DSP Design Package MATLAB Simulink HDL Coder MATLAB Coder™ Fixed-Point Designer™ Signal Processing Toolbox™ DSP System Toolbox™ Xilinx ISE® WebPACK software Linux drivers and applicationssoftware HDL source Reference designsOrdering Information (North America)Part Number: AES-ZSDR-ADI-G-MATW-ANUL(Annual Term License)Part Number: AES-ZSDR-ADI-G-MATW-PERP(Perpetual License)www.em.avnet.com/adizynqsdrOutside North America:Contact fpga_expert@mathworks.com21
  22. 22. ©2013 The Mathworks, Inc.Visit the MathWorks Table in the Exhibition RoomModel-based design workflowfor communications systemdesignMATLAB and SimulinkSimRF and other physicalmodeling tools22This demo board is available for purchase:www.analog.com/DC13-hardware

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