contenct of collouquim

1. 1
SYNOPSIS
High frequency and increasing design complexity are stretching the
limits of design tools and methodologies. Recent advances in silicon technology
have made it possible to design with significantly larger gate densities and
higher clock frequencies. Design engineers have used these advances to
integrate more complex functionality into their system-on-chip (SoC) designs.
As process geometries move into the nanometer range, even digital logic
designs with analog circuits are getting complex, and for these high-
performance designs, cell-based verification flows are insufficient[1]-[3]. Hence
the designers need to move to custom designs for accurate simulation of
mixed-signal designs.
Currently designers have a variety of simulation methodologies to verify
the designs that contained both analog and digital circuits. At the lowest level
of abstraction, designers are used to model the analog and digital circuitry at
the transistor level. To analyze such transistor level circuitry, SICE-like
simulators are used. Typically lower levels of abstraction result into slower
simulation time. Consequently, for simulating large mixed-signal designs at the
transistor level with a standard SPICE-like simulators will result more slower
simulation time[4],[5].
At the highest level of abstraction, to model the mixed signal designs
some system designers are using VHDL–AMS (VHSIC Hardware Description
Language-Analog & Mixed Signal Extensions) or Verilog-AMS (Verilog Analog &

2. 2
Mixed Signal Extensions). But, these languages are basically used for
simulation. Unlike VHDL and Veriolg languages, AMS (Analog & Mixed Signal)
languages will not be used for synthesis in the near future[6],[7].
Also, while designing the mixed-signal circuits using VHDL-AMS, both
the digital simulation tool and the analog simulation tool are to be used, by
which the major bottleneck is synchronization[8],[9]. To eliminate the
synchronization problem and to provide the synthesis to mixed-signal circuits,
there is a necessity of new mixed-signal design methodology.
An ideal integrated mixed-signal simulator should processes a single
circuit description and generates a single output file i.e., all of the processing is
done within a single program so that synchronization problem will be
eliminated. This is therefore the most efficient type of mixed signal simulator.
Unfortunately such a simulator has not yet been built[10]-[13].
Analog to Digital Converter(ADC) and Digital to Analog Converter(DAC)
are called the mixed-signal design circuits[14]. ADC and DAC are used for data
processing applications and signal processing applications. ADC and DAC are
also called as coder and decoder respectively or CODEC.
The ADC used for signal processing applications is designed with over-
sampling rate otherwise, the signal can not be re-constructed and hence, it
gives great design difficulties to build-in along with the digital signal
processor(DSP) [15]. Hence, to eliminate the over-sampled ADC and to increase
the traditional fixed-point ADC precision, using the novel mixed-signal design

3. 3
methodology a floating-point audio CODEC using IEEE 754 standard for signal
processing is designed. Since, CODEC is a co-processor, half precision is used.
As the floating-point values demand for more storage space, to reduce
the number of computations, the floating point audio CODEC is designed using
multi-rate analysis technique. Multi-rate analysis is nothing but analyzing the
different frequency bands at various resolutions. This multi-rate analysis for
mixed-signal floating point is carried-out by Discrete Wavelet
Transform(DWT)[16].
To design mixed-signal floating point DWT or CODEC, the Multiplier
Accumulator Content(MAC) should be in floating point. To get MAC in floating
point, floating point multiplier and floating point adder should be designed with
half precision. Since, the digital simulation tools are not supporting the
floating-point designs, an user defined floating point library package with half
precision is developed[17] and compiled with the standard IEEE(Institute of
Electrical and Electronics Engineers) library packages of Modelsim 10.3c and
then simulated the required floating point designs.
To increase the speed of the floating point CODEC, the floating point
adder structure is modified. In the floating point adder operation, the
successive numbers are added in the sequential fashion. To increase the speed
of operation, the serial adder structure is developed by the parallel and pipe
line processing and used it in the floating point MAC[18]. This novel floating
point MAC is used in the standard floating point DWT and prove that the novel

4. 4
floating point DWT is having the more speed than the standard floating point
DWT.
Based on the above requirement, the following objectives are framed to
overcome the analog and mixed-signal design issues.
The first objective of this thesis is to propose a novel design
methodology for mixed-signal Integrated Circuit designs through which the
system performance is to be improved.
The second objective is to develop the floating point Multiplier
Accumulator Content(MAC) using IEEE 754 standard in VHDL for the novel
design methodology.
The third objective is to design the floating point audio 3-stage Discrete
Wavelet Transform(DWT) for real time applications using VHDL.
The fourth objective is to update the floating point adder which is the
part of the MAC with novel algorithm in order to increase the speed of the
floating point audio 3-stage Discrete Wavelet Transform(DWT).

5. 5
To carry out the above objectives, the overall thesis is organized as follows:
CHAPTER 1: INTRODUCTION
This chapter addresses the motivation of the research work.
This motivation drives to find the novel design methodology and to design the
floating point mixed-signal audio CODEC. This chapter also summarizes
mainly, the objectives of the thesis.
CHAPTER 2: LITERATURE SURVEY
This chapter describes the review of earlier work in the
design of mixed-signal Integrated Circuits with various design methodologies.
This review is based on the material published in a wide range of technical
books, journals and conference proceedings.
CHAPTER 3: PROPOSED MIXED-SIGNAL DESIGN METHODOLOGY
There are various bottlenecks for traditional mixed-signal designs i.e., at
the transistor level of mixed-signal designs as the SPICE is used, speed is less.
As VHDL-AMS is used, synthesis is not possible for the whole system and also
synchronization problem arises. Therefore a novel mixed-signal design
methodology is required.
In the novel mixed-signal design methodology, for the realization of
mixed signal system designs, a simplified digital modeling of analog signal
operation is developed. For this, a package, defining analog operation in digital
environment using floating point notation compatible to IEEE 754 standard is

6. 6
developed. This user defined library definition of analog operation, integrated
with the standard definition library of available EDA tool, provides a simplified
method to use HDL definition for mixed signal designs[19].
The step by step design flow using novel design methodology for the mixed
signal designs is explained[20] and shown in below figure3.1.
Implementation
Timing analysis
Compile the VHDL MAC
package with standard IEEE
library
Design details of real-time
Application(DWT)
Analysis
RTL Coding (VHDL)
simulation
synthesis
Wantto optimize
thedesign ?
Any syntax
errors ?
Design of IEEE754 16 bit
floating point MAC package in
VHDL
Compile the VHDL code of DWT
Figure(3.1):Flow chart of prposed mixed-signal design methodology
No
Yes
Yes
No
Optimize
MAC

7. 7
CHAPTER 4: DESIGN OF MULTPLIR ACCUMULATOR CONTENT USING
IEEE 754 FORMAT
The basic building block of any signal processing application is MAC
which consists of floating point adder, multiplier and shifter as show in below
figure4.1.
x(n)
y(n)
h(n)
Figure(4.1): Design of floating point MAC for mixed-signal applications
The above MAC can be illustrated as:
N-1
y(n)= ∑ h(k).x(n-k)
k=0 if N=number of coefficients =4
= h(0).x(n-0) + h(1).x(n-1) + h(2).x(n-2) + h(3).x(n-3)
The MAC is designed using IEEE 754 16 bit floating point format. In this
representation, 1-bit is allotted to the sign, 4-bits are allotted to the exponent
and 11-bits are allotted to the mantissa as shown in below figure4.2.
Sign(1) Exponent(4) Mantissa(11)
Figure(4.2): IEEE 754 16 bit floating point representation.
In this chapter, the complete design of floating point MAC is covered with the
design of floating point multiplier, adder and shifter[21].
Multiplier
adder
shifter

8. 8
8
Ex Ey
Exponent
Subtractor
Sign
Computation
Sx
Sy
0 1
Sz
Inc/Dec
Ez
Detect
Carry
Fx Fy
Swap
Shift right
Significantadder
Shift right/left
Rounding logic
Fz
sign
d=Ex-Ey
C C
Max(Ex or Ey)
2x1
Mux
Figure( 4.3): Design of IEEE 754 Floating Point Adder
The above figure4.3 shows the floating point adder. As the floating point adder
is going to be optimized with parallel and pipeline processing, the simulation
results of floating point adder [21] and MAC are shown in below figures4.4 and
4.5
Simulation results: For Floating Point Adder:
Figure(4.4) For Floating Point Adder:
Input A=1 0101 11111100011 Input B=1 1101 10110100010 Output C=1 1101 10110101001

9. 9
Floating point MAC:
Figure(4.5):Multiplier Accumulator Content
Input A=0 1010 01111111001 Input B=1 0111 11000000111 Output C=1 1011 01011111110
Synthesis Reports:
The below table 4.1 shows the synthesis report of floating point adder and
MAC. It is observed that floating point MAC has taken more hardware
resources than floating point adder.
Parameters
Operations
Floating Point Adder MAC
Number of IOs 31 out of 182
17%
54 out of 182
29%
Number of BELs: 59 out of 1728
3.4%
103 out of 1728
6%
Minimum period 0.983 ns 1.286 ns
Max. Frequency(speed) 1017.2 MHz 793.65 MHz
Power consumption 9.726mw 12.493mw
Table 4.1 for Floating Point Adder and MAC:

10. 10
CHAPTER 5: DESIGN OF DISCRETE WAVELET TRANSFORM WITH MAC
USING IEEE 754 FORMAT FOR REAL-TIME APPLICATIONS
In this chapter, the main concentration is to design the floating point
audio 3-stage Discrete Wavelet Transform. Figure5.1 shows the de-composer of
DWT. In order to process the analog signal on the digital 3-stage filter bank of
DWT, analog signal is to be over sampled. These over sampled values are in
floating point. But, digital system accepts integer values so that floating point
values are represented using IEEE-754 notation and then applied to 3- stage
decomposer of DWT.
5.1 DESIGN OF IEEE 754 FLOATING POINT DWT DECOMPOSER:
Figure(5.1): De-composer of Discrete Wavelet Transform
The above DWT is constituted with the design of FIR(Finite Impulse
Response) High Pass and Low Pass filters as given below[22],[23].
d1
d2
d3
a1

11. 11
Design of FIR LPF using db4 window:
The standard db4 LPF co-efficients are obtained through MATLAB as-
?[L]=orthfilt(dbwavf(‘db4’))
h(0)=1 0100 00001001000 = -0.1294
h(1)=0 0100 10101100010 = 0.2241
h(2)=0 0110 10101100010 = 0.8365
h(3)=0 0101 11101110100 = 0.4830
The transfer function H(z) of FIR LPF is given by ,
4-1
H(z)=Z{h(n)} = ∑ h(n)z = h(0)+h(1)z +h(2)z +h(3)z
n=0
=-0.1294+0.2241[z ]+0.8365[z ]+0.4830[z ]
Structure :
LetH(z)=Y(Z)/X(Z)=-0.1294+0.2241[z ]+0.8365[z ]+0.4830[z ]
Hence,Y(Z)=-0.1294[X(Z)]+0.2241[z ]X(Z)+0.8365[z ] X(Z)+0.4830[z ]X(Z)
The below figure(5.2) shows the design structure of FIR low pass filter.
X(Z)
x(n)
-0.1294 0.2241 0.8365 0.4830
z z z
+ + + + My(n)
Y(Z)
y(m)
-1 -2
-3
Figure(5.2 ): Usage of FIR LPF Filter with Decimator :

12. 12
Design of FIR HPF using db4 window:
The standard db4 HPF co-efficients are obtained using MATLAB as -
?[H]=orthfilt(dbwavf(‘db4’))
h(0)=1 0101 11101110100 = -0.4830
h(1)=0 0110 10101100010 = 0.8365
h(2)=1 0100 11001010111 = -0.2241
h(3)=1 0100 00001001000 =-0.1294
The transfer function H(z) of FIR HPF is given by ,
4-1
H(z)=Z{h(n)}= ∑ h(n)z = h(0)+h(1)z +h(2)z +h(3)z
n=0
=-0.4830+0.8365[z ]-0.2241[z ]-0.1294[z ]
Structure :
Let H(z) = Y(Z)/X(Z) =-0.4830+0.8365[z ]-0.2241[z ]-0.1294 [z ]

13. 13
Hence,Y(Z)=-0.4830[X(Z)]+0.8365[z ]X(Z)-0.2241[z ] X(Z)-0.1294[z ]X(Z)
X(Z)
x(n)
-0.4830 0.8365 -0.2241 -0.1294
z z z
+ + + + M
y(n)
Y(Z)
y(m)
-1 -2
-3
Figure(5.3) shows the design structure of FIR High Pass Filter with decimator.
The above FIR Filter with Decimator can be implemented as:
x(n) w(n) y(m)
N-1
w(n)= ∑ h(k).x(n -k) ----1
k=0
The output of the decimator y(m)= W(mM),
which on combiningwith equation1,
N-1
y(m)= ∑ h(k).x( mM-k) -----2
k=0
h(k) M

14. 14
Figure(5.4) and (5.5) show the flow charts of the single stage and multi stage
decimation processes.
start
Readnew inputsample,x(n)
Updatethe delaylineinputwith new input
sample
Computeoutput sample,y(m)
Msamples
obtained?
yes
no
Figure(5.4): Flowchart forthesingle stagedecimationprocess :

15. 15
The below figure(5.5) shows the three stage decimation process.
figure(5.5): the three stage decimation process.
yes
start
Readnewinputsample ,x(n)
Update stage1 delay line with
new input sample
Compute output sample for
stage1, y1
M1
input
samples
?
yes
no
Update satage2 delay line with y1
M2y1
samples
obtained?
M3y2 samples
obtained?
Compute output sample for stage2,
y2
Update satage3 delay line with y2
Compute decimator output sample
y(m)
A
A
yes
no
no
yes
start
Read new input sample ,x(n)
Update stage1delayline with
newinput sample
Compute output sample for
stage1,y1
M1
input
samples
?
yes
no
Updatesatage2delaylinewith y1
M2y1
samples
obtained?
M3y2 samples
obtained?
Computeoutput sampleforstage2,
y2
Updatesatage3delaylinewith y2
Computedecimatoroutput sample
y(m)
A
A
yes
no
no

16. 16
5.2 DESIGN OF IEEE 754 FLOATING POINT DWT RE-CONSTRUCTOR:
Figure(5.6):Re-constructor of Discrete Wavelet Transform
2
2
2
2
2
2
c1
c2
c3
a1
a3
a2
d1
The detailed and approximate co-efficients of the decomposer of DWT are
applied as inputs to the re-constructor of the DWT. After processing on the re-
constructor, the output of the re-constructor is same as the input signal of the
decomposer[24],[25]. The basic device in the re-constructor is interpolator. Its
structure with FIR filter is explained in the below topic.

17. 17
x(n) w(m) y(m)
The output of the interpolator y(m) is -
N-1
y(m)= ∑ h(k).w(m-k) -----1
k=0
L h(k)
x[(m-k)/L], m-k=0,L,2L
0
w(m-k)=
The Interpolator with FIR Filter can be Implemented as:
L
z
z
z
z
xn) w(m)
-1
-1
-1
-1
y(m)
h(0)
h(1)
h(2)
h(3)
h(n)
Figure(5.7): The Interpolator with FIR Filter:
The below figure5.8 and 5.9 show the flow charts for the single stage and three
stage interpolation process.

18. 18
Insert a sample of x(n) in delay line
Compute output sample, y(m)
start
Insert a zero in delay line
L-1 zeros
inserted
Compute output sample, y(m)
no
yes
Figure(5.8): Flow chart for the single stage interpolation process:
stage2
Fetch a new input sample
W3(i)=x(n)
Update stage 3
Delay line with w3(i)
Compute stage3
Output,y3(i)
Insert a zero valued sample
W3(i)=0 i=i+1
L3 stage3 output
samples computed?
i=0 , j=0
Number of stages I=1?
Fetch a sample from stage1
W2(j)=y3(i)
Insert a zero valued sample
W2(j)=0 j=j+1
Compute stage2
Output,y3(j)
Update stage2
Delay line with w2(j)
i=i+1, all L3 samples in
stage3 utilized?
L2 stage2 output
samples computed?
i=0
START n=0
A
B
C
D
D
yes
yes
no
yes
no
stage3
continuation….

19. 19
continuation….
yes
yes
no
no
no
Yes
Yes
Fetcha samplefromstage2
W1(m)=y2(j)
Updatestage1
Delay line with w1(m)
Computestage1
Output,y1(m)
m=m+1,L1
output
samples
obtained?
Insert a zero valued sample
W1(m)=0
J=j+1allL3
samples in
stage2utilized?
Saveoutput samples
Interpol
ation
complet
ed?
J=0,m=0,numb
er of stages
I=2?
stop
n=n+1
B
C
A
no
Figure(5.9): Flow chart for three stage interpolation process
Simulation results:
The simulation results of proposed Discrete Wavelet Transform are
shown in figure5.10. For clear understand the values of inputs and outputs are
tabulated in table 5.1and 5.2 as IEEE 754 format and decimal respectively. If
the input and output values are compared the error is not there.

20. 20
Figure(5.10): The input and output values of the DWT system at particular instant of time say t1.
Table 5.1: Using floating point values:
Figure At
Time
Input Value (Floating) Output Value (Floating) Error
5.10 t1 1000010000110110 1000010010110110 zero
Table 5.2: Using decimal values:
Figure At
Time
Input Value (Decimal) Output Value (Decimal) Error
5.10 t1 -7.6444*10-09 -7.6444*10-09 zero
Synthesis Results:
Figure(5.11): Synthesis Diagram of DWT

21. 21
Figure(5.12): Synthesis Diagram of DWT
Figure(5.13): Synthesis Diagram of DWT

22. 22
Figure(5.14): Synthesis Diagram of DWT
The above figures 5.11 to figure 5.14 show the synthesis diagrams of DWT for
both decomposer and re-constructor. It’s synthesis report for different
parameters is shown in below table 5.3.
Parameters DWT
Number of IOs 105 out of 182
57%
Number of BELs: 205 out of 1728
11.8%
Minimum period 2.649 ns
Max. Frequency(speed) 377.501 MHz
Power consumption 38.46mw
Table 5.3: Different Parameters of DWT designed with IEEE 754 format for real-
time applications

23. 23
CHAPTER 6: MODIFIED MULTIPIER ACCUMULATOR CONTENT WITH
NOVEL ALGORITHM
In order to optimize the DWT designed for the real time applications in
chapter5, the floating point adder of MAC is developed with novel algorithm. In
the floating point adder, the mantissas of the first input and second input are
added in the serial order.
Input Buffer
C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4
SA1 SA1 SA1 SA1 SA1 SA1 SA1 SA1
SA2 SA2SA2SA2
SA4SA4
SA8
Cou
nter
Mod
ule
A
d
d
e
r
M
o
d
u
l
e
Accumulated output
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
5 5 5 5 5 5 5 5
7 7 7 7
11 11
19
16
Figure (6.1): Parallel and Pipelined structure to increase the speed of addition of
mantissas in the floating point adder.
Hence, the system is to be spent more time to add the two mantissas i.e.,
to add the N number of input words, the system will take the N number of

24. 24
clock cycles. For large values of N to get the accumulated output, the
computational time will be too high to meet the timing requirement in real-time
applications. To reduce the computational time, a novel algorithm is developed
in which multiple accumulations will be taking place within very few clock
cycles[26]. The algorithm for new approach of MAC is developed by parallel and
Pipelined structure as shown in above figure(6.1).
Simulation results:
Modified Floating Point Adder:
Figure(6.2): Modified Floating Point Adder
Input A=0 1010 01111111001 Input B=1 0111 11000000111 Output C=0 1010 10110111001
Modified Multiplier Accumulator Content:
Figure(6.3): Modified Multiplier Accumulator Content
Input A=1 1010 01111111001 Input B=0 0111 11000000111 Output C=1 1011 01011111110

25. 25
The above figure6.2 shows the simulation results of modified floating
point adder and figure 6.3 shows the simulation results of modified Multiplier
Accumulator Content with new algorithm. Table 6.1 shows the synthesis report
of both. It is observed that the speed was increased with little expense of
hardware and power consumption.
Synthesis Report:
Parameters Operations
modified Floating Point Adder modified MAC
Number of IOs 31outof182
17%
54 out of 182
29%
Number of BELs: 72 out of 1728
4.16%
129 out of 1728
7.5%
Minimum period 0.729 ns 0.948 ns
Max. Frequency(speed) 1371.7MHz 1020.4 MHz
Power consumption 11.726mw 15.239mw
Table 6.1: Synthesis Report for modified floating point Adder and modified MAC
CHAPTER 7: DESIGN OF NOVEL DISCRETE WAVELET TRANSFORM WITH
MODIFIED MAC FOR REAL-TIME APPLICATIONS
The modified floating point MAC of figure (6.1) is used in the proposed
DWT to design the HPF and LPF. Hence, the decomposer as well as re-
constructor of the novel DWT are shown in figure7.1 and 7.2 respectively.
Similarly, the simulation and synthesis results of both standard and novel
DWT are compared and proved that for the novel one speed is increased with
the bit expense of hardware and power consumption[26].

26. 26
Figure(7.1): De-composer of Discrete Wavelet Transform
Figure(7.2): Re-constructor of Discrete Wavelet Transform
2
2
2
2
2
2
c1
c2
c3
a1
a3
a2
d1

27. 27
Simulation results of Novel DWT :
The input and output values of the DWT system at particular instant of time
is shown in figure7.3.
Figure(7.3): The input and output values of the DWT system at a particular instant of time t1
The input and output values obtained in figure7.3 are tabulated in
table7.1 and 7.2. In table 7.1 the input and output values are taken in floating
point notation. For better understanding purpose the same results are
represented in decimal notation in table7.2. It is observed that speed has been
increased with novel algorithm.
Table 7.1: Using floating point values:
Figure At
Time
Input Value (Floating) Output Value (Floating) Error
7.3 t1 1000110000110101 1000110010011101 zero
Table7.2: Using decimal values:
Figure At
Time
Input Value (Decimal) Output Value (Decimal) Error
7.3 t1 -7.6444*10-06 -7.6444*10-06 zero

28. 28
Synthesis Report:
Figure(7.4): Synthesis Diagram of DWT
Figure(7.5): Synthesis Diagram of DWT

29. 29
Figure(7.6): Synthesis Diagram of DWT
Figure(7.7): Synthesis Diagram of DWT

30. 30
Figure(7.6): Synthesis Diagram of DWT
Figure(7.7): Synthesis Diagram of DWT

31. 31
Figure(7.8): Synthesis Diagram of DWT
Figure(7.9): Synthesis Diagram of DWT

32. 32
Parameters Novel DWT
Number of IOs 105 out of 182
57%
Number of BELs: 236 out of 1728
13.6%
Minimum period 1.937 ns
Max. Frequency(speed) 516.262 MHz 36.757%
Power consumption 41.79mw
8.65%
Table7.3: Synthesis Report of Novel DWT designed with modified MAC
The above figure7.4 to figure7.9 show the synthesis diagram of novel
DWT and table7.3 shows the synthesis report. It is understood that the speed
of novel DWT is increased compare with standard DWT using normal MAC with
less expense of hardware and power consumption.
CHAPTER 8: RESULTS, CONCLUSION AND FUTURE SCOPE
This chapter covers first the result analysis of floating point adder, MAC
and DWT of standard and novel. At the end it is given with conclusions and
future scope. Table8.1 shows the comparison of proposed and novel results of
floating point adder. The synthesis is carried out using Xilinx Synthesis
Technology (XST) tool. The selected hardware device is Xc2s50e-ft256-6.The
speed grade is -6. In this device, the maximum number of IOs are 182 and the
maximum number of BELs are 1728.

33. 33
Table 8.1 Floating Point Adder
PARAMETERS
Proposed Floating Point Adder
using IEEE 754 format
Novel Floating Point Adder using
IEEE 754 format
Number of IOs 31 out of 182
17%
31outof182
17%
Number of BELs 59 out of 1728
3.4%
72 out of 1728
4.16%
Minimum period 0.983 ns 0.729 ns
Max. Frequency
(speed)
1017.2 MHz 1371.7MHz
Pow er consumption 9.726mw 11.726mw
Figure (8.1):IOs Figure (8.2):BELs
17% 17%
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
ProposedNovel
3.40%
4.16%
0.00%
0.50%
1.00%
1.50%
2.00%
2.50%
3.00%
3.50%
4.00%
4.50%
ProposedNovel

34. 34
Figure (8.3):Minimum Period Figure (8.4):Max.Frequency
Figure (8.5):Power Consumption
The above figures 8.1,8.2,8.3,8.4 and 8.5 show the IOs, BELs, Minimum time
period, Maximum frequency and Power consumption respectively of the floating
point adder for the proposed and novel.
0.983
0.729
0
0.2
0.4
0.6
0.8
1
1.2
proposed novel
Minimumperiodinns
1017.2
1371.7
0
200
400
600
800
1000
1200
1400
1600
proposed novel
Max.FrequencyinMhz
9.726
11.726
0
2
4
6
8
10
12
14
proposed novel
PowerConsumptioninmW

35. 35
Table 8.2 Multiplier Accumulator Content
PARAMETERS Proposed Multiplier Accumulator
Content using IEEE 754 format
Novel Multiplier Accumulator
Content using IEEE 754 format
Number of IOs 54 out of 182
29%
54 out of 182
29%
Number of BELs 103 out of 1728
6%
129 out of 1728
7.5%
Minimum period 1.286 ns 0.948 ns
Max. Frequency
(speed)
793.65 MHz 1020.4 MHz
Pow er consumption 12.493 15.239mw
Figure (8.6):IOs Figure (8.7):BELs
29% 29%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
proposed novel
NumberofIOsin%
6%
7.50%
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
proposed novel
NumberofBELsin%

36. 36
Figure (8.8):Min.Period Figure (8.9):Max.Frequency
Figure (8.10):Power Consumption
Table8.2 shows the Comparison of proposed and novel results of
multiplier accumulator content(MAC). The above figures 8.6,8.7,8.8,8.9 and
1.286
0.948
0
0.2
0.4
0.6
0.8
1
1.2
1.4
proposed novel
Minimumperiodinns
793.65
1020.4
0
200
400
600
800
1000
1200
proposed novel
Max.FrequencyinMhz
12.493
15.239
0
2
4
6
8
10
12
14
16
18
proposed novel
PowerConsumptioninmW

37. 37
8.10 show the IOs, BELs, Minimum time period, Maximum frequency and
Power consumption respectively of the Multiplier Accumulate Content(MAC).
The below table8.3 shows the comparison of proposed and novel results of the
discrete wavelet transform.
Table 8.3 Discrete Wavelet Transform
PARAMETERS
Standard DWT using MAC designed
by IEEE 754 FORMAT
Novel DWT using modified MAC
designed by IEEE 754 FORMAT
Number of IOs 105 out of 182 57% 105 out of 182 57%
Number of BELs 205 out of 1728 11.8% 236 out of 1728 13.6%
Minimum period 2.649 ns 1.937 ns
Max. Frequency
(speed)
377.501 MHz 516.262 MHz
36.757%
Pow er consumption 38.46mw 41.79mw
8.65%
Figure (8.11):IOs Figure (8.12):BELs
57% 57%
0
0.1
0.2
0.3
0.4
0.5
0.6
proposed novel
NumberofIOsin%
11.80%
13.60%
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
proposed novel
NumberofBELs%

38. 38
Figure(8.13):Min.Period Figure(8.14):Max. Frequency
Figure (8.15):Power Consumption
The above figures 8.11,8.12,8.13,8.14 and 8.15 show the IOs, BELs,
Minimum time period, Maximum frequency and Power consumption
respectively of the Discrete Wavelet Transforms(DWTs). It is observed in all the
2.649
1.937
0
0.5
1
1.5
2
2.5
3
proposed novel
timeperiodinns
377.501
516.262
0
100
200
300
400
500
600
proposed novel
frequencyinMhz
38.46
41.79
36
37
38
39
40
41
42
43
proposed novel
PowerconsumptioninmW

39. 39
above cases that the hardware resources are more for novel one and the speed
of novel floating point adder is more compare with standard with little bit
expense of power consumption, the reason is since the floating point adder is
operated in parallel and pipe line processing.
Conclusion:
The utilization of the mixed signal design chips is being increased day to
day in almost all the applications like Signal Processing systems, RF
Communication systems and Networking systems etc. But, the design of
mixed-signal systems becomes very typical because of not able to accommodate
both the digital and analog functionalities within the same chip. To design
mixed-signal systems, either the analog design tools or the digital design tools
are not supported at one stretch.
In the traditional design methodology, some designers are used VHDL-
AMS, but using VHDL-AMS mixed signal designs are not being synthesized.
Hence, it is difficult to optimize the system in this method. Hence, a new design
methodology for mixed signal designs is required. As per the requirement, in
this research, a new design methodology for the design of mixed-signal design
I.C has been proposed. To support the new mixed signal design methodology, a
generic MAC using IEEE 754 for 16 bit floating point arithmetic was designed
using which the standard DWT was designed.

40. 40
Here, to design a standard 3-stage DWT, 3 stage filter bank is designed.
The 3 stage filter bank is designed by 3 filter stacks. Each filter stack consists
of one high pass filter and one low pass filter. These high pass and low pass
filters are constituted by the convolution operation. The convolution operation
is constituted by Multiplier Accumulator Content(MAC).
Hence, to design the 3 stage DWT, a 16 bit floating point MAC is
designed first. This 16 bit floating point MAC is generic. It can be used for any
signal processing system. Because, this MAC is the basic building block for any
signal processing system. To simulate the designed mixed signal system (DWT),
a Modelsim PE 10.3c tool is used. This EDA tool won’t support the 16-bit
floating point arithmetic operations. Hence, an user defined IEEE 754 16-bit
floating point math package is developed and then compiled with the standard
IEEE library of the tool.
Hence, it is proven that with the novel design methodology synthesis is
possible. After analyzing synthesis report to increase the speed of operation of
DWT, floating point adder is updated with parallel and pipeline process and
used with novel MAC. This novel MAC is used to design the DWT and observed
that the speed of novel DWT has been increased with little expense of
hardware.

41. 41
Future scope:
In this work, the main target is to design floating point audio CODEC
and to increase the speed of the CODEC. To design the floating point audio
CODEC, the library package is developed and to increase the speed, the
process of serial addition of the floating point adder is updated with parallel
and pipeline processing at the expense of some hardware and power
consumption.
Hence, in the future research by retaining the same speed, the hardware
and power consumption is to be reduced with some new algorithms at the
architectural level like implementing floating point multiplier with Booth
Multiplier or Wallace tree multiplier etc,.
While designing the floating point multiplier, the truncation rounding
mode is applied to the floating point multiplier. If truncation mode is not
applied hardware becomes more. Hence, it should be the trade-off between the
hardware and the truncation rounding mode.
Here, we have developed the floating point audio CODEC mixed-signal
device with novel design methodology by single design flow using VHDL. In
future, any sophisticated design methodology can be used to design such
floating point audio CODEC mixed-signal device.

42. 42
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