This presentation explores exotic efficiency enhancement techniques for RF power amplifiers.

1. Design of Reconfigurable
Radiofrequency Power
Amplifiers
for Wireless Applications
Laurent Leyssenne
Director: Eric Kerhervé
Co-director: Yann Deval
IMS Laboratory – Bordeaux – France
Design group
Microwave Circuits & Systems team
November 27th 2009

2. Intro.. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
2
I. Introduction
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

3. Intro.. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
3
Present trends in modern standards (a)
 Increased throughput in 3G/4G standards.
 More complex modulation scheme
 Increased Peak-to-Average Power Ratio (P.A.P.R.)
 Wider channel bandwidth
 Still high power / range
 E.g.:
 WiMAX: OFDMA, 10MHz channel, 23dBm output power, 12dB PAPR
 LTE: SC-FDMA, 20MHz channel, 24dBm output power, 7/8dB PAPR
 Linearity/Efficiency trade-off
 Battery life-time
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

4. Intro.. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
4
Present trends in modern standards (b)
Source: Chris Rudell - Intel
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

5. Intro.. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
5
Issues related to handset PA design (a)
 Demand of high efficiency.
 Low Bill-Of-Material
 Low die area
 Many stringent requirements in terms of linearity
 Spectral/time masks
 Adjacent Channel Leakage Ratio
 Error Vector Magnitude (max, RMS)
 Max and/or RMS phase error, max. phase steps …
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

6. Intro.. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
6
Issues related to handset PA design (b)
Main and adjacent channels
for a 3.84Mcps HPSK signal (WCDMA)
and ACLR automated computation
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

7. Intro.. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
7
Issues related to handset PA design (c)
HPSK illustration and EVM automated computation
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

8. Intro.. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
8
Fundamental goal of this thesis
 Developing novel smart and compact adaptive PA
architectures on silicon to save battery life-time.
 Low silicon area
 Adaptive mechanisms over wide power dynamic range,
and over wide channel bandwith
 Two adaptive families:
 Discretized PA
 Adaptive bias PA
 Put stress on « low power » integrated analog signal
processing.
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

9. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
9
II. Power Amplifier discretized
reconfigurability
 PA architectures developed in the frame of projects
Medea+ UpperMost and RNRT Asturies.
 Reconfigurable PA for WiFi (802.11n), WiMAX
(802.16e) and WCDMA applications.
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

10. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
10
PA architectures based on Switched power cells
 Stage bypass: non constant–gain technique
 AGC loop is required
 Severe phase hopping must be avoided
 Slow reconfiguration rate (~kHz)
 Parallelized switched power cells: « quasi » constant
gain technique
 Fast reconfiguration rate allowed
 Interpolation allowed over a wide power range.
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

11. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
11
Power stage Bypass architecture (a)
Power stage bypass synoptic
p phase shifter
Power stage
Bypass/drive
r stage
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

12. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
12
Power stage Bypass architecture (b)
2.312.38mm2 BiCMOS
Layout demonstrator
Test Board on Epoxy
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

13. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
13
Power stage Bypass architecture (c)
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

14. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
14
PA architecture based on Parallelized Switched power
cells (a)
Discretized power stage
AM/AM
 Reduced averaged interpolated AM/AM
 AM/AM « analogous » to ADC response
 Quantization magnitude noise results in
distortion
 white noise over the bandwidth
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

15. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
15
PA architecture based on Parallelized Switched power
cells (b)
Discretized power stage
AM/PM
 Reduced averaged interpolated AM/PM
 Quantization phase noise results in
distortion
 pink noise in the carriers’ vicinity
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

16. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
16
PA architecture based on Parallelized Switched
power cells (c)
 Discrete adaptive reconfigurability
 Control bits = digitalized image of envelope/EVM
 Volterra kernels are dynamically modulated by control
bits
 !! Quantization noise is upconverted to RF band
 Importance of Over-Sampling Ratio, and resolution
 + Delta-Sigma technique
 X IN  X IN _ min 
g j  g j,1  Δg j    qn 
X 
 IN _ max  X IN _ min 
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

17. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
17
PA architecture based on Parallelized Switched
power cells (d)
IMD3 level for
IMD3 level for a class A PA a reconfigurable PA
w1 w2 w1 w2
2w1-w2 2w2-w1 2w1-w2 2w2-w1
2w1-w2 w1 w2 2w2-w1
Quantization noise level Quantization noise level for a reconfig. PA
for a basic reconfigurable PA controlled by a DS modulated envelope
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

18. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
18
PA architecture based on Parallelized Switched
power cells (e)
Band-Pass filter:
• Bandwidth fixed by standard
• Selectivity can be increased
Clk at cost of higher in-band losses
Digital
Control filter
word
Decimator channel filter:
• Operates in base-band domain
• Bandwidth can be optimized
(>Bwchannel)
• Selectivity/order can be
increased
at cost of higher latency (>2TS)
• Higher complexity
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

19. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
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PA architecture based on Parallelized Switched
power cells (f)
 Two approaches were considered
 Open-loop topology:
 a Delta-Sigma Built-In Current Sensor probes 2nd order non-linear
currents at PA input
 Modular approach
 Closed-loop topology:
 Reconfigurable PA is inserted in a loop.
 Instantaneous EVM is probed and fed-back to PA.
 Delta-Sigma-like topology
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

20. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
20
First Approach: PA control via DS-BICS
Schematic
Envelope detection
law (IENV)
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

21. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
21
First Approach: PA control via DS-BICS (a)
Schemati Envelope detection law
c
IENV
Built-In Current
Sensor schematic
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

22. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
22
First Approach: PA control via DS-BICS (b)
Schemati Envelope detection law
c
IENV
Built-In Current
Sensor schematic
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

23. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
23
First Approach: PA control via DS-BICS (c)
Schemati Envelope detection law
c
IENV
Built-In Current
Sensor schematic
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

24. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
24
Base-band Synoptic & BICS theoretical response
VBICS vs. XIN response
is analogous to ADC
but linearity degraded
Linearization by non-uniform
current DACs
VBICS 

q n, w  H 0  Yp 2,1  X IN  X IN _ min 
 H0
1   
 DYp 2  X IN  X IN _ min  Yp 2, N  
 X IN _ max  X IN _ min 
 FS 
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

25. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
25
Architecture response for a WLAN transmitter (a)
BICS output spectrum
Chronograms
PA output spectrum
(RF domain)
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

26. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
26
Architecture response for a WLAN transmitter (b)
BICS output spectrum
PA output spectrum
(RF domain)
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

27. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
27
Conclusion on first discrete approach
 Significant efficiency improvement compared with
classA
 Spectral mask requirements are respected in the
channel vicinity …
 …but issues @40MHz from carrier
 Wider BICS bandwidth
 Decimator filter insertion prior to PA
 EVM degradation in the bottom reconfiguration power
corner.
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

28. Intro. Conclusion
PA discretized reconfigurability 2. Gate Bias Envelope Tracking
28
Second approach: PA embedded in an
EVM-cancellation closed-loop
 Non linear Delta-Sigma loop in base-band domain
 PA core + power detector = DAC-like block
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

29. Intro. Conclusion
PA discretized reconfigurability 2. Gate Bias Envelope Tracking
29
Architecture response for a
WLAN transmitter
Improved EVM
ACLR control over
targeted power range
Impact of Resolution on
spectral performances
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

30. Intro. Conclusion
PA discretized reconfigurability 1. Gate Bias Envelope Tracking
30
Conclusion on Second discrete approach
 Significant efficiency improvement compared with
classA
 Spectral mask requirements are respected in the
channel vicinity …
 …but still issues @40MHz from carrier
 Wider loop bandwidth is necessary
 Decimator filter cannot be considered
 EVM degradation in the bottom reconfiguration power
corner is properly handled.
 High VSWR sensitivity:
 Slow control loop is necessary to adjust the average
feedback envelope magnitude and avoid EVM over-estimation.
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

31. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
31
III. Envelope tracking based on
reconfigurable depth adaptive gate Bias
 PA architecture developed in the frame of FP6
MOBILIS European project
 A multi-band Transmitter for DCS/EDGE/WCDMA
applications
 Wide-band differential-to-single PA Module:
 Targeted band: [1710MHz,1980MHz]
 Adaptive bias functionality
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

32. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
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MOBILIS transceiver architecture
Overall
demonstrator
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1

33. Intro. Conclusion
PA discretized reconfigurability Gate Bias Envelope Tracking
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MOBILIS transceiver architecture
Silicon to IPD
wire-bonded connexion
• Very low-Z node!
• Inter-chip gap sensitive
Unit demonstrator
Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1