The document discusses various aspects of input-output organization in computer systems. It describes peripheral devices, input-output interfaces, asynchronous data transfer methods using handshaking, direct memory access, interrupt handling, and input-output processors. The key aspects covered are the interface between the computer and external devices, synchronization for asynchronous data transfer, and different modes of transferring data between memory and I/O devices.

1. 1
Input-Output Organization
Computer Organization Computer Architectures Lab
• Peripheral Devices
• Input-Output Interface
• Asynchronous Data Transfer
• Modes of Transfer
• Priority Interrupt
• Direct Memory Access
• Input-Output Processor
• Serial Communication
INPUT-OUTPUT ORGANIZATION

2. 2
Input-Output Organization
Computer Organization Computer Architectures Lab
PERIPHERAL DEVICES
Input Devices
• Keyboard
• Optical input devices
- Card Reader
- Paper Tape Reader
- Bar code reader
- Digitizer
- Optical Mark Reader
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices
Output Devices
• Card Puncher, Paper Tape Puncher
• CRT
• Printer (Impact, Ink Jet,
Laser, Dot Matrix)
• Plotter
• Analog
• Voice
Peripheral Devices

3. 3
Input-Output Organization
Computer Organization Computer Architectures Lab
* Provides a method for transferring information between internal storage
(such as memory and CPU registers) and external I/O devices
* Resolves the differences between the computer and peripheral devices
- Peripherals - Electromechanical Devices
CPU or Memory - Electronic Device
- Data Transfer Rate
Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals
Some kinds of Synchronization mechanism may be needed
- Unit of Information
Peripherals - Byte
CPU or Memory - Word
- Operating Modes
Peripherals - Asynchronous
CPU or Memory - Synchronous
INPUT/OUTPUT INTERFACES
Input/Output Interfaces

4. 4
Input-Output Organization
Computer Organization Computer Architectures Lab
I/O BUS AND INTERFACE MODULES
Each peripheral has an interface module associated with it
Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
I/O command (Function codes) :
Control Command
Status Command
Input Command
Output Command
Input/Output Interfaces
Processor
Interface
Keyboard
and
display
terminal
Magnetic
tape
Printer
Interface Interface Interface
Data
Address
Control
Magnetic
disk
I/O bus
 Interface Modules : (VLSI Chip)
» PCI
» IDE
» SATA
» RS-232
» USB

5. 5
Input-Output Organization
Computer Organization Computer Architectures Lab
I/O BUS AND MEMORY BUS
* MEMORY BUS is for information transfers between CPU and the MM
* I/O BUS is for information transfers between CPU
and I/O devices through their I/O interface
* Some computers use a common single bus system
for both memory and I/O interface units
- Use one common bus but separate control lines for each function
- Use one common bus with common control lines for both functions
* Some computer systems use two separate buses,
one to communicate with memory and the other with I/O interfaces
Functions of Buses
Physical Organizations
Input/Output Interfaces

6. 6
Input-Output Organization
Computer Organization Computer Architectures Lab
» I/O Bus versus Memory Bus
• 1) Use two separate buses, one for memory and the other for I/O :
– I/O Processor is required (IOP)
• 2) Use one common bus for both memory and I/O but have separate control
lines for each : Isolated I/O
– IN, OUT : I/O Instruction
– MOV or LD : Memory read/write Instruction
• 3) Use one common bus for memory and I/O with common control lines :
Memory Mapped I/O
– MOV or LD : I/O and Memory read/write Instruction
Intel, Zilog
Motorola
* Control Lines
I/O Request, Mem Request, Read/Write
* Control Lines
Read/Write

7. 7
Input-Output Organization
Computer Organization Computer Architectures Lab
ISOLATED vs MEMORY MAPPED I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions
Isolated I/O
Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations
Input/Output Interfaces

8. 8
Input-Output Organization
Computer Organization Computer Architectures Lab
I/O INTERFACE
- Information in each port can be assigned a meaning
depending on the mode of operation of the I/O device
-> Port A = Data; Port B = Command; Port C = Status
- CPU initializes(loads) each port by transferring a byte to the Control Register
-> Allows CPU to define the mode of operation of each port (In, Out, Command, …
-> Programmable Port: By changing the bits in the control register, it is
possible to change the interface characteristics
CS RS1 RS0 Register selected
0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Programmable Interface
Input/Output Interfaces
Chip select
Register select
Register select
I/O read
I/O write
CS
RS1
RS0
RD
WR
Timing
and
Control
Bus
buffers
Bidirectional
data bus
Port A
register
Port B
register
Control
register
Status
register
I/O data
I/O data
Control
Status
CPU I/O
Device
Example of I/O Interface :
4 I/O port : Data port A, Data port B, Control,
Status
Address Decode : CS, RS1, RS0

9. 9
Input-Output Organization
Computer Organization Computer Architectures Lab
ASYNCHRONOUS DATA TRANSFER
Synchronous - All devices derive the timing
information from common clock line
Asynchronous - No common clock
Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted
Strobe pulse
- A strobe pulse is supplied by one unit to indicate
the other unit when the transfer has to occur
Handshaking
- A control signal is accompanied with each data
being transmitted to indicate the presence of data
- The receiving unit responds with another control
signal to acknowledge receipt of the data
Synchronous and Asynchronous Operations
Asynchronous Data Transfer
Two Asynchronous Data Transfer Methods
Asynchronous Data Transfer

10. 10
Input-Output Organization
Computer Organization Computer Architectures Lab
* The strobe may be activated by either the source or the destination unit
STROBE CONTROL
Source
unit
Destination
unit
Data bus
Strobe
Data
Strobe
Valid data
Block Diagram
Timing Diagram
Source-Initiated Strobe
for Data Transfer
Source
unit
Destination
unit
Data bus
Strobe
Data
Strobe
Valid data
Block Diagram
Asynchronous Data Transfer
Destination-Initiated Strobe
for Data Transfer
Timing Diagram

11. 11
Input-Output Organization
Computer Organization Computer Architectures Lab
HANDSHAKING
Strobe Methods
Source-Initiated
The source unit that initiates the transfer has
no way of knowing whether the destination unit
has actually received data
Destination-Initiated
The destination unit that initiates the transfer
no way of knowing whether the source has
actually placed the data on the bus
To solve this problem, the HANDSHAKE method
introduces a second control signal to provide a Reply
to the unit that initiates the transfer
Asynchronous Data Transfer

12. 12
Input-Output Organization
Computer Organization Computer Architectures Lab
SOURCE-INITIATED TRANSFER USING HANDSHAKE
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
Block Diagram
Timing Diagram
Accept data from bus.
Enable data accepted
Disable data accepted.
Ready to accept data
(initial state).
Sequence of Events
Place data on bus.
Enable data valid.
Source unit Destination unit
Disable data valid.
Invalidate data on bus.
Source
unit
Destination
unit
Data bus
Data accepted
Data bus
Data valid
Valid data
Data valid
Data accepted
Asynchronous Data Transfer

13. 13
Input-Output Organization
Computer Organization Computer Architectures Lab
DESTINATION-INITIATED TRANSFER USING HANDSHAKE
* Handshaking provides a high degree of flexibility and reliability because the
successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism
Block Diagram
Timing Diagram
Source
unit
Destination
unit
Data bus
Ready for data
Data valid
Sequence of Events
Place data on bus.
Enable data valid.
Source unit Destination unit
Ready to accept data.
Enable ready for data.
Disable data valid.
Invalidate data on bus
(initial state).
Accept data from bus.
Disable ready for data.
Ready for data
Data valid
Data bus
Valid data
Asynchronous Data Transfer

14. 14
Input-Output Organization
Computer Organization Computer Architectures Lab
ASYNCHRONOUS SERIAL TRANSFER
- Employs special bits which are inserted at both
ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.
A character can be detected by the receiver from the knowledge of 4 rules;
- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected
by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last character , a Stop Bit is detected when
the line returns to the 1-state for at least 1 bit time
The receiver knows in advance the transfer rate of the
bits and the number of information bits to expect
Four Different Types of Transfer
Asynchronous Serial Transfer
Start
bit
(1 bit)
Stop
bits
Character bits
1 1 0 0 0 1 0 1
(at least 1 bit)
Asynchronous Data Transfer

15. Computer System Architecture Dept. of Info. Of Computer.
Chap. 11 Input-Output Organization
Modes of Transfer
 The final target of I/O data is memory of the system
 Memory data transfer to and from peripherals
1) Programmed I/O
2) Interrupt-initiated I/O
3) Direct Memory Access (DMA)
4) I/O Processor (IOP)
 Example of Programmed I/O
 Interrupt-initiated I/O
1) Non-vectored : fixed branch address
2) Vectored : interrupt source supplies the branch address (interrupt vector)
Interface
CPU
I/O
device
Data register
Status
register
F
Data bus
I/O write
I/O read
Address bus
Data accepted
Data valid
I/O bus
F = Flag bit
Read status register
Check flag bit
Read data register
Transfer data to memory
Continue
with
program
Flag
Operation
complete ?
= 0
= 1
yes
no

16. Computer System Architecture Dept. of Info. Of Computer.
Chap. 11 Input-Output Organization
n Priority Interrupt
 Priority Interrupt
l Identify the source of the interrupt when several sources will request service
simultaneously
l Determine which condition is to be serviced first when two or more requests
arrive simultaneously
» 1) Software : Polling
» 2) Hardware : Daisy chain, Parallel priority

17. Computer System Architecture Dept. of Info. Of Computer.
Chap. 11 Input-Output Organization
n Direct Memory Access (DMA)
 DMA
l DMA controller takes over the buses to manage the transfer directly between the
I/O device and memory
CPU
BR
BG
DBUS
WR
ABUS
RD
Bus request
Bus grant
Address bus
Write
Read
Data bus
High-impedance
(disable)
when BG is
enabled
DMA
Controller
BR
BG

18. Computer System Architecture Dept. of Info. Of Computer.
Chap. 11 Input-Output Organization
 DMA Transfer (I/O to Memory)
l 1) I/O Device sends a DMA request
l 2) DMAC activates the BR line
l 3) CPU responds with BG line
l 4) DMAC sends a DMA acknowledge
to the I/O device
l 5) I/O device puts a word in the data
bus (for memory write)
l 6) DMAC write a data to the address
specified by Address register
l 7) Decrement Word count register
l 8) if Word count register = 0
EOT interrupt
l 9) if Word count register  0
DMAC checks the DMA request from
I/O device
I/O
Peripheral
device
DMA acknowledge
Address
select
CPU
Interrupt
Address Data
BG
BR
RD WR
Random access
memory) RAM(
Address Data
RD WR
Direct memory
access) DAM(
controller
Interrupt
Address Data
RD WR
BG
RS
DS
BR
DMA request
Read control
Write control
Address bus
Data bus

19. Computer System Architecture Dept. of Info. Of Computer.
Chap. 11 Input-Output Organization
 Transfer Modes
l 1) Burst transfer :
l 2) Cycle stealing transfer :
 DMA Controller ( Intel 8237 DMAC )
l DMA Initialization Process
» 1) Set Address register :
n memory address for read/write
» 2) Set Word count register :
n the number of words to transfer
» 3) Set transfer mode :
n read/write,
n burst/cycle stealing,
n I/O to I/O,
n I/O to Memory,
n …..
» 4) DMA transfer start
» 5) EOT (End of Transfer)
n Interrupt
Control
logic
CS
Data bus
buffers
Control register
Data bus
DMA select
Internal
bus
RS
Interrupt
BG
BR
RD
WR
Register select
Read
Write
Bus request
Bus grant
Interrupt
Address register
Word count register
Address bus
buffers
Address bus
DMA request
DMA Acknowledge
to I/O device

20. Computer System Architecture Dept. of Info. Of Computer.
Chap. 11 Input-Output Organization
n Input-Output Processor (IOP)
 IOP :
l Communicate directly with all I/O devices
l Fetch and execute its own instruction
» IOP instructions are specifically designed to facilitate I/O transfer
» DMA Controller (DMAC) must be set up entirely by the CPU
l Designed to handle the details of I/O processing
 Command
l Instruction that are read from memory by an IOP
» Distinguish from instructions that are read by the CPU
» Commands are prepared by experienced programmers and are stored in memory
» Command word = IOP program
Memory unit
Central Processing
unit (CPU)
Input-output
processor (IOP)
Memory
bus
PD PD
PD
PD
Peripheral devices
I/O bus

21. Computer System Architecture Dept. of Info. Of Computer.
Chap. 11 Input-Output Organization
 CPU - IOP Communication :
l Memory units acts as a message center :
» each processor leaves information for the other
CPU operations IOP operations
Send instruction
to test IOP path
Transfer status word
to memory location
If status OK. , send
start I/O instruction
to IOP
Access memory for
IOP program
CPU continues with
another program
Conduct I/O transfer
using DMA ; prepare
status report
I/O transfer completed
interrupt CPU
Request IOP status
Transfer status word
to memory location
Check status word
for correct transfer
Continue
Message Center
IOP Program
CPU Program