Introduction to Interfacing Technique


Published on

A well designed flexible interfaces will be required to ensure compatibility and extend design options.

Published in: Education, Technology, Business
  • Be the first to comment

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

Introduction to Interfacing Technique

  1. 1. <ul><li>DEFINITION AND COMPONENTS OF INTERFACE </li></ul><ul><li>CLASSIFICATION OF DATA TRANSFER SCHEMES: </li></ul><ul><li> PROGRAM CONTROLLED TRANSFER </li></ul><ul><li> INTERRUPT DRIVEN TRANSFER </li></ul><ul><li> PERIPHERAL CONTROL TRANSFER </li></ul>CHAPTER 1 Introduction to Interfacing Techniques & Data Transfer Schemes
  2. 2. Interfacing <ul><li>Why? </li></ul><ul><ul><li>microcomputer revolution will continue into the future </li></ul></ul><ul><ul><li>many will be required to specify and integrate microprocessors into products or systems in their own disciplines </li></ul></ul><ul><ul><li>well-designed flexible interfaces will be required to ensure compatibility with other equipments and to extend design options </li></ul></ul><ul><ul><li>interfaces are the last items to be seriously considered in the race of new technology </li></ul></ul><ul><ul><li>it deals with the systematic study of microprocessor interfaces and their applications in many diversified fields </li></ul></ul>
  3. 3. <ul><li>In this subject students learn how to interface microprocessors, and hence microcomputers and other related equipments, to external digital or analog devices. </li></ul>
  4. 4. μP <ul><li>progress has advanced at a pace perhaps unparallel in scientific history since its introduction in 1971 </li></ul><ul><li>there have been four generations of microprocessors </li></ul><ul><li>the number of devices per chip has increased by a factor of 2000, the clock frequency by a factor of 1000 </li></ul><ul><li>the overall throughput of the microprocessor has increased by hundred or several hundreds of magnitudes </li></ul>
  5. 5. <ul><li>Developing a microprocessor (μP)-based system represents one of the most difficult tasks that can confront an engineer. Advances in microprocessor architectures and capabilities are forcing changes in development systems and the ways in which they develop microcode instructions. Also, all μP architectures are not created equal when it comes to providing designers with the tools they need for effective systems resource management. </li></ul>
  6. 6. <ul><li>Therefore, a well designed flexible interfaces will be required to ensure compatibility and extend design options. </li></ul>
  7. 7. Definitions: <ul><li>Microprocessor - The central unit of a microcomputer that contains logical elements for manipulating data and performing arithmetic or logical operations. A single chip may contain RAM, ROM, and PROM memories, clocks, and interfaces for memory and I/O device. </li></ul><ul><li>Microprogramming - A method for controlling the operation of the CPU in which each complete instruction starts the execution of a sequence of instructions, called microinstructions, which are at a more elementary level. </li></ul><ul><li>Multiprocessor - As defined by ANSI, it is a computer employing two or more processing units under integrated control. Although this definition may be correct, it is not complete enough to be too helpful. </li></ul><ul><li>There are other important features that include both hardware and software. A multiprocessor will be defined as a system with: a) two , or more processing units, b)shared memory, and c) shared I/0. </li></ul>
  8. 8. Interface Definitions <ul><li>Interface </li></ul><ul><li>a shared boundary between system elements defined by common physical interconnection characteristics, signal characteristics, and meanings of interchanged signals. </li></ul><ul><li>is a tool and concept that refers to a point of interaction between components, and is applicable at the level of both hardware and software. </li></ul><ul><li>allows a component to function independently while using interfaces to communicate with other components via an input/output system and an associated protocol. </li></ul>
  9. 9. Cont… <ul><li>Interface Device </li></ul><ul><li>A device that meets the interface specifications on one side of an interface. </li></ul><ul><li>The term is usually applied to a device through which a system or equipment works to meet interface specifications. </li></ul>
  10. 10. <ul><li>Interface Specification </li></ul><ul><li>a set of technical requirements that must be met at an interface. </li></ul><ul><li>Direct Memory Access </li></ul><ul><li>A technique that permits a peripheral device to enter or extract blocks of data from the memory without involving the central processing unit. In some cases, the CPU can perform other functions while the data transfers occur. </li></ul>
  11. 11. Components of Interface The interfacing devices should make use of standard data transfer schemes for the efficient exchange of data. Interface Signals Interface Signals Interfacing Device (ID 1) Interfacing Device (ID 2) Interfacing Standards & Converters
  12. 12. Data Transfer Schemes <ul><li>refers to the method of data transfer between the processor and peripheral devices: </li></ul><ul><li>microprocessor and memory </li></ul><ul><li>microprocessor and I/O devices </li></ul><ul><li>memory and I/O devices </li></ul>For effective data transfer between these devices, the timing parameters of the devices should be matched. But most of the devices have incompatible timings.
  13. 13. Two Categories: <ul><li>1. Programmed data transfer. </li></ul><ul><li>2. Direct memory access data transfer. </li></ul>
  14. 14. Programmed Data Transfer <ul><li>a memory resident routine (subroutine) requests the device for data transfer to or from one of the processor register </li></ul><ul><li>scheme is used when a relatively small amount data are to be transferred </li></ul><ul><li>usually one byte or word of data is transferred at a time </li></ul>Examples of devices using parallel data transfer are ADC,DAC, Hex-keyboard, 7-segment LED's, etc.
  15. 15. 3 Types of Programmed Data Transfer <ul><li>The scheme can be further classified into the following: </li></ul><ul><li>1. Synchronous data transfer scheme. </li></ul><ul><li>2. Asynchronous data transfer scheme. </li></ul><ul><li>3. Interrupt driven data transfer scheme. </li></ul>
  16. 16. Direct Memory Access (DMA) Data Transfer <ul><li>the processor is forced to hold state by an I/O device until the data transfer between the device and the memory is completed </li></ul><ul><li>the processor does not execute any instructions during the hold period </li></ul><ul><li>is used for large block of data transfer between I/O device and memory </li></ul>Typical examples of devices using DMA are CRT controller, floppy disk, hard disk, high speed line printer, etc
  17. 17. 3 Types of DMA Data Transfer <ul><li>The schemes are: </li></ul><ul><li>1. Cycle stealing DMA. </li></ul><ul><li>2. Block or Burst mode DMA. </li></ul><ul><li>3. Demand transfer mode DMA. </li></ul>
  18. 18. Types of Data Transfer Schemes
  19. 19. PROGRAM CONTROLLED TRANSFER <ul><li>the transfer of data is completely under the control of the microprocessor program </li></ul><ul><li>data transfers can take place synchronously or asynchronously </li></ul>an i/o operation takes place only when an i/o instruction is encountered in the execution of the program synchronous transfers mean transfers occurring at the same time asynchronous transfers mean transfers taking place at irregular intervals Data transfers between the microprocessor and the peripherals are primarily asynchronous
  20. 20. Program controlled data transfers can take place under several conditions <ul><li>Unconditional </li></ul><ul><li>Polling </li></ul><ul><li>Interrupt </li></ul><ul><li>With ready signal </li></ul><ul><li>With handshake signals </li></ul>assumes that a peripheral is always available kept in a loop to check whether data are available interrupted from its normal execution of program by an I/O device, when the latter is ready when peripheral response time is slower than the microprocessor execution time, READY signal is used handshake signals are signals exchanged prior to data transfer
  21. 21. Synchronous data transfer scheme <ul><li>is the simplest of all data transfer schemes </li></ul><ul><li>the processor does not check the readiness of the device </li></ul><ul><li>I/O device or peripheral should have matched timing parameters </li></ul>the mode-O input or output in 8155 or 8255 is an example of synchronous data transfer
  22. 22. Asynchronous Data Transfer Schemes <ul><li>is employed when the speed of processor and I/O device does not match </li></ul><ul><li>the processor ends a request to the device for read/write operation </li></ul><ul><ul><li>then the processor keeps on polling the status of the device </li></ul></ul><ul><ul><li>once the device is ready, the processor executes a data transfer instruction to complete the process </li></ul></ul><ul><ul><li>to implement this scheme, the device should provide a signal which may be tested by the processor to ascertain whether it is ready or not </li></ul></ul>handshake data transfer without interrupt (mode-l and mode-2) of8155 or 8255 is an example
  23. 23. Interrupt Driven Data Transfer Scheme <ul><li>is the best method of data f transfer for effectively utilizing the processor time </li></ul>the processor first initiates the I/O device for data transfer. After initiating the device, the processor will continue the execution of instructions in the program. Also at the end of an instruction the processor will check for a valid interrupt signal. If there is no interrupt then the processor will continue the execution. When the IO device is ready, it will interrupt the processor. On receiving an interrupt signal, the processor will complete the current instruction execution and saves the processor status in stack. Then the processor call an interrupt service routine (ISR) to service the interrupted device.
  24. 24. <ul><li>when the processor call an interrupt service routine (ISR) to service the interrupted device. At the end of ISR the processor status is retrieved from stack and the processor starts executing its main program. </li></ul>
  25. 25. PROGRAM CONTROLLED DMA TRANSFERS <ul><li>In DMA transfer, the microprocessor is forced to hold on by an I/O device until the data transfer is complete </li></ul>In programmed data transfer, a memory resident routine requests the device for data transfer to and from one of the microprocessor registers Programmed data are used when relatively small amounts of data are transferred using relatively slow I/O devices such AID, D/A converters, and peripheral floating point arithmetic unit. DMA is preferred when a large block of data is to be transferred. This scheme is generally employed for transferring data between the microprocessor and peripheral mass storage devices like hard disk or a high-speed line printer.
  26. 26. INTERRUPT PROCESS IN MICROCOMPUTERS <ul><li>8085 </li></ul><ul><li>FIVE pins on the chip for implementing the interrupt process </li></ul><ul><li>PIN NO Name </li></ul><ul><li>6 TRAP </li></ul><ul><li>7 RST 7.5 </li></ul><ul><li>8 RST 6.5 </li></ul><ul><li>9 RST 5.5 </li></ul><ul><li>10 INTR. </li></ul>