Srinivas Kotha is seeking a position as a Physical Design Engineer. He has a master's degree in VLSI System Design and experience implementing physical design projects including block-level layout of a torpedo subsystem and timing analysis using synthesis tools. His skills include Verilog, physical design flows, timing closure, and Tcl scripting. He completed projects in image compression, FPGA memory testing, and physical design challenges like power planning and DRC/LVS fixes.

1. Profile Information
Name: Srinivas Kotha Email: ksrinivasvlsi@gmail.com
Phone: 8123419352 Address: #1239
32 G'Cross, 26 th Main
4 T Block, Jayanagar
Bangalore
Karnataka-560041
Career Objective
Looking for an opportunity to work as a Physical Design Engineer in a dynamic work environment.
Core Competancy
• Good understanding of MOS Transistors and Circuit Theory fundamentals
• Good knowledge of Digital Design concepts
• Good knowledge of Verilog HDL coding
• Good knowledge of IC fabrication process
• Well versed with Netlist - GDS II flow
• Good at Timing Analysis and Block Level Timing Closure
• Exposure to Technology by taking additional training in Physical Design with a Hands on Project
• Implemented a VLSI project during my Post Graduation
• Good in scripting with Tcl to handle various requirements of design
• Good working knowledge of Linux Operating System
Education Details
Degree Discipline School/College
Year of
passing
Aggregate
PG
Diploma
Advanced Diploma in ASIC
Design
RV-VLSI Design Center 2015 -
Master
Degree
VLSI System Design
Aurora's Technological and
Research Institute
2013 72.56
Degree Electronics and Communication
Sree Chaitanya College of
Engineering
2009 68.23
PUC - Loyola Junior College 2005 82.40
SSLC - Loyola High School 2003 82.00
Project Details
Project Title 180 nm Block Level Physical Design of Torpedo Sub-system
Institue Name RV-VLSI Design Center
Project
Description
Block level Physical Design of Torpedo consisting a Macro Count of 32 and a
Standard Cell Count of 43k with a Supply Voltage of 1.8V, operating on a Clock
Frequency of 400 MHz incorporated with 5 Clocks. DFT is inserted.
Technology Node: 180 nm
Tools Used IC Compiler for APR ,Prime Time for STA , Hercules and Calibre for DRC/LVS
Challenges
Power Planning to get IR Drop (VDD + VSS) less than 5% of 1.8V. Macro
Placement with Congestion free Floorplan. Fixing Timing violations after each
step. Fixing hold violations after CTS. Fixing Antenna Violation and DRC/LVS
Errors.

2. Project Title Timing Analysis using STA for Various Cases
Institue Name RV-VLSI Design Center
Project
Description
Generation and analysis of timing reports of different designs in various
scenarios with MCMM . Understanding the effect of clock uncertainity on
timing. Analysis of CRPR. Understanding various techniques to fix violation.
Tools Used Synopsys Prime Time
Challenges
Dealing with false paths and multi-cycle paths. Analysis of latch based designs.
Analysis of Signal Integrity/Cross Talk.
Project Title Scripting with Tcl
Institue Name RV-VLSI Design Center
Project
Description
Writing Tcl scripts to various design examples. Extracting information from IC
Compiler database. Analysis of Tcl scripts for the tool templates of Floor plan,
Power plan, Placement,CTS,Routing and Customized them to the flow.
Tools Used Tclsh, Tcl - Tutor, Synopsys IC Compiler
Challenges Writing Tcl scripts for design examples.
Project Name SAR Image Compression Based on Discrete Wavelet Transform
Institute Name Sree Chaitanya College of Engineering
Project
Description
The objective of the project is to reduce the cost of data storage and
transmission in relatively slow channels.
Challenges
Getting the samples of Synthetic Aperture Radar Image. Texture analysis of
SAR Image.
Tools MATLAB
Project Name
FPGA Based Complex Test Pattern Geneartion for High Speed Fault Diagnosis
of FPGA Memory Blocks
Institute Name Aurora's Technological and Research Institute
Project
Description
The objective of the project is to test the working of Block RAMs on FPGA
device which is very useful in developing the applications for Defence and
Military.
Challenges
Analysis of Fault Models. Finding of efficient algorithms for sensitive blocks
like memories. Fault Insertion.
Tools Xilinx ISE