This document is a resume for Blake Xu summarizing his background and experience. He has expertise in C/C++ and Verilog programming along with experience in testing and failure analysis. His technical skills include software languages like C/C++ and Python as well as hardware languages like Verilog and SystemVerilog. He has worked as a test engineer and interned as a test engineer and IC board designer. He holds a Master's degree in Electrical and Electronics Engineering and a Bachelor's degree in Applied Physics.

1. Blake Xu
Baton Rouge Dr., San Jose, CA, 95133  (408)921-9758  BlakeXu1989@me.com
SUMMARY
Expert C/C+, Verilog programmer. Experience in Testing and Failure Analysis. Very thorough knowledge of JTAG Boundary Scan with IEEE 1149 protocol, ASIC Design Flow, CMOS Circuit Design, Device Physics, ARM M3/M4 Program, SRAM Design. Familiar with HDD, SSD System, IC Board Design.
OBJECTIVE
Seeking a full-time position as an engineering that utilize my programing skills, hardware background and failure analysis experience
TECHNICAL SKILLS
Software Programing Languages: C/C++, Python, BAT script
Hardware Programing Languages: Verilog, SystemVerilog, Hspice
Operation Systems: Windows, Mac OS, MS DOS, UNIX, Sun Workstation (SunOS, Solaris)
Software: Microsoft Visual Studio, Cadence Virtuoso, Synopsis Design Vision, Encounter, Modelsim, QPST, QXDM, Wireshark, Matlab, Protel
WORK EXPERIENCE
Test Engineer Sep.2014 – Present
Foxconn, San Jose, CA
 Implemented testing, calibration and distortion with Automatic Test Equipment for optical network products
 Accomplished board level failure analysis by using DMM, network analyzer and spectrum analyzer
Test Engineer Intern Dec.2012 – Aug.2013
ZTE INC., Plano, TX
 Executed test cases to debug the software of mobile devices using Windows bat commands to invoke Android shell commands
 Analyzed mobile phone log by QXDM, QPST and telecommunication package logs by Wireshark
 Obtained experience of 3G/4G/LTE logs analysis and AT&T 10776 test cases package by studying form other engineer  Received great evaluation for good motivation about self-learning of Windows BAT and Android shell command in order to improve the efficiency of test process
IC Board Designer & Programmer Intern Oct.2010 – Aug.2011 Chinese Academy of Sciences: Sciences and Application Research Center, Beijing, China
 Designed a USB controlled circuit board to delay multi-channel TTL signal for rear Single-proton Detector (SPD)
 Programmed USB port driver
 Implemented PCB schematic on Protel, control program using Keil C and MFC(C++), and accomplished USB communication coding based on USB 1.1 mode
 Completed B.S. graduation thesis based on this project and gained very high grade of 93/100(3rd of class)

2. EDUCATION
M.S. Electrical and Electronics Engineering, GPA:3.79 (Top 20% of major) Dec.2013
The University of Texas at Dallas, TX
B.S. Applied Physics, Grade:83.5/100 (Top 20% of major) Jul.2011
Beijing University of Posts and Telecommunications, China
ACADEMIC PROJECTS Verilog Programming Project (ModelSim/Design Vision/Encounter) Sep. 2011 – Dec.2011  Implemented the front-end design of a high-speed and low power Mini Stereo Digital Audio Processor (MSDAP) based on professor algorithm with optimal POT coefficients FIR digital filtering structure  Contributed structure build and all programming work in this project generated chip layout with Design Vision  Achieved 5% less area and power consumption compare with other products through perfect architecture design and coding
ARM Programming Project (C++ /MFC/ CCSv5) Sep. 2012 –Dec.2012
 Implemented the simulation of two-dimensional balls collision program on TI Launchpad(ARM Cortex-M4) using C++  Structured USB connection between broad and PC for transferring data packages of balls’ position velocity base on the board example code, completed the ball collision animation on PC by using MFC platform  Obtained highly evaluation by good PC interface and great board simulation speed
Design Project of 1024 bits SRAM (Cadence, Hspice) Jun.2013 – Aug.2013  Developed a 1024bit SRAM base on TSMC 130nm process, generated schematic and physical layout with Cadence Virtuoso and verified by Calibre DRC and LVS, examined read write performance using Hspice, accomplishing all works 50% faster than most of other students
 Received grade in top 15%, fulfilling this project individually which is normally finished by 2 people
RELATIVE COUTSES COMPLETED
 ASIC Design Grade A in UTD
 VLSI Design Grade A in UTD
 Advanced VLSI Design Grade A- in UTD
 Advanced Digital Logic Grade A in UTD
 Microprocessor System Grade A- in UTD
 Digital Signal Process I Grade A in UTD
 C++ Programming Language Grade A in BUPT