1. RESUMÉ
Name: PAVAN TEJA DAMA Email: pavantejadama@gmail.com
Phone: +91-9703978970
Career Objective
Seeking a challenging and enriching position in layout design where I can use my
knowledge towards organization goals that offers professional growth.
Core Competency
 Familiar with ASIC Design, Full-Custom Design flow & IC Fabrication process.
 Hands on Experience in Standard cell layout design, Analog layout design and
Memory layout designs with advanced technology nodes.
 Hands on experience with Industry standard EDA tools like IC Studio, PYXIS,
Calibre, Questa SIM and DC Shell.
 Practical Knowledge on IC physical verification like DRC, LVS, Compatibility rules.
 Thorough knowledge on Digital electronics, Semiconductor Physics, CMOS Concepts
and Second Order Effects.
 Familiar with DFM concepts like Latch-up, Antenna effect, electro-migration, Metal
density rules and ESD.
 Knowledge on Layout Proximity Effects like WPE, LOD & PSE.
 Basic Knowledge on Analog Circuit Design, FINFET, Double pattering, Shallow
Trench Isolation Process, characterization at different PVT corners.
 Familiar with SRAM Architecture and Analog matching techniques like
interdigitization & Common Centroid concepts.
 Working Knowledge of Linux/Unix operating system and Perl Scripting.
Academic Education
Feb 2016 – Aug 2016 RV-VLSI Design Center, Bangalore, Karnataka
PG Diploma in ASIC Design
2013-2015 Sri Venkataswara Engineering College, Tirupati, AP
M.Tech in VLSI design with 77%
2008-2012 CR Engineering College, Tirupati, AP
B.Tech in ECE with 71%
2006-2008 Sri Chaitanya College, Tirupati, AP
Intermediate in MPC with 90%
2005-2006 Sudaha High School, Tirupati, AP
SSC with 70%

2. Work Experience
RV-VLSI Design Center, Bangalore, Karnataka. Feb. 2016 – Aug. 2016
Project Trainee in ASIC Design (Full Custom) (Full Time)
Conquer Techno Solutions, Tirupati, AP. Aug. 2014 – Feb. 2015
Project Trainee in VLSI (Part Time)
Academic Achievements
 Attended workshop on ADVANCEMANTS IN VLSI at SVCE, Tirupati in 2015.
 Secured II prize for ACCELEROBOT in TECHMEET national workshop at CREC,
Tirupati in 2012.
 Attended workshop on ROBO-GRAVITY & conducted at SRM University, Chennai
in 2011.
 Attended training class on VLSI SIGNAL PROCESSING at IIT KHARGPUR in
2010.
Domain Project Details
Project Title SRAM Memory layout in 28nm Technology
Institute Name RV-VLSI Design Center, Bangalore, India
Project
Description
Project involves floor planning and layout designing of SRAM Blocks,
The Designed blocks are Sense amp, precharge & Mux, data-in and data-
out, Pre-Decoder, Final Decoder, Control block, Scan block.
Challenges
Faced
-Designing an optimized and less parasitic layout following design
Constrains make my work challenging.
-Floor planning of Control Block was challenging because of it repetitive
structure.
-Fixing pin placements in each block and then designing Layout was
challenging.
-Top level routing was challenging
Tools used
IC Studio, PYXIS Circuit and Layout Editor (Mentor Graphics), Calibre
for Physical Verification (DRC and LVS)
Project Title Analog Layout design on 180nm process
Institute Name RV-VLSI Design Center, Bangalore, India
Project
Description
Two stage operational amplifier (Op-Amp) which has differential
amplifier, bias circuit and current source.
Challenges
Faced
-Understanding of centroid, dummy poly, shielding, guard ring concepts
and applying those concepts to making floor planning was a challenging.
-Floorplanning of that many fingered transistors and achieving matching at
critical transistors through floorplanning was challenging.
-Routing for such a complex analog design was challenging.
Tools used
IC Studio, PYXIS Circuit and Layout Editor (Mentor Graphics), Calibre
for Physical Verification (DRC and LVS)

3. Project Title Design of 9T standard cells Layouts in 28nm and 90nm
Institute Name RV-VLSI Design Center, Bangalore, India
Project
Description
To deliver DRC/LVS clean layout for basic logic circuits from Transistor
level netlist and schematic.
Challenges
Faced
-Placing polys and contacts on poly pitches which restricts majority of
routing area was challenging to do.
-Routing without using poly and higher metal than metal-1 was difficult.
-Due to fix area tap placement was difficult.
Tools used
IC Studio, PYXIS Circuit and Layout Editor (Mentor Graphics), Calibre
for Physical Verification (DRC and LVS)
M.Tech Project Details
Project Title Improved LMS & RLS Adaptive Filter With Low Adaption Delay
Institute Name SV College, Tirupati, India
Project
Description
Designed an improved architecture for LMS and RLS adaptive filter which
has area, power and delay advantage then previews architectures.
Tools used Xilinx ISE 10
Challenges
Faced
-Optimizing all three main factors (Area, Power and Delay) in a Design
was a challenging.
-Using xilinx tool for simulation RTL Code was challenging because it is
complex and has many steps to run a Design.
Personal Details
Name : D.PAVAN TEJA
Father Name : D.SUBRAMANYAM
Date of Birth : 12-06-1991
Sex : Male
Languages Known : English, Telugu and Hindi
Address for Communication : 3-5-135, Adrathi Lane, Near Bazzar Street, Tirupati.
Declaration
I hereby declare that the above particulars furnished by me are true to the best of my
knowledge and belief.
Place: Bangalore
Date: (PAVAN TEJA DAMA)