5. Write the VHDL code for the state machine. library ieee; use ieee.std_logic_1164.all; entity state_machine5 is port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end state_machine5; architecture arc_ state_machine5 of state_machine5 is type state_type is (A,B,C,D); signal present_state,next_state:state_type; begin process (clk,reset) if (R=’1’) then present_state<=A; elsif (rising_edge(clk) then present_state<=next_state; end if; end process; process (present_state,S,T) begin case present_state is when A => if (S=’1’ or T=’1’)then next_state<=A; elsif (S=’0’)then next_state<=C; elsif (S=’1’ or T=’0’) next_state<=B; else next_state<=A; end if; when B => if (R=’0’)then next_state<=B; elsif (R=’1’)then next_state<=C; else next_state<=A; end if; when C => if (R=’0’ and T=’1’ )then next_state<=D; elsif (R=’1’ and T=’0’)then next_state<=A; elsif((R=’0’andT=’0’)or R=’1’and T=’1’) next_state<=B; else next_state<=A; end if; when D => next_state<=A; end case; end process; end arc_ state_machine5; Test bench: entity test_sm is end test_sm; architecture arc_test_sm of test_sm is component state_machine5 port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end component; signal clk: std_logic :=’0’; signal R: std_logic :=’1’; signal S: std_logic :=’0’; signal T: std_logic :=’0’; constant clk_period : time := 5 ns; begin test1: state_machine5 port map ( clk,R,S,T); process begin clk<=’0’; wait for clk_period/2; clk<=’1’; wait for clk_period/2; end process; process begin wait for 5 ns; R<=’0’; S<=’0’;T<=’0’; wait for 5 ns; S<=’0’;T<=’1’; wait for 5 ns; R<=’1’; wait for 5 ns; S<=’1’;T<=’0’; wait for 5 ns; S<=’1’;T<=’1’; end process; end arc_test_sm; Solution 5. Write the VHDL code for the state machine. library ieee; use ieee.std_logic_1164.all; entity state_machine5 is port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end state_machine5; architecture arc_ state_machine5 of state_machine5 is type state_type is (A,B,C,D); signal present_state,next_state:state_type; begin process (clk,reset) if (R=’1’) then present_state<=A; elsif (rising_edge(clk) then present_state<=next_state; end if; end process; process (present_state,S,T) begin case present_state is when A => if (S=’1’ or T=’1’)then next_state<=A; elsif (S=’0’)then next_state<=C; elsif (S=’1’ or T=’0’) next_state<=B; else next_state<=A; end if; when B => if (R=’0’)then next_state<=B; elsif (R=’1’)then next_state<=C; else next_state<=A; end if; when C => if (R=’0’ and T=’1’ )then next_state<=D; elsif (R=’1’ and T=’0’)then next_state<=A; elsif((R=’0’andT=’0’)or R=’1’and T=’1’) next_state<=B; else next_state<=A; end if; when D => next_state<=A; end case; end process; end arc_ state_machine5; Test bench: entity test_sm is end test_sm; architecture arc_test_sm of test_sm is component state_machine5 port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end component; signal clk: std_logic :=’0’; signal R: std_logic :=’1’; signal S: std_logic :=’0’; signal T: std_logic :=’0’; .