5.Write the VHDL code for the state machine.library ieee;use i.pdf
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5. Write the VHDL code for the state machine. library ieee; use ieee.std_logic_1164.all; entity state_machine5 is port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end state_machine5; architecture arc_ state_machine5 of state_machine5 is type state_type is (A,B,C,D); signal present_state,next_state:state_type; begin process (clk,reset) if (R=’1’) then present_state<=A; elsif (rising_edge(clk) then present_state<=next_state; end if; end process; process (present_state,S,T) begin case present_state is when A => if (S=’1’ or T=’1’)then next_state<=A; elsif (S=’0’)then next_state<=C; elsif (S=’1’ or T=’0’) next_state<=B; else next_state<=A; end if; when B => if (R=’0’)then next_state<=B; elsif (R=’1’)then next_state<=C; else next_state<=A; end if; when C => if (R=’0’ and T=’1’ )then next_state<=D; elsif (R=’1’ and T=’0’)then next_state<=A; elsif((R=’0’andT=’0’)or R=’1’and T=’1’) next_state<=B; else next_state<=A; end if; when D => next_state<=A; end case; end process; end arc_ state_machine5; Test bench: entity test_sm is end test_sm; architecture arc_test_sm of test_sm is component state_machine5 port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end component; signal clk: std_logic :=’0’; signal R: std_logic :=’1’; signal S: std_logic :=’0’; signal T: std_logic :=’0’; constant clk_period : time := 5 ns; begin test1: state_machine5 port map ( clk,R,S,T); process begin clk<=’0’; wait for clk_period/2; clk<=’1’; wait for clk_period/2; end process; process begin wait for 5 ns; R<=’0’; S<=’0’;T<=’0’; wait for 5 ns; S<=’0’;T<=’1’; wait for 5 ns; R<=’1’; wait for 5 ns; S<=’1’;T<=’0’; wait for 5 ns; S<=’1’;T<=’1’; end process; end arc_test_sm; Solution 5. Write the VHDL code for the state machine. library ieee; use ieee.std_logic_1164.all; entity state_machine5 is port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end state_machine5; architecture arc_ state_machine5 of state_machine5 is type state_type is (A,B,C,D); signal present_state,next_state:state_type; begin process (clk,reset) if (R=’1’) then present_state<=A; elsif (rising_edge(clk) then present_state<=next_state; end if; end process; process (present_state,S,T) begin case present_state is when A => if (S=’1’ or T=’1’)then next_state<=A; elsif (S=’0’)then next_state<=C; elsif (S=’1’ or T=’0’) next_state<=B; else next_state<=A; end if; when B => if (R=’0’)then next_state<=B; elsif (R=’1’)then next_state<=C; else next_state<=A; end if; when C => if (R=’0’ and T=’1’ )then next_state<=D; elsif (R=’1’ and T=’0’)then next_state<=A; elsif((R=’0’andT=’0’)or R=’1’and T=’1’) next_state<=B; else next_state<=A; end if; when D => next_state<=A; end case; end process; end arc_ state_machine5; Test bench: entity test_sm is end test_sm; architecture arc_test_sm of test_sm is component state_machine5 port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end component; signal clk: std_logic :=’0’; signal R: std_logic :=’1’; signal S: std_logic :=’0’; signal T: std_logic :=’0’; .
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Combinational Circuits
Combinational Circuits presentation given by Farzan Dehbashi and Parham Alvani
Behavioral modelling in VHDL
this slide is prepare in very simple manner to understand the behavioral modeling of vhdl
solution of question no.6inputPresent stateNext stateoutput.pdf
solution of question no.6
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0
1
S1
S1
0
0
S2
S3
0
1
S2
S1
0
0
S3
S0
0
1
S3
S4
0
0
S4
S2
1
1
S4
S1
1
library ieee;
use IEEE.std_logic_1164.all;
entity moore is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end moore;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is \"s0\"
if(input =\'0\') then
output <= \'0\';
next_s <= s0;
else
output <= \'0\';
next_s <= s1;
end if;
when s1 =>; --when current state is \"s1\"
if(input =\'0\') then
output <= \'0\';
next_s <= s2;
else
output <= \'0\';
next_s <= s1;
end if;
when s2 => --when current state is \"s2\"
if(input =\'0\') then
output <= \'0\';
next_s <= s3;
else
output <= \'0\';
next_s <= s1;
end if;
when s3 => --when current state is \"s3\"
if(input =\'0\') then
output <= \'1\';
next_s <= s0;
else
output <= \'0\';
next_s <= s4;
end if;
when s4 => --when current state is \"s4\"
if(input =\'0\') then
output <= \'1\';
next_s <= s2;
else
output <= \'1\';
next_s <= s1;
end if;
end case;
end process;
end behavioral;
solution of question no.7
input
Present state
Next state
output
0
S0
S1
0
1
S0
S0
0
0
S1
S1
0
1
S1
S2
0
0
S2
S3
0
1
S2
S0
0
0
S3
S1
0
1
S3
S2
1
library ieee;
use IEEE.std_logic_1164.all;
entity mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end mealy;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is \"s0\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'0\';
next_s <= s0;
end if;
when s1 =>; --when current state is \"s1\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'0\';
next_s <= s2;
end if;
when s2 => --when current state is \"s2\"
if(input =\'0\') then
output <= \'0\';
next_s <= s3;
else
output <= \'0\';
next_s <= s1;
end if;
when s3 => --when current state is \"s3\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'1\';
next_s <= s2;
end if;
end case;
end process;
end behavioral;
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0
1
S1
S1
0
0
S2
S3
0
1
S2
S1
0
0
S3
S0
0
1
S3
S4
0
0
S4
S2
1
1
S4
S1
1
Solution
solution of que.
solution of question no.6inputPresent stateNext stateoutput.pdf
solution of question no.6
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0
1
S1
S1
0
0
S2
S3
0
1
S2
S1
0
0
S3
S0
0
1
S3
S4
0
0
S4
S2
1
1
S4
S1
1
library ieee;
use IEEE.std_logic_1164.all;
entity moore is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end moore;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is \"s0\"
if(input =\'0\') then
output <= \'0\';
next_s <= s0;
else
output <= \'0\';
next_s <= s1;
end if;
when s1 =>; --when current state is \"s1\"
if(input =\'0\') then
output <= \'0\';
next_s <= s2;
else
output <= \'0\';
next_s <= s1;
end if;
when s2 => --when current state is \"s2\"
if(input =\'0\') then
output <= \'0\';
next_s <= s3;
else
output <= \'0\';
next_s <= s1;
end if;
when s3 => --when current state is \"s3\"
if(input =\'0\') then
output <= \'1\';
next_s <= s0;
else
output <= \'0\';
next_s <= s4;
end if;
when s4 => --when current state is \"s4\"
if(input =\'0\') then
output <= \'1\';
next_s <= s2;
else
output <= \'1\';
next_s <= s1;
end if;
end case;
end process;
end behavioral;
solution of question no.7
input
Present state
Next state
output
0
S0
S1
0
1
S0
S0
0
0
S1
S1
0
1
S1
S2
0
0
S2
S3
0
1
S2
S0
0
0
S3
S1
0
1
S3
S2
1
library ieee;
use IEEE.std_logic_1164.all;
entity mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end mealy;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is \"s0\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'0\';
next_s <= s0;
end if;
when s1 =>; --when current state is \"s1\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'0\';
next_s <= s2;
end if;
when s2 => --when current state is \"s2\"
if(input =\'0\') then
output <= \'0\';
next_s <= s3;
else
output <= \'0\';
next_s <= s1;
end if;
when s3 => --when current state is \"s3\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'1\';
next_s <= s2;
end if;
end case;
end process;
end behavioral;
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0
1
S1
S1
0
0
S2
S3
0
1
S2
S1
0
0
S3
S0
0
1
S3
S4
0
0
S4
S2
1
1
S4
S1
1
Solution
solution of que.
Digital System Design-Synchronous Sequential Circuits
Behavioral modeling of sequential logic modules: Latches, Flip Flops, counters and shift registers applications
Synchronous Sequential Circuits: Analysis and synthesis of synchronous sequential circuits: Mealy and Moore FSM models for completely and incompletely specified circuits, State Minimization-Partitioning Minimization Procedure, sequence detector with verilog HDL modeling Design of a Modulo-8 Counter using the Sequential Circuit Approach and its verilog implementation. One-Hot Encoding
W8_2: Inside the UoS Educational Processor
In this unit we provide more details to the UoS educational, in particular it's implementation in VHDL.
Unit duration: 50mn.
License: LGPL 2.1
Polarity is measured on a scale of electronegativ.pdf
Polarity is measured on a scale of electronegativity (the electron disparity between
two elements that are combined in a compound). The more electrons you take from your partner
element in the bonding process, the greater your negative charge, and the greater your
electronegativity. Non-polar covalent is the least polar - in fact, it is not polar at all. This
occurs when valence electrons are shared equally between two atoms. There is little or no
tendency for either atom to pull any of the electrons toward itself. Non-polar covalent bonds can
often be seen in molecules with two non-metals. Methane (CH4) is an example of a non-polar
covalent bond.
Solution
Polarity is measured on a scale of electronegativity (the electron disparity between
two elements that are combined in a compound). The more electrons you take from your partner
element in the bonding process, the greater your negative charge, and the greater your
electronegativity. Non-polar covalent is the least polar - in fact, it is not polar at all. This
occurs when valence electrons are shared equally between two atoms. There is little or no
tendency for either atom to pull any of the electrons toward itself. Non-polar covalent bonds can
often be seen in molecules with two non-metals. Methane (CH4) is an example of a non-polar
covalent bond..
Geometric isomers are a subset of stereoisomers. .pdf
Geometric isomers are a subset of stereoisomers. Geometricisomerism usually
describes cis-trans relationships only.Stereoisomers describes compounds that differ in the 3-
Dorientation, which includes geometric isomers. Otherstereoisometric relationships include
enatiomers (mirror images)and meso compounds.
Solution
Geometric isomers are a subset of stereoisomers. Geometricisomerism usually
describes cis-trans relationships only.Stereoisomers describes compounds that differ in the 3-
Dorientation, which includes geometric isomers. Otherstereoisometric relationships include
enatiomers (mirror images)and meso compounds..
Scientists Contributions Stanley Miller Conducted an experiment .pdf
Scientists Contributions Stanley Miller Conducted an experiment which demonstrated that
several organic compounds could be formed spontaneously by simple chemical processes from
inorganic substances. Alexander Oparin Contributions include the \'theory of the origin of life
on Earth\' . According to the theory, life evolved in the oceans during a period when the
atmosphere was reducing and containing reduced H2, H2O, NH3, CH4, and CO2, but no free O
Sidney Fox Contributions include the discoveries on the origins of life by exploring the synthesis
of amino acids from inorganic molecules etc., John Ussher Contributions include the strong
suggestions to the long-running theological debate on the age of the Earth Carlos Linnaeus
Contributions include the formalisations of the modern system of naming organisms Jean
Baptiste Lamark Proposed a full-blown theory of evolution
Solution
Scientists Contributions Stanley Miller Conducted an experiment which demonstrated that
several organic compounds could be formed spontaneously by simple chemical processes from
inorganic substances. Alexander Oparin Contributions include the \'theory of the origin of life
on Earth\' . According to the theory, life evolved in the oceans during a period when the
atmosphere was reducing and containing reduced H2, H2O, NH3, CH4, and CO2, but no free O
Sidney Fox Contributions include the discoveries on the origins of life by exploring the synthesis
of amino acids from inorganic molecules etc., John Ussher Contributions include the strong
suggestions to the long-running theological debate on the age of the Earth Carlos Linnaeus
Contributions include the formalisations of the modern system of naming organisms Jean
Baptiste Lamark Proposed a full-blown theory of evolution.
1) Microfinance is the provision of small-scale financial services t.pdf
1) Microfinance is the provision of small-scale financial services to people who lack access to
traditional banking services.
2) Payday loans are small-credit loans marketed as a quick and easy way to tide borrowers over
until the next payday.
Solution
1) Microfinance is the provision of small-scale financial services to people who lack access to
traditional banking services.
2) Payday loans are small-credit loans marketed as a quick and easy way to tide borrowers over
until the next payday..
More Related Content
Similar to 5.Write the VHDL code for the state machine.library ieee;use i.pdf
Combinational Circuits
Combinational Circuits presentation given by Farzan Dehbashi and Parham Alvani
Behavioral modelling in VHDL
this slide is prepare in very simple manner to understand the behavioral modeling of vhdl
solution of question no.6inputPresent stateNext stateoutput.pdf
solution of question no.6
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0
1
S1
S1
0
0
S2
S3
0
1
S2
S1
0
0
S3
S0
0
1
S3
S4
0
0
S4
S2
1
1
S4
S1
1
library ieee;
use IEEE.std_logic_1164.all;
entity moore is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end moore;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is \"s0\"
if(input =\'0\') then
output <= \'0\';
next_s <= s0;
else
output <= \'0\';
next_s <= s1;
end if;
when s1 =>; --when current state is \"s1\"
if(input =\'0\') then
output <= \'0\';
next_s <= s2;
else
output <= \'0\';
next_s <= s1;
end if;
when s2 => --when current state is \"s2\"
if(input =\'0\') then
output <= \'0\';
next_s <= s3;
else
output <= \'0\';
next_s <= s1;
end if;
when s3 => --when current state is \"s3\"
if(input =\'0\') then
output <= \'1\';
next_s <= s0;
else
output <= \'0\';
next_s <= s4;
end if;
when s4 => --when current state is \"s4\"
if(input =\'0\') then
output <= \'1\';
next_s <= s2;
else
output <= \'1\';
next_s <= s1;
end if;
end case;
end process;
end behavioral;
solution of question no.7
input
Present state
Next state
output
0
S0
S1
0
1
S0
S0
0
0
S1
S1
0
1
S1
S2
0
0
S2
S3
0
1
S2
S0
0
0
S3
S1
0
1
S3
S2
1
library ieee;
use IEEE.std_logic_1164.all;
entity mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end mealy;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is \"s0\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'0\';
next_s <= s0;
end if;
when s1 =>; --when current state is \"s1\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'0\';
next_s <= s2;
end if;
when s2 => --when current state is \"s2\"
if(input =\'0\') then
output <= \'0\';
next_s <= s3;
else
output <= \'0\';
next_s <= s1;
end if;
when s3 => --when current state is \"s3\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'1\';
next_s <= s2;
end if;
end case;
end process;
end behavioral;
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0
1
S1
S1
0
0
S2
S3
0
1
S2
S1
0
0
S3
S0
0
1
S3
S4
0
0
S4
S2
1
1
S4
S1
1
Solution
solution of que.
solution of question no.6inputPresent stateNext stateoutput.pdf
solution of question no.6
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0
1
S1
S1
0
0
S2
S3
0
1
S2
S1
0
0
S3
S0
0
1
S3
S4
0
0
S4
S2
1
1
S4
S1
1
library ieee;
use IEEE.std_logic_1164.all;
entity moore is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end moore;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is \"s0\"
if(input =\'0\') then
output <= \'0\';
next_s <= s0;
else
output <= \'0\';
next_s <= s1;
end if;
when s1 =>; --when current state is \"s1\"
if(input =\'0\') then
output <= \'0\';
next_s <= s2;
else
output <= \'0\';
next_s <= s1;
end if;
when s2 => --when current state is \"s2\"
if(input =\'0\') then
output <= \'0\';
next_s <= s3;
else
output <= \'0\';
next_s <= s1;
end if;
when s3 => --when current state is \"s3\"
if(input =\'0\') then
output <= \'1\';
next_s <= s0;
else
output <= \'0\';
next_s <= s4;
end if;
when s4 => --when current state is \"s4\"
if(input =\'0\') then
output <= \'1\';
next_s <= s2;
else
output <= \'1\';
next_s <= s1;
end if;
end case;
end process;
end behavioral;
solution of question no.7
input
Present state
Next state
output
0
S0
S1
0
1
S0
S0
0
0
S1
S1
0
1
S1
S2
0
0
S2
S3
0
1
S2
S0
0
0
S3
S1
0
1
S3
S2
1
library ieee;
use IEEE.std_logic_1164.all;
entity mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end mealy;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset=\'1\') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is \"s0\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'0\';
next_s <= s0;
end if;
when s1 =>; --when current state is \"s1\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'0\';
next_s <= s2;
end if;
when s2 => --when current state is \"s2\"
if(input =\'0\') then
output <= \'0\';
next_s <= s3;
else
output <= \'0\';
next_s <= s1;
end if;
when s3 => --when current state is \"s3\"
if(input =\'0\') then
output <= \'0\';
next_s <= s1;
else
output <= \'1\';
next_s <= s2;
end if;
end case;
end process;
end behavioral;
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0
1
S1
S1
0
0
S2
S3
0
1
S2
S1
0
0
S3
S0
0
1
S3
S4
0
0
S4
S2
1
1
S4
S1
1
Solution
solution of que.
Digital System Design-Synchronous Sequential Circuits
Behavioral modeling of sequential logic modules: Latches, Flip Flops, counters and shift registers applications
Synchronous Sequential Circuits: Analysis and synthesis of synchronous sequential circuits: Mealy and Moore FSM models for completely and incompletely specified circuits, State Minimization-Partitioning Minimization Procedure, sequence detector with verilog HDL modeling Design of a Modulo-8 Counter using the Sequential Circuit Approach and its verilog implementation. One-Hot Encoding
W8_2: Inside the UoS Educational Processor
In this unit we provide more details to the UoS educational, in particular it's implementation in VHDL.
Unit duration: 50mn.
License: LGPL 2.1
Similar to 5.Write the VHDL code for the state machine.library ieee;use i.pdf (18)
solution of question no.6inputPresent stateNext stateoutput.pdf
solution of question no.6inputPresent stateNext stateoutput.pdf
solution of question no.6inputPresent stateNext stateoutput.pdf
solution of question no.6inputPresent stateNext stateoutput.pdf
Digital System Design-Synchronous Sequential Circuits
Digital System Design-Synchronous Sequential Circuits
More from sooryasalini
Polarity is measured on a scale of electronegativ.pdf
Polarity is measured on a scale of electronegativity (the electron disparity between
two elements that are combined in a compound). The more electrons you take from your partner
element in the bonding process, the greater your negative charge, and the greater your
electronegativity. Non-polar covalent is the least polar - in fact, it is not polar at all. This
occurs when valence electrons are shared equally between two atoms. There is little or no
tendency for either atom to pull any of the electrons toward itself. Non-polar covalent bonds can
often be seen in molecules with two non-metals. Methane (CH4) is an example of a non-polar
covalent bond.
Solution
Polarity is measured on a scale of electronegativity (the electron disparity between
two elements that are combined in a compound). The more electrons you take from your partner
element in the bonding process, the greater your negative charge, and the greater your
electronegativity. Non-polar covalent is the least polar - in fact, it is not polar at all. This
occurs when valence electrons are shared equally between two atoms. There is little or no
tendency for either atom to pull any of the electrons toward itself. Non-polar covalent bonds can
often be seen in molecules with two non-metals. Methane (CH4) is an example of a non-polar
covalent bond..
Geometric isomers are a subset of stereoisomers. .pdf
Geometric isomers are a subset of stereoisomers. Geometricisomerism usually
describes cis-trans relationships only.Stereoisomers describes compounds that differ in the 3-
Dorientation, which includes geometric isomers. Otherstereoisometric relationships include
enatiomers (mirror images)and meso compounds.
Solution
Geometric isomers are a subset of stereoisomers. Geometricisomerism usually
describes cis-trans relationships only.Stereoisomers describes compounds that differ in the 3-
Dorientation, which includes geometric isomers. Otherstereoisometric relationships include
enatiomers (mirror images)and meso compounds..
Scientists Contributions Stanley Miller Conducted an experiment .pdf
Scientists Contributions Stanley Miller Conducted an experiment which demonstrated that
several organic compounds could be formed spontaneously by simple chemical processes from
inorganic substances. Alexander Oparin Contributions include the \'theory of the origin of life
on Earth\' . According to the theory, life evolved in the oceans during a period when the
atmosphere was reducing and containing reduced H2, H2O, NH3, CH4, and CO2, but no free O
Sidney Fox Contributions include the discoveries on the origins of life by exploring the synthesis
of amino acids from inorganic molecules etc., John Ussher Contributions include the strong
suggestions to the long-running theological debate on the age of the Earth Carlos Linnaeus
Contributions include the formalisations of the modern system of naming organisms Jean
Baptiste Lamark Proposed a full-blown theory of evolution
Solution
Scientists Contributions Stanley Miller Conducted an experiment which demonstrated that
several organic compounds could be formed spontaneously by simple chemical processes from
inorganic substances. Alexander Oparin Contributions include the \'theory of the origin of life
on Earth\' . According to the theory, life evolved in the oceans during a period when the
atmosphere was reducing and containing reduced H2, H2O, NH3, CH4, and CO2, but no free O
Sidney Fox Contributions include the discoveries on the origins of life by exploring the synthesis
of amino acids from inorganic molecules etc., John Ussher Contributions include the strong
suggestions to the long-running theological debate on the age of the Earth Carlos Linnaeus
Contributions include the formalisations of the modern system of naming organisms Jean
Baptiste Lamark Proposed a full-blown theory of evolution.
1) Microfinance is the provision of small-scale financial services t.pdf
1) Microfinance is the provision of small-scale financial services to people who lack access to
traditional banking services.
2) Payday loans are small-credit loans marketed as a quick and easy way to tide borrowers over
until the next payday.
Solution
1) Microfinance is the provision of small-scale financial services to people who lack access to
traditional banking services.
2) Payday loans are small-credit loans marketed as a quick and easy way to tide borrowers over
until the next payday..
The components of individual health are as followsThe three compon.pdf
The components of individual health are as follows
The three components of public and community health that differ from individual health are as
follows
Environmental health :
The prevention or control of disease, disability and injury related to the interactions between
people and their environment is known as environmental health. The objectives of environmental
health include outdoor air quality, surface and ground water quality, toxic substances and
hazardous wastes, homes and communities, global environmental health, Infrastructure and
surveillance.
Water:
Safe drinking water is a fundamental requirement for public and community health. The
improvements in water quality are made by administering the requirements of water, assessing
water suppliers compliance with drinkinh water standards, assessing water supplier’s water
safety plans e.t.c,
Waste disposal:
It is for prime importance that both solid and liquid waste is disposed of in healthy manner. If the
waste disposal sysmtem is not in a healthy manner, it can have a serious impact on human health.
The different forms of waste disposal include direct discharge to land, direct discharge to water
and sludge disposal.
Solution
The components of individual health are as follows
The three components of public and community health that differ from individual health are as
follows
Environmental health :
The prevention or control of disease, disability and injury related to the interactions between
people and their environment is known as environmental health. The objectives of environmental
health include outdoor air quality, surface and ground water quality, toxic substances and
hazardous wastes, homes and communities, global environmental health, Infrastructure and
surveillance.
Water:
Safe drinking water is a fundamental requirement for public and community health. The
improvements in water quality are made by administering the requirements of water, assessing
water suppliers compliance with drinkinh water standards, assessing water supplier’s water
safety plans e.t.c,
Waste disposal:
It is for prime importance that both solid and liquid waste is disposed of in healthy manner. If the
waste disposal sysmtem is not in a healthy manner, it can have a serious impact on human health.
The different forms of waste disposal include direct discharge to land, direct discharge to water
and sludge disposal..
-Lower income households have become more concentrated in U.S. centr.pdf
-Lower income households have become more concentrated in U.S. central cities and higher
income households have become more concentrated in their suburbs at least since 1969.
-The increased concentration of poor and other lower income households in the central city and
of higher income households in the suburbs characterize large metropolitan areas in the United
States.
-While there is no doubt that poorer households are increasingly concentrated within the central
cities of large metropolitan areas in the United States, some observers have suggested that there
is also a growing spatial concentration of poorer households within some suburban
municipalities.
-Many scholars have identified suburban areas that are experiencing increasing poverty (or
unemployment, or other indicators of low income). Orfield (1997) identified “older suburbs” as
well as “inner ring” suburbs as more recent sites for residential concentrations of the urban poor.
Bourne (1993), in his study of Canadian suburbs, found that suburbs that have been primarily
residential, functioning as “bedroom communities,” were less likely to experience increasing
poverty than those that have industrial bases similar to the central city.
-These studies consider the economic or production factors that underlie changes in the spatial
distribution of poverty and income within a metropolitan area. They argue that suburbs that are
more similar to the central city, in that they were developed earlier and include aging
manufacturing plants, may also be experiencing the increasing concentrations of poverty and low
income that have developed in central cities.
-In other words, among suburban municipalities, income and poverty may be becoming more
spatially concentrated.
-The concentration of poverty among suburban governmental jurisdictions is important for
understanding the implications of changes in the suburbs for the U.S.
Solution
-Lower income households have become more concentrated in U.S. central cities and higher
income households have become more concentrated in their suburbs at least since 1969.
-The increased concentration of poor and other lower income households in the central city and
of higher income households in the suburbs characterize large metropolitan areas in the United
States.
-While there is no doubt that poorer households are increasingly concentrated within the central
cities of large metropolitan areas in the United States, some observers have suggested that there
is also a growing spatial concentration of poorer households within some suburban
municipalities.
-Many scholars have identified suburban areas that are experiencing increasing poverty (or
unemployment, or other indicators of low income). Orfield (1997) identified “older suburbs” as
well as “inner ring” suburbs as more recent sites for residential concentrations of the urban poor.
Bourne (1993), in his study of Canadian suburbs, found that suburbs that have been primarily
residential, functioning as “bedroom.
NO+ note O has one more electron then N, thus, .pdf
NO+ note: O has one more electron then N, thus, NO+ is isoelectrpnical to N2,
having a NO triple bond. Triple NO bond is the strongest NO bond. All the others have a NO
bond order less than three.
Solution
NO+ note: O has one more electron then N, thus, NO+ is isoelectrpnical to N2,
having a NO triple bond. Triple NO bond is the strongest NO bond. All the others have a NO
bond order less than three..
Yes, we should be very suspicious of the bones authenticity. This .pdf
Yes, we should be very suspicious of the bone\'s authenticity. This is mainly because carbon
dating cannot be used to determine the age of dinosaur bones. Radiocarbon dating measures the
life of the isotope of carbon which is C-14. This isotope decays with time. The half life of C-14
isotope is around 5,730 years, so it can be effectively used to determine ages of samples of
around 50,000 years old and not of older samples. And dinosaur bones are around million years
old and their ages cannot be determined by Carbon dating. To determine ages of rock samples of
million years old, we can use radioactive dating of other isotopes that have a very long half-life.
Some of these isotopes are of Uranium (U-235 and U-238) and Potassium (K-40), which have
half-life of more than a million years but even these isotopes are not found in the bones of
dinosaurs or even in the sedimentary rocks containing these dinosaur bones. The dating of these
dinosaur fossils is therefore done in a much more complex way. We need to find igneous rocks
which are buried as deep as the sedimentary rocks containing dinosaur fossils. These igneous
rocks do contain uranium isotopes and their ages can be found by radioactive dating, and can
give a key to the ages of dinosaur bones. Thus, we can safely say that Carbon dating cannot be
used to date dinosaur bones.
One more reason to doubt the claims of the seller is that dinosaurs first appeared in the \"Triassic
period\", roughly 225 million years ago. So how could a dinosaur bone be 400 million years old.
Solution
Yes, we should be very suspicious of the bone\'s authenticity. This is mainly because carbon
dating cannot be used to determine the age of dinosaur bones. Radiocarbon dating measures the
life of the isotope of carbon which is C-14. This isotope decays with time. The half life of C-14
isotope is around 5,730 years, so it can be effectively used to determine ages of samples of
around 50,000 years old and not of older samples. And dinosaur bones are around million years
old and their ages cannot be determined by Carbon dating. To determine ages of rock samples of
million years old, we can use radioactive dating of other isotopes that have a very long half-life.
Some of these isotopes are of Uranium (U-235 and U-238) and Potassium (K-40), which have
half-life of more than a million years but even these isotopes are not found in the bones of
dinosaurs or even in the sedimentary rocks containing these dinosaur bones. The dating of these
dinosaur fossils is therefore done in a much more complex way. We need to find igneous rocks
which are buried as deep as the sedimentary rocks containing dinosaur fossils. These igneous
rocks do contain uranium isotopes and their ages can be found by radioactive dating, and can
give a key to the ages of dinosaur bones. Thus, we can safely say that Carbon dating cannot be
used to date dinosaur bones.
One more reason to doubt the claims of the seller is that dinosaurs first appeared in the \"Tr.
WHITE COLLAR CRIMEWhite-collar crime is nonviolent crime commited.pdf
WHITE COLLAR CRIME:
White-collar crime is nonviolent crime commited for financial gain.White collar crime involve
criminal activities committed by people in the regular course of their business and involve
bribery, extortion, fraud and embezzlement. These crimes usually end in financial gain for the
perpetrator.
what are the opportuinites for diet and excercises in white collor crime:
How You prevent White collar Crime:
There are at least a few reasons we tend to worry less about white collar crime. First, no one gets
physically hurt. Second, we do not imagine professionals stealing. Third, it is difficult to
spot.White collar crime is necessarily perpetrated by people in special positions. Those people in
the office who manage figures and access funds, who make the deals and the big money, or who
file the taxes the ones you really trust with the hard stuff -- are most likely to be involved in a
criminal scheme.
Trusted criminals: Criminals, including white collar criminals, whose crimes involve a breach of
the trust bestowed on them because of their seeming respectability.
Abscam: Asting operation involving a bogus company (Abdul Enterprises) set up in the late
1970s by the FBI, which ultimately led to seven Congressmen being indicted for accepting
bribes, expelled from Congress or forced to resign; also noteworthy as the first congressional
bribe case in which videotaped evidence was available.
Directory Advertising: Actor either impersonates sales person from a directory company like the
yellow pages or fraudulently sells advertising which the victim never receives.
The schemes are often not easy for others to recognize. White collar criminals use their
professional skills for financial gain, relying on the respectability that comes with their position
as a shield. Who imagines that their accountant evades taxes?
How to Stop Fraud in Your Office:
Even if you don\'t believe your people would ever lie, cheat, or steal, you should be wary. If
workers are committing crimes or other wrongdoing and your business is implicated, you will be
held responsible regardless of your conscious involvement. Here are four simple things you can
do to help prevent problems with fraud in your office.
1.Know the Law:
Gain some familiarity with the legal requirements of your business. You will not be able to
develop an expertise in every area of the law, of course, but you should have a lawyer you can
talk to when you have specific questions and a general sense of acceptable behaviors and
potential fraud warning signs. Do not wait for a government investigation that uncovers all you
have done wrong to learn what your business was supposed to be doing. Watch the Work: Make
sure there are systems in place to check on employees. Yes, of course you must trust the people
you hired and you cannot spend all the time monitoring their activities or nothing will get done at
work. But, on the other hand, do not be naïve. Keep an eye on employees and let them know the
ways .
Web 3.0 is just how, why and at what time.Web serviceis a software.pdf
Web 3.0 is just how, why and at what time.
Web serviceis a software system planned to support ‘computer-to-computer’ communication
over the Internet.
At present, 1000’s of web services is available.
Though, in the context of Web 3.0, they gross center stage.
By joining a semantic markup in addition with web services, the Web 3.0 capacities the potential
for applications that can say to each other directly, and for wider searches for info through
simpler interfaces.
· It is user behavior.
· It is user engagement.
· Individual Focus & Smart Applications
Solution
Web 3.0 is just how, why and at what time.
Web serviceis a software system planned to support ‘computer-to-computer’ communication
over the Internet.
At present, 1000’s of web services is available.
Though, in the context of Web 3.0, they gross center stage.
By joining a semantic markup in addition with web services, the Web 3.0 capacities the potential
for applications that can say to each other directly, and for wider searches for info through
simpler interfaces.
· It is user behavior.
· It is user engagement.
· Individual Focus & Smart Applications.
There are a few different reagent could be used to perform this tran.pdf
There are a few different reagent could be used to perform this transformation. The most
common is thionyl chloride SOCl2. It would convert the OH of the acid to Cl and result in the
acid chloride.
Solution
There are a few different reagent could be used to perform this transformation. The most
common is thionyl chloride SOCl2. It would convert the OH of the acid to Cl and result in the
acid chloride..
now a days security is very important to organization and physical s.pdf
now a days security is very important to organization and physical security and their
infrastructures are no exception and now a days hacking has become major threats like cyber
security or computer crimes .security is awareness that reduce misuse of computer threats and
the considerations should be taken into account in order for deciding which physical controls
should be implemented and their reasons are first thing we can protect the data from hackers by
using security controls like information security controls like technical , policy safeguards like
the law ie the data protection acts place an obligation on data controllers to have appropriate
security measures in place to prevent the unauthorised acces to or destruction of data or
accidental loss of data and we should do this by providing appropriate level of security .
another one is providing access control ie a data controller should have limit to access the
personal data on need to know basis . access authentication ie users should have unique identifier
such as pass words to allow access to personal data and data controller should make sure that
their passwords should be unique and it should not disclose to anyone and these include not only
passwords but also smart card or token.Encryption is the process of encoding information stored
on device and further adding security and it is considered an essential security measure where
information is stored on portable device or transmitted over public network and by using
passwords we can decrypt the data.Mainly antivirus plays an major important role in protecting
the information by preventing the viruses that may also introduced from portable devices .
Firewalls plays a major important role in protecting the information from hackers as their major
duty is to prevent unauthorised access attempts and the importance of firewalls has increased in
organizations and individuals avail on internet connections . software patching are the latest
updates from the creator of your os and they usually contain fixes to potential security concerns
and can be important tool in preventing hacking and malware attacks .wireless network ie access
to server by means of wireless connection can expose network attacks . Human factor ie no
matter what people should not write passwords that related to information and prevent it from
hacking .backup systems are essential in preventing the destruction of information or loss of
data.logs and audit trails ie normally the system should identify the user name that access the file
and the time of access. IN This way we can protect the information from hacking by using this
preventive measures in protecting the information.
Solution
now a days security is very important to organization and physical security and their
infrastructures are no exception and now a days hacking has become major threats like cyber
security or computer crimes .security is awareness that reduce misuse of computer threats and
the considerations sh.
pH = pKa + log([A-][HA])(base) HONH2 + H2O (acid) HONH3+ + OH-.pdf
pH = pKa + log([A-]/[HA])
(base) HONH2 + H2O (acid) HONH3+ + OH-
so,
pH = pKa + log([HONH2]/[HONH3+])
pH = 1.1 E-8 + log(0.500/0.500) = 1.1 E-8 + 0 = 1.1 E-8
Solution
pH = pKa + log([A-]/[HA])
(base) HONH2 + H2O (acid) HONH3+ + OH-
so,
pH = pKa + log([HONH2]/[HONH3+])
pH = 1.1 E-8 + log(0.500/0.500) = 1.1 E-8 + 0 = 1.1 E-8.
Solution Relation between carpels and locules Carpels is the p.pdf
Solution
:
Relation between carpels and locules:
Carpels is the part of flower which contain sigma,style and ovary.Locules are present in the
ovary as like compartment.It have ovule helps in producing seed when ovule is fertilized.Each of
the carpel contain only one locule.Both of them helps in the process of reproduction in plants..
Solution.Providing legal advice to the president of the company co.pdf
Solution
.
Providing legal advice to the president of the company concerning a possible merger would be
considered a organization sustaining activity.
A merger or acquisition is a combination of two companies where one corporation is completely
absorbed by another corporation. The less important company loses its identity and becomes part
of the more important corporation, which retains its identity. A merger extinguishes the merged
corporation, and the surviving corporation assumes all the rights, privileges, and liabilities of the
merged corporation. A merger is not the same as a consolidation, in which two corporations lose
their separate identities and unite to form a completely new corporation..
S and Se are 6th group elementsSize increase the leaving nature in.pdf
S and Se are 6th group elements
Size increase the leaving nature increase for example Iis better leaving group than F
Therefore S-2 strong base thanSe-2
Solution
S and Se are 6th group elements
Size increase the leaving nature increase for example Iis better leaving group than F
Therefore S-2 strong base thanSe-2.
Please refer this solution. This is working file for IntegersHeade.pdf
Please refer this solution. This is working file for Integers
Header file :-
-----------------------------------
#ifndef LINKEDLIST_H
#define LINKEDLIST_H
struct node{
void * data;
node * next;
};
class LinkedList
{
private:
node* head ;
int size;
public:
LinkedList();
//method to create a node
node * create(void* data);
//method to append
void append(node * item);
//method to prepend
void prepend(node * item);
//insert in ascending order
void insertAscend(node * item);
//insert in ascending order
void insertDescend(node * item);
//display all nodes
void display();
//free the list
void freeUp();
};
#endif // LINKEDLIST_H
Source file :-
----------------------------------
#include \"linkedlist.h\"
#include
#include
#include
LinkedList::LinkedList()
{
//head = (node *)malloc(sizeof(node));
size = 0;
head = NULL;
}
//method to create a node
node * LinkedList::create(void* data){
node * newNode = (node *)malloc(sizeof(node));
newNode->data = malloc(sizeof(data));
memcpy(newNode->data,data,sizeof(data));
newNode->next = NULL;
return newNode;
}
//method to append
void LinkedList::append(node * item){
if(head == NULL){
head = item;
size++;
return;
}
node* current;
current = head;
while (current->next!=NULL )
{
current = current->next;
}
current->next = item ;
size++;
}
//method to prepend
void LinkedList::prepend(node * item){
if(head == NULL){
head = item;
size++;
return;
}
item->next = head;
head = item;
size++;
}
//insert in ascending order
void LinkedList::insertAscend(node * item){
if(head == NULL){
head = item;
size++;
return;
}
node* current;
current = head;
node * prev = NULL;
bool found = false;
while (current !=NULL){
int *current_data = static_cast(current->data);
int *item_data = static_cast(item->data);
if(*item_data < *current_data){
if(prev == NULL){
item->next = current;
if(current == head){
head = item;
}
}
else{
prev->next = item;
item->next = current;
}
found = true;
break;
}
prev = current;
current = current->next;
}
if(!found){
prev->next = item;
}
size++;
}
//insert in Descending order
void LinkedList::insertDescend(node * item){
if(head == NULL){
head = item;
size++;
return;
}
node* current;
current = head;
node * prev = NULL;
bool found = false;
while (current !=NULL){
int *current_data = static_cast(current->data);
int *item_data = static_cast(item->data);
if(*item_data > *current_data){
if(prev == NULL){
item->next = current;
if(current == head){
head = item;
}
}
else{
prev->next = item;
item->next = current;
}
found = true;
break;
}
prev = current;
current = current->next;
}
if(!found){
prev->next = item;
}
size++;
}
//display all nodes
void LinkedList::display(){
int idx = 0;
node* current;
current = head;
while (current != NULL ){
idx++;
int *data = static_cast(current->data);
printf(\"data for item ::%dis :: %d\ \",idx,*data);
current = current->next;
}
}
//free the list
void LinkedList::freeUp(){
node* current;
current = head;
while (current->next!=NULL ){
head = current->next;
delete current;
current = head;
}
}
Main f.
Simple DefinationsIntertidal zone is the area that is above wate.pdf
Simple Definations
Intertidal zone : is the area that is above water at low tide and under water at high tide (in other
words, the area between tide marks).
Coral reef : are diverse underwater ecosystems held together by calcium carbonate structures
secreted by corals.
lentic habitat : has still waters. Examples include: ponds, basin marshes, ditches, reservoirs,
seeps, lakes, and vernal / ephemeral pools.
lotic habitat : has flowing waters. Examples include: creeks, streams, runs, rivers,springs, brooks
and channels.
Intertidal zone
Coral reef
Intertidal zone
Coral reeflentic habitatlotic habitatLand meets sea,daily cycle of tidesstill,often deep
waterflowing water,well aerated water,Huge variation in temperature .light intensity,&
availablity of sea waterfound between 20 & 30 degrees ,penetrating sunlightsupports fish as trout
and salmon
Solution
Simple Definations
Intertidal zone : is the area that is above water at low tide and under water at high tide (in other
words, the area between tide marks).
Coral reef : are diverse underwater ecosystems held together by calcium carbonate structures
secreted by corals.
lentic habitat : has still waters. Examples include: ponds, basin marshes, ditches, reservoirs,
seeps, lakes, and vernal / ephemeral pools.
lotic habitat : has flowing waters. Examples include: creeks, streams, runs, rivers,springs, brooks
and channels.
Intertidal zone
Coral reef
Intertidal zone
Coral reeflentic habitatlotic habitatLand meets sea,daily cycle of tidesstill,often deep
waterflowing water,well aerated water,Huge variation in temperature .light intensity,&
availablity of sea waterfound between 20 & 30 degrees ,penetrating sunlightsupports fish as trout
and salmon.
Production.javapublic class Production { Declaring instance.pdf
Production.java
public class Production {
//Declaring instance variables
private String title;
private String director;
private String writer;
//Parameterized constructor
public Production(String title, String director, String writer) {
super();
this.title = title;
this.director = director;
this.writer = writer;
}
//Setters and getters.
public String getTitle() {
return title;
}
public void setTitle(String title) {
this.title = title;
}
public String getDirector() {
return director;
}
public void setDirector(String director) {
this.director = director;
}
public String getWriter() {
return writer;
}
public void setWriter(String writer) {
this.writer = writer;
}
//display() method which displays the Instance variable values
public void display()
{
System.out.println(\"Title: \" + this.title);
System.out.println(\"Director: \" + this.director);
System.out.println(\"Writer: \" + this.writer);
}
//toString() method is used to display the contents of an object
@Override
public String toString() {
return \"Title :\" + title + \"\ Director :\" + director
+ \"\ Writer :\" + writer;
}
}
___________________________________________
Film.java
public class Film extends Production{
//Declaring instance variables
private int boxOfficeGross;
//Parameterized constructor
public Film(String title, String director, String writer, int boxOfficeGross) {
super(title, director, writer);
this.boxOfficeGross = boxOfficeGross;
}
//Setters and getters.
public int getBoxOfficeGross() {
return boxOfficeGross;
}
public void setBoxOfficeGross(int boxOfficeGross) {
this.boxOfficeGross = boxOfficeGross;
}
//display() method which displays the Instance variable values
public void display()
{
System.out.println(\"BoxOfiiceGross: \" + this.boxOfficeGross);
}
//toString() method is used to display the contents of an object
@Override
public String toString() {
return super.toString()+\"\ BoxOfficeGross :\" + boxOfficeGross+\"\ \";
}
}
_______________________________________________
Play.java
public class Play extends Production {
//Declaring instance variables
private int performances;
//Parameterized constructor
public Play(String title, String director, String writer, int performances) {
super(title, director, writer);
this.performances = performances;
}
//Setters and getters.
public int getPerformances() {
return performances;
}
public void setPerformances(int performances) {
this.performances = performances;
}
//display() method which displays the Instance variable values
public void display()
{
System.out.println(\"Performances: \" + this.performances);
}
//toString() method is used to display the contents of an object
@Override
public String toString() {
return super.toString()+\"\ Performances :\" + performances+\"\ \";
}
}
_______________________________________________
Musical.java
public class BobsTerribleTests
{
public static void main(String[] args)
{
//Creating an Film Object by passing parameters
Film titanic = new Film(\"Titanic\", \"James Cameron\", \"James Cameron\.
Proteobacteria are major phylum of gram negative bacteria. Major gro.pdf
Proteobacteria are major phylum of gram negative bacteria. Major groups of Proteobacteria with
medical importance:
Medically important genus Rickettsia which causes typhus, Rocky Mountain spotted fever,
Flinders Island spotted fever, rickettsialpox, Boutonneuse fever, African tick bite
feverQueensland tick typhus. They are transmitted by arthropod including tick, flea and lice.
Two species of Neisseria causes diseses-N. meningitidis and N. gonorrhoeae (sexually
transmitted)
Three species of Bordetella are human pathogen - B. pertussis (causes whooping cough- air
borne infection), B. parapertussis, B. bronchiseptica
Some serotypes of Escherichia coli are human pathogens and cause urinary tract infections,
significant sources of gastrointestinal disease, ranging from simple diarrhea to dysentery-like
conditions
Shigella-S. dysenteriae cause dysentry (Shigella infection is typically by ingestion)
Salmonella-Salmonella typhi cause typhoid fever. Other species of Salmonella causes food
poisoning
Yersinia -Y. pestis is the causative agent of the plague
Haemophilus -H. influenzae causes sepsis and bacterial meningitis in young children and H.
ducreyi, the causative agent of chancroid
Vibrio- V. cholerae (causative agent of cholera) is generally transmitted by contaminated water.
Pseudomonas are opportunistic pathogen
Helicobacter,H. pylori is strongly associated with peptic ulcers, chronic gastritis, duodenitis, and
stomach cancer
Solution
Proteobacteria are major phylum of gram negative bacteria. Major groups of Proteobacteria with
medical importance:
Medically important genus Rickettsia which causes typhus, Rocky Mountain spotted fever,
Flinders Island spotted fever, rickettsialpox, Boutonneuse fever, African tick bite
feverQueensland tick typhus. They are transmitted by arthropod including tick, flea and lice.
Two species of Neisseria causes diseses-N. meningitidis and N. gonorrhoeae (sexually
transmitted)
Three species of Bordetella are human pathogen - B. pertussis (causes whooping cough- air
borne infection), B. parapertussis, B. bronchiseptica
Some serotypes of Escherichia coli are human pathogens and cause urinary tract infections,
significant sources of gastrointestinal disease, ranging from simple diarrhea to dysentery-like
conditions
Shigella-S. dysenteriae cause dysentry (Shigella infection is typically by ingestion)
Salmonella-Salmonella typhi cause typhoid fever. Other species of Salmonella causes food
poisoning
Yersinia -Y. pestis is the causative agent of the plague
Haemophilus -H. influenzae causes sepsis and bacterial meningitis in young children and H.
ducreyi, the causative agent of chancroid
Vibrio- V. cholerae (causative agent of cholera) is generally transmitted by contaminated water.
Pseudomonas are opportunistic pathogen
Helicobacter,H. pylori is strongly associated with peptic ulcers, chronic gastritis, duodenitis, and
stomach cancer.
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5.Write the VHDL code for the state machine.library ieee;use i.pdf
- 1. 5. Write the VHDL code for the state machine. library ieee; use ieee.std_logic_1164.all; entity state_machine5 is port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end state_machine5; architecture arc_ state_machine5 of state_machine5 is type state_type is (A,B,C,D); signal present_state,next_state:state_type; begin process (clk,reset) if (R=’1’) then present_state<=A; elsif (rising_edge(clk) then present_state<=next_state; end if; end process; process (present_state,S,T) begin case present_state is when A => if (S=’1’ or T=’1’)then next_state<=A; elsif (S=’0’)then next_state<=C; elsif (S=’1’ or T=’0’) next_state<=B; else next_state<=A; end if; when B => if (R=’0’)then
- 2. next_state<=B; elsif (R=’1’)then next_state<=C; else next_state<=A; end if; when C => if (R=’0’ and T=’1’ )then next_state<=D; elsif (R=’1’ and T=’0’)then next_state<=A; elsif((R=’0’andT=’0’)or R=’1’and T=’1’) next_state<=B; else next_state<=A; end if; when D => next_state<=A; end case; end process; end arc_ state_machine5; Test bench: entity test_sm is end test_sm; architecture arc_test_sm of test_sm is component state_machine5 port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end component; signal clk: std_logic :=’0’; signal R: std_logic :=’1’; signal S: std_logic :=’0’; signal T: std_logic :=’0’; constant clk_period : time := 5 ns; begin
- 3. test1: state_machine5 port map ( clk,R,S,T); process begin clk<=’0’; wait for clk_period/2; clk<=’1’; wait for clk_period/2; end process; process begin wait for 5 ns; R<=’0’; S<=’0’;T<=’0’; wait for 5 ns; S<=’0’;T<=’1’; wait for 5 ns; R<=’1’; wait for 5 ns; S<=’1’;T<=’0’; wait for 5 ns; S<=’1’;T<=’1’; end process; end arc_test_sm; Solution 5. Write the VHDL code for the state machine. library ieee; use ieee.std_logic_1164.all; entity state_machine5 is port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end state_machine5;
- 4. architecture arc_ state_machine5 of state_machine5 is type state_type is (A,B,C,D); signal present_state,next_state:state_type; begin process (clk,reset) if (R=’1’) then present_state<=A; elsif (rising_edge(clk) then present_state<=next_state; end if; end process; process (present_state,S,T) begin case present_state is when A => if (S=’1’ or T=’1’)then next_state<=A; elsif (S=’0’)then next_state<=C; elsif (S=’1’ or T=’0’) next_state<=B; else next_state<=A; end if; when B => if (R=’0’)then next_state<=B; elsif (R=’1’)then next_state<=C; else next_state<=A; end if; when C => if (R=’0’ and T=’1’ )then next_state<=D; elsif (R=’1’ and T=’0’)then
- 5. next_state<=A; elsif((R=’0’andT=’0’)or R=’1’and T=’1’) next_state<=B; else next_state<=A; end if; when D => next_state<=A; end case; end process; end arc_ state_machine5; Test bench: entity test_sm is end test_sm; architecture arc_test_sm of test_sm is component state_machine5 port(clk: in std_logic; R: in std_logic; S,T:in std_logic); end component; signal clk: std_logic :=’0’; signal R: std_logic :=’1’; signal S: std_logic :=’0’; signal T: std_logic :=’0’; constant clk_period : time := 5 ns; begin test1: state_machine5 port map ( clk,R,S,T); process begin clk<=’0’; wait for clk_period/2; clk<=’1’; wait for clk_period/2; end process; process
- 6. begin wait for 5 ns; R<=’0’; S<=’0’;T<=’0’; wait for 5 ns; S<=’0’;T<=’1’; wait for 5 ns; R<=’1’; wait for 5 ns; S<=’1’;T<=’0’; wait for 5 ns; S<=’1’;T<=’1’; end process; end arc_test_sm;