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# Day4 順序控制的循序邏輯實現

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### Day4 順序控制的循序邏輯實現

1. 1. DAY3 順序控制 循序邏輯實現
2. 2. Feedback
3. 3. SR Latch RESET SET Bistable → 雙穩態
4. 4. SR Latch, 自保回路
5. 5. SR Latch
6. 6. SR Latch with Enable LAB
7. 7. D Latch: 狀態儲存
8. 8. D Filp Flop: Edge-Triggered Latch D Latch D Flip Flop posedge clock
9. 9. D Flip Flop D Flip Flop clock negedge
10. 10. DFF: Enable, Preset, Clear
11. 11. JK Flip Flop J & !Q K&Q
12. 12. T Flip Flop
13. 13. Counter 000 – 001–010–011–100–101–110–111–000
14. 14. Synchronous Counter( 同步計數器 ) `
15. 15. LAB
16. 16. Timer one-shot
17. 17. Debouncer LAB3
18. 18. Timer Delay
19. 19. LAB4
20. 20. Verilog HDL RTL Code
21. 21. SR Latch HDL Code
22. 22. D Latch HDL Code
23. 23. DFF always @(posedge clk) always @(posedge clk) begin begin if (CE) if (S) Q = D; Q = 1'b1; end else Q = D; end endmodule
24. 24. 4-bit unsigned Up counter with asynchronous clear module counter (C, CLR, Q); input C, CLR; output [3:0] Q; reg [3:0] Q; always @(posedge C or posedge CLR) begin if (CLR) Q = 4'b0000; else Q = Q + 1'b1; end endmodule
25. 25. 4-bit unsigned Down counter with synchronous set module counter (C, S, Q); input C, S; output [3:0] Q; reg [3:0] Q; always @(posedge C) begin if (S) Q = 4'b1111; else Q = Q - 1'b1; end endmodule
26. 26. 4-bit unsigned Up Counter with asynchronous load module counter (C, ALOAD, D, Q); input C, ALOAD; input [3:0] D; output [3:0] Q; reg [3:0] Q; always @(posedge C or posedge ALOAD) begin if (ALOAD) Q = D; else Q = Q + 1'b1; end endmodule
27. 27. 4-bit unsigned Up counter with asyn- chronous clear and clock enable module counter (C, CLR, CE, Q); input C, CLR, CE; output [3:0] Q; reg [3:0] Q; always @(posedge C or posedge CLR) begin if (CLR) Q = 4'b0000; else if (CE) Q = Q + 1'b1; end endmodule
28. 28. 8-bit shift-left register serial in serial out. module shift (C, SI, SO); input C,SI; output SO; reg [7:0] Q; always @(posedge C) begin Q <= Q << 1; // Q <= {Q[6:1], SI}; Q[0] <= SI; end assign SO = Q[7]; endmodule