4. Basic Syntax
4
1 module Top;
2 initial $display(“hello, world");
3 endmodule
this will be executed at program startup
like C’s printf, but automatically append newline character
uninstantiated module as top-level module
5. Value Set
5
0 – logic zero
1 – logic one
x – unknown value
both true & false, don’t care (in some condition)
z – high impedance state
neither true or false, open circuit
6. Event Control
6
blocked until event occurs
@a $display(a);
call display by any value change in a
@(posedge clk) $display(a);
call display by positive edge on clk
to
from 0 1 x z
0 no pos pos pos
1 neg no neg neg
x neg pos no no
z neg pos no no
7. Always Construct
7
Basically, a, b, c have the same behavior
But assignment at time zero is unspecified
1 initial while (1) @u a = u;
2
3 initial forever @u b = u;
4
5 always @u c = u;
6
7 always d = u;
unintentional looping
8. Non-Constant Data Type
8
Variable
reg, integer, real, time…
assigned only in procedure block or declaration
initial, always, task, function block
Net
wire, tri, supply1…
continuous assigned only
net declaration assignment, port connection…
have drive strength
9. Multiple Assignment
9
0 1 x z
0 0 x x 0
1 x 1 x 1
x x x x x
z 0 1 x z
1 reg a;
2 wire b;
3
4 wire #1 u = 0;
5 wire #1 v = 1;
6
7 always @u a = u;
8 always @v a = v;
9
10 assign b = u;
11 assign b = v;
1 unit delay, which is specified by timescale
result in 0 or 1 after 1 unit delay
(race condition)
result in unknown x after 1 unit delay
(multiple driven)
multiple driven on wire
10. Registers
10
Typically composed of D flip-flops
capture signal at the rising edge of the clock
Not confused with the data type “reg“
11. 1 module DFFR (
2 input CLK,
3 input D,
4 input R,
5 output reg Q
6 );
7 always @ (posedge CLK, negedge R)
8 if (!R)
9 Q = 0;
10 else
11 Q = D;
12 endmodule
D Flip-Flop
11
same as “or”
does that describe D flip-flop correctly?
implicit type wire
18. Separate Compilation
18
compile
time
elaboration
time
run
time
1 module Module;
2 reg in;
3 wire out;
4
5 SubModule subModule (
6 .in(in),
7 .out(out)
8 );
9
10 initial in = some_function();
11 endmodule
module, task, function will be resolved in elaboration time
i.e. the prototype can be unavailable during compile time
this makes separate compilation possible
incremental compilation isn’t based on timestamp in VCS
19. Interact with Your Simulation
Compile time
`define FNAME “vec1”
vcs +define+FNAME=“vec2” …
Elaboration time
parameter IDX_FNAME = 1
vcs –pvalue+<hier>.FNAME=2 …
Run time
$value$plusargs(“FNAME=%s”, FNAME)
./simv +FNAME=vec2
$fscanf(“%s”, FNAME)
19
21. Toggle Coverage
Monitor transition on each bit
0 -> 1, 1 -> 0
x & z are ignored
0 -> x -> 1 equals 0 -> 1
21
22. Verilog Branch
22
1 reg v;
2 reg [2:0] m = 3'b010,
3 n = 3'b110,
4 a, b, c;
5
6
7 if (v)
8 a = m;
9 else
10 a = n;
11
12
13 case (v)
14 1'b0:
15 b = m;
16 1'b1:
17 b = n;
18 endcase
19
20
21 c = v ? m : n;
v a b c
0 3’b110
1 3’b010
x or z 3’b110 old value 3’bx10
23. Branch Coverage
Monitor scenarios
if, case, casex, casez, ?:
23
a b c
0 1 -
0 0/x/z -
1 - 0
1 - 1
default - -
only 5 cases need to be covered
1 reg a, b, c;
2
3 case (a)
4 0:
5 if (b)
6 // do something
7 1:
8 c = c ? a : b;
9 endcase
24. Condition Coverage
Monitor boolean formula
==, !=
&&, ||
&, |, ^, ~^ scalar-only
vector condition
24
a b C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
a b C
0 1 1
1 0 1
1 1 0
1 1 1
a
0
1
b
0
1
c
0
1
basic std allvectors
a && b && c
25. FSM coverage
Monitor finite-state machine
transition
S0->S0, S0->S1, S1->S0
25
1 module FSM #(
2 parameter S0 = 0,
3 S1 = 1
4 ) (
5 input clk,
6 rstN,
7 in,
8 output reg state
9 );
10 always @ (posedge clk, negedge rstN)
11 if (!rstN)
12 state <= S0;
13 else case (state)
14 S0:
15 if (in)
16 state <= S1;
17 S1:
18 state <= S0;
19 endcase
20 endmodule
26. Coverage Analysis
26
we need to add test case to cover the
condition SEN = 0 & SRST = 1 in the
instance tb.scmCEDS