This document discusses sequential circuits in VHDL. It begins by defining sequential circuits as circuits that perform computations over multiple clock cycles by storing intermediate results in memory registers. It then explains how to write sequential logic in VHDL using process statements. Several examples of basic sequential elements like D flip-flops with and without resets are described. The document concludes by providing references for further reading on VHDL and digital design.

1. Sequential Circuits
Siavash Kavousi
Parham Alvani
Amirkabir
University of Technology
Computer & InformationTechnology
Engineering Department

2. Outline
VHDL
• Operators
• Sequential
Circuits

3. VHDL Operators

4. VHDL Operators
xnor xor nor nand or and Logical
>= > <= < /= = Relational
ror rol sra sla srl sll Shift
& - + Addition
- + Sign
rem mod / * Multiplicative
not abs ** Etc
4

5. – bit, bit-vector, boolean
– Std-logic, std-logic vector
entity OPR_EX_E is
port( X,Y : in bit;
Z : out bit);
end entity OPR_EX_E;
architecture OPR_EX_A of OPR_EX_E is
signal DATA_BUS1, DATA_BUS2, DATA_BUS3 : std_logic_vector(7
downto 0);
begin
Z <= X and Y;
DATA_BUS3 <= DATA_BUS1 xor DATA_BUS2;
end architecture OPR_EX_A;
Boolean Operation

6. variable A : bit_vector(2 downto 0);
variable B : bit_vector(0 to 2);
if(A(2) > B(0) or
((A(2) = B(0))and(A(1) > B(1)))or
((A(2) = B(0))and(A(1) = B(1))and(A(0) > B(2))))then ;
variable A : bit_vector(2 downto 0);
variable B : bit_vector(0 to 2);
if(A > B)then ;
Relational Operators

7. • Logical Shift
• Arithmetic Shift
• Rotation
Shift Operators

8. ⋮
signal S_A1, S_A2 : bit_vector (3 downto 0);
signal S_A3 : bit_vector (7 downto 0);
signal S1, S2, S3 : bit;
⋮
S_A3 <= S_A1 & S_A2;
S_A1 <= S1 & S2 & ‘0’ & S3;
S_A3 <= S_A1 & S1 & ‘1’ & S2 & S3;
S_A3 <= S_A1 & “0000”;
Additional Operators

9. Sequential Circuits

10. Sequential circuits
• Circuits that perform a computation in
multiple steps (clock cycles)
Memory registers
Combinational circuits
• Intermediate results are held in registers and
transfered from register-to-register using
combinational circuits

11. How can we write sequentially in VHDL?
with
process statements
☺

12. What is a process?
A process statement is a concurrent statement, but all
statements contained in it are sequential statement
(statements that executes serially, one after the other).

13. Flip Flop (FF)
• DFF
process (CLK)
begin
if (CLK’event and CLK = ’1’) then
Q <= D;
end if;
end process;
process
begin
wait until rising_edge(CLK);
Q <= D;
end process;
D
CLK
Q

14. FF with reset
• Synchronous
process (CLK, RST)
begin
if (RST = '1') then
Q <= '0';
elsif (CLK'event and CLK = '1') then
Q <= D;
end if;
end process;
D
CLK
Q
RST

15. FF with reset
• Asynchronous
process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RST = '1') then
Q <= '0';
else
Q <= D;
end if;
end if;
end process;
D
CLK
Q
RST

16. FF with reset and enable
• Synchronous
• Asynchronous
process
begin
wait until rising_edge(CLK) and CLKEN = ’1’;
Q <= D;
end process;
D
CLK
Q
RST

17. FF with reset and enable
architecture …
begin
signal A, B, C;
process (CLK)
begin
if (CLK'event and CLK = '0') then
C <= A * B;
end if;
end process;
…
end architecture;
D
CLK
Q
RST

18. Example #1
A
CLK
C
RST
B

19. References

20. • Zainalabedin Navabi, “Verilog Digital System Design”, 2th edition.
• Zainalabedin Navabi, “VHDL modular Design and Synthesis of cores and
Systems”, 3th edition.
• Morteza Saheb Zamani, FPGA course slides, Spring 2016.

21. Siavash Kavousi
Parham Alvani
Thank you !
Any Questions ?