solution of question no.6inputPresent stateNext stateoutput.pdf

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solution of question no.6 input Present state Next state output 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0 1 S1 S1 0 0 S2 S3 0 1 S2 S1 0 0 S3 S0 0 1 S3 S4 0 0 S4 S2 1 1 S4 S1 1 library ieee; use IEEE.std_logic_1164.all; entity moore is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end moore; architecture behavioral of moore is type state_type is (s0,s1,s2,s3,s4); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset=\'1\') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is \"s0\" if(input =\'0\') then output <= \'0\'; next_s <= s0; else output <= \'0\'; next_s <= s1; end if; when s1 =>; --when current state is \"s1\" if(input =\'0\') then output <= \'0\'; next_s <= s2; else output <= \'0\'; next_s <= s1; end if; when s2 => --when current state is \"s2\" if(input =\'0\') then output <= \'0\'; next_s <= s3; else output <= \'0\'; next_s <= s1; end if; when s3 => --when current state is \"s3\" if(input =\'0\') then output <= \'1\'; next_s <= s0; else output <= \'0\'; next_s <= s4; end if; when s4 => --when current state is \"s4\" if(input =\'0\') then output <= \'1\'; next_s <= s2; else output <= \'1\'; next_s <= s1; end if; end case; end process; end behavioral; solution of question no.7 input Present state Next state output 0 S0 S1 0 1 S0 S0 0 0 S1 S1 0 1 S1 S2 0 0 S2 S3 0 1 S2 S0 0 0 S3 S1 0 1 S3 S2 1 library ieee; use IEEE.std_logic_1164.all; entity mealy is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end mealy; architecture behavioral of moore is type state_type is (s0,s1,s2,s3); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset=\'1\') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is \"s0\" if(input =\'0\') then output <= \'0\'; next_s <= s1; else output <= \'0\'; next_s <= s0; end if; when s1 =>; --when current state is \"s1\" if(input =\'0\') then output <= \'0\'; next_s <= s1; else output <= \'0\'; next_s <= s2; end if; when s2 => --when current state is \"s2\" if(input =\'0\') then output <= \'0\'; next_s <= s3; else output <= \'0\'; next_s <= s1; end if; when s3 => --when current state is \"s3\" if(input =\'0\') then output <= \'0\'; next_s <= s1; else output <= \'1\'; next_s <= s2; end if; end case; end process; end behavioral; input Present state Next state output 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0 1 S1 S1 0 0 S2 S3 0 1 S2 S1 0 0 S3 S0 0 1 S3 S4 0 0 S4 S2 1 1 S4 S1 1 Solution solution of que.

Education

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library ieee;
use IEEE.std_logic_1164.all;
entity moore is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end moore;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset='1') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;

--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is "s0"
if(input ='0') then
output <= '0';
next_s <= s0;
else
output <= '0';
next_s <= s1;
end if;
when s1 =>; --when current state is "s1"
if(input ='0') then
output <= '0';
next_s <= s2;
else
output <= '0';
next_s <= s1;
end if;
when s2 => --when current state is "s2"
if(input ='0') then
output <= '0';
next_s <= s3;
else
output <= '0';
next_s <= s1;
end if;
when s3 => --when current state is "s3"
if(input ='0') then
output <= '1';

next_s <= s0;
else
output <= '0';
next_s <= s4;
end if;
when s4 => --when current state is "s4"
if(input ='0') then
output <= '1';
next_s <= s2;
else
output <= '1';
next_s <= s1;
end if;
end case;
end process;
end behavioral;
solution of question no.7
input
Present state
Next state
output
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S0
S1
0
1
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S0
0
0
S1
S1
0
1

S1
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library ieee;
use IEEE.std_logic_1164.all;
entity mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end mealy;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin

process (clk,reset)
begin
if (reset='1') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is "s0"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '0';
next_s <= s0;
end if;
when s1 =>; --when current state is "s1"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '0';
next_s <= s2;
end if;
when s2 => --when current state is "s2"
if(input ='0') then
output <= '0';
next_s <= s3;

else
output <= '0';
next_s <= s1;
end if;
when s3 => --when current state is "s3"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '1';
next_s <= s2;
end if;
end case;
end process;
end behavioral;
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
0

1
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1
Solution
solution of question no.6
input
Present state
Next state
output

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S0
0
1
S0
S1
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library ieee;
use IEEE.std_logic_1164.all;
entity moore is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end moore;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset='1') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is "s0"

if(input ='0') then
output <= '0';
next_s <= s0;
else
output <= '0';
next_s <= s1;
end if;
when s1 =>; --when current state is "s1"
if(input ='0') then
output <= '0';
next_s <= s2;
else
output <= '0';
next_s <= s1;
end if;
when s2 => --when current state is "s2"
if(input ='0') then
output <= '0';
next_s <= s3;
else
output <= '0';
next_s <= s1;
end if;
when s3 => --when current state is "s3"
if(input ='0') then
output <= '1';
next_s <= s0;
else
output <= '0';
next_s <= s4;
end if;
when s4 => --when current state is "s4"

if(input ='0') then
output <= '1';
next_s <= s2;
else
output <= '1';
next_s <= s1;
end if;
end case;
end process;
end behavioral;
solution of question no.7
input
Present state
Next state
output
0
S0
S1
0
1
S0
S0
0
0
S1
S1
0
1
S1
S2
0
0
S2
S3

0
1
S2
S0
0
0
S3
S1
0
1
S3
S2
1
library ieee;
use IEEE.std_logic_1164.all;
entity mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end mealy;
architecture behavioral of moore is
type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
begin
process (clk,reset)
begin
if (reset='1') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then

current_s <= next_s; --state change.
end if;
end process;
--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is "s0"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '0';
next_s <= s0;
end if;
when s1 =>; --when current state is "s1"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '0';
next_s <= s2;
end if;
when s2 => --when current state is "s2"
if(input ='0') then
output <= '0';
next_s <= s3;
else
output <= '0';
next_s <= s1;
end if;

when s3 => --when current state is "s3"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '1';
next_s <= s2;
end if;
end case;
end process;
end behavioral;
input
Present state
Next state
output
0
S0
S0
0
1
S0
S1
0
0
S1
S2
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1
S1
S1
0
0
S2

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S2
S1
0
0
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S0
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1
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0
0
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1
1
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S1
1

Hi please find my code. import java.util.HashMap; import java.util.Map; public class Max3Bag { private HashMap map; public Max3Bag() { map = new HashMap<>(); } public void add(String element){ if(map.containsKey(element)){ // if map already contains this element if(map.get(element) < 3) // if count is less than 3 then add this element with count incremented by 1 map.put(element, map.get(element)+1); }else map.put(element, 1); // if element is not in map then add it it map with count 1 } public void remove(String element){ if(map.containsKey(element)){// if element is in map if(map.get(element) == 1) // if count is 1 then remove from map map.remove(element); else // else decrement count by 1 map.put(element, map.get(element)-1); } } public boolean member(String element){ return map.containsKey(element); } public void print(){ // get each entry of map and print key and value for(Map.Entry entry : map.entrySet()){ System.out.println(entry.getKey()+\"=\"+entry.getValue()); } } } public class Max3BagTest { public static void main(String[] args) { Max3Bag A = new Max3Bag(); A.add(\"a\"); A.add(\"a\"); A.add(\"a\"); A.add(\"a\"); A.add(\"b\"); A.add(\"b\"); A.add(\"b\"); A.remove(\"a\"); A.add(\"c\"); A.print(); } } /* Sample Output: a=2 b=3 c=1 */ Solution Hi please find my code. import java.util.HashMap; import java.util.Map; public class Max3Bag { private HashMap map; public Max3Bag() { map = new HashMap<>(); } public void add(String element){ if(map.containsKey(element)){ // if map already contains this element if(map.get(element) < 3) // if count is less than 3 then add this element with count incremented by 1 map.put(element, map.get(element)+1); }else map.put(element, 1); // if element is not in map then add it it map with count 1 } public void remove(String element){ if(map.containsKey(element)){// if element is in map if(map.get(element) == 1) // if count is 1 then remove from map map.remove(element); else // else decrement count by 1 map.put(element, map.get(element)-1); } } public boolean member(String element){ return map.containsKey(element); } public void print(){ // get each entry of map and print key and value for(Map.Entry entry : map.entrySet()){ System.out.println(entry.getKey()+\"=\"+entry.getValue()); } } } public class Max3BagTest { public static void main(String[] args) { Max3Bag A = new Max3Bag(); A.add(\"a\"); A.add(\"a\"); A.add(\"a\"); A.add(\"a\"); A.add(\"b\"); A.add(\"b\"); A.add(\"b\"); A.remove(\"a\"); A.add(\"c\"); A.print(); } } /* Sample Output: a=2 b=3 c=1 */.

Hi please find my code.import java.util.HashMap;import java.util.pdf

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Given below is the code for the question. Since the test files (mentioned in question) are missing, I wrote a small test for the implementation. Output is shown at the end. Please don\'t forget to rate the answer if it helped. Thank you. sequence2.cpp #include \"sequence2.h\" using namespace CISP430_A2; sequence::sequence(size_type entry ) { capacity = entry; used = 0; current_index = 0; data = new value_type[capacity]; } // COPY CONSTRUCTOR sequence::sequence(const sequence& entry) { data = NULL; *this = entry; } // Library facilities used: cstdlib // MODIFICATION MEMBER FUNCTIONS void sequence::start( ) { current_index = 0; } void sequence::advance( ) { if(is_item()) current_index++; } void sequence::insert(const value_type& entry) { if(size() == capacity) //check if resizing is needed { resize(capacity * 1.1); //increaase by 10% } if(is_item() && current_index > 0) current_index--; else current_index = 0; for(size_type i = size(); i > current_index; i--) data[i] = data[i-1]; data[current_index] = entry; used++; } void sequence::attach(const value_type& entry) { if(size() == capacity) //check if resizing is needed { resize(capacity * 1.1); //increaase by 10% } if(!is_item()) current_index = used; else current_index++; //make room for new entry by pushing elements after current to right for(size_type i = size(); i > current_index ; i--) data[i] = data[i-1]; data[current_index] = entry; used++; } void sequence::remove_current( ) { if(is_item()) { for(size_type i = current_index + 1; i < size(); i++) data[i-1] = data[i]; used--; } } void sequence::resize(size_type new_capacity ) { if(new_capacity > capacity) { value_type *temp = new value_type[new_capacity]; for(int i = 0; i < used; i++) temp[i] = data[i]; delete []data; data = temp; } } void sequence::operator =(const sequence &entry) { if(data != NULL) delete []data; capacity = entry.capacity; used = entry.used; current_index = entry.current_index; data = new value_type[capacity]; for(int i = 0; i < used; i++) data[i] = entry.data[i]; } // CONSTANT MEMBER FUNCTIONS sequence::size_type sequence::size( ) const { return used ; } bool sequence::is_item( ) const { return size() != 0 && current_index < used; } sequence::value_type sequence::current( ) const { return data[current_index]; } //Destructor sequence::~sequence() { delete []data; } output attach 1 2 3 [1 2 3 ] advance after print... so should not have current item is_item() = 0 insert 4 5 6, should appear in front of seq as 6 5 4 print from current [6 5 4 1 2 3 ] print from current [7 5 4 1 2 3 ] Solution Given below is the code for the question. Since the test files (mentioned in question) are missing, I wrote a small test for the implementation. Output is shown at the end. Please don\'t forget to rate the answer if it helped. Thank you. sequence2.cpp #include \"sequence2.h\" using namespace CISP430_A2; sequence::sequence(size_type entry ) { capacity = entry; used = 0; current_index = 0; data = new value_type[capacity]; } // COPY CONSTR.

Given below is the code for the question. Since the test files (ment.pdf

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\"Cisco Systems, Inc: Acquisition Integration for manufacturing\" at glance. Cisco Systems Inc, a multi-billion dollar networking device manufacturing and software company. Cisco Systems started by a married couple, namely Sandy Lerner and Leonard Bosack working at Stanford University in their home garage. Apart from above mentioned founders, David Keller has been an influential force in driving the success of the company in initial stages of the company. He has been in the roles of Vice President of Manufacturing, New Product Introduction and Technology at Cisco Systems Inc. The very important aspect of the success in the company’s strategy in handling competition from the emerging network manufacturing companies was to maintain the quality as well the scalability in their product dimensions. In the process of capturing the market of networking the computers worldwide, Cisco has been vital in acquisitioning various small hardware to large hardware manufacturing companies, also to a good extent with network software companies and integrating all these numerous companies. Cisco Systems has acquisitioned nearly 40 plus companies throughout its journey of expanding and capturing the emerging computer networking market by providing them with world class and first of its devices like hubs, multiport switches and routers and other small networking devices. Its strategy was not only to acquire the company but, also to integrate very well with the policies and structure of Cisco’s capability. During the integration process, Cisco does make sure that it retains the best employees of the acquisitioned companies and also give them the same kind of best benefits which is prevailing in Cisco. Also, whenever Cisco acquires a new manufacturing company, its biggest task is to introduce and market their product and it does by their strategy called “New Product Introduction” by which, they market their product for attaining and capturing highest possible market share and in revenue creation as fast as possible before any new entity can think of doing it. When Cisco thinks of acquiring the company, there is a very strong process involving in analyzing the company which is going to get acquired by sending Cisco’s top management from crucial departments like Manufacturing, Finance, Planning, Technology division, Resource planning and Administration. This is to ensure and check the return of investment, future cost of bearing the company to be acquired, Feasibility check and scalability too. Cisco has mandatory Manufacturing Integrations steps which is carefully evaluated before acquiring and integrating the company to its portfolio: All these are the reason why, a company like Cisco has proven track record of becoming the world leader in Network Product and Technology Manufacturing Company. Thank you. Solution \"Cisco Systems, Inc: Acquisition Integration for manufacturing\" at glance. Cisco Systems Inc, a multi-billion dollar networking device manufacturing and .

Cisco Systems, Inc Acquisition Integration for manufacturing at.pdf

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As we understand, when soil particles binds to each other more strongly and forms groups called as soil aggregates and their stability is defines in terms of resisting disintegration of soil particles when disruptive forces associated with tillage and water or wind erosion are applied externally. Changes in aggregate stability indicate about recovery or degradation of soils. Further Aggregate stability is an indicator of organic matter content, biological activity, and nutrient cycling in soil. Microbial decomposition of fresh organic matter releases products (that are less stable) that bind small aggregates into large aggregates (> 2-5 mm). These large aggregates are more sensitive to management effects on organic matter. Greater amounts of stable aggregates suggest better soil quality. When the proportion of large to small aggregates increases, soil quality generally increases. Pore space is also essential for air and water entry into soil, and for air, water, nutrient, and biota movement within soil. Stable aggregates favor high infiltration rates and appropriate aeration for plant growth. Factors affecting aggregate stability can be grouped as abiotic (clay minerals, sesquioxides, exchangeable cations), biotic (soil organic matter, activities of plant roots, soil fauna and microorganisms), and environmental (soil temperature and moisture). Soil microorganisms like bacteria, actinomycetes, fungi, algae and protozoa played a vital role in maintaining stability of soil through the bio physicochemical activities in the soil through deposition of extracellular polysaccharides and formation of degraded, aromatic humic materials that form clay–polyvalent metal–organic matter complexes. In short, it is understood that activities of soil organisms interact in a complex food web with herbivores and predators, detritivores , on fungi or on bacteria, and others living off but not consuming their hosts (parasites). Soil fauna and most fungi, bacteria and actinomycetes are heterotrophs, they rely on organic materials either directly (primary consumers) or through intermediaries (secondary or tertiary consumers) for C and energy needs. Actinomycetes are a broad group of bacteria that form thread-like filaments in the soil. Actinomycetes form associations with some non- leguminous plants and fix N, which is then available to both the host and other plants in the near vicinity. Bacteria produce a sticky substance in the form of polysaccharides that helps bind soil particles into small aggregates, conferring structural stability to soils. Decomposers like saprophytic fungi - convert dead organic material into fungal biomass, CO2, and small molecules, such as organic acid. Mycorrhizae extend plant reach to water and nutrients, allowing plants to utilize more of the resources available in the soil. Arbuscular mycorrhizal fungi can also benefit the physical characteristics of the soil because their hyphae form a mesh to help stabilize soil aggregates thus in .

As we understand, when soil particles binds to each other more stron.pdf

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Amount deposited (base amount) = 2000Rate of interest = 5Amount.pdf

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24. Accomodation - n. Ability of lens to chhange shape diminishes as one ages 25. Astigmatism - o.Unequal curvatures of lens or cornea causing blurred vision 26.Audiometer - h. Measures frequency and intensity of audible range of sound 27.Auditory ossicles- l. transmit sound waves from tympanic membrane to inner ear 28.bitter taste- u.Produced by alkaloids detected on posterior tongue 29.Cochlea- b.contains sensory organs for hearing 30.conduction deafness y.intereference with conduction of sound vibrations to fluids of inner ear 31.emmetropia- p.Normal vision: light focuses on retina 32.glaucoma- v.increased intraocular pressure due to insufficient drainage of aqueous humor 33.gustatory cells- e.dendrites project through the pores in the taste bud 34. hypermyopia- d. Ability to focus for close vision under 20 feet 35.Iris- r. regulates the amount of light entering through the pupil of the eye 36.Myopia- a. near sightedness; inability to focus on objects farther away 37.near point- w. Closest point at which clear focus is possible 38.Nerve deafness- s.Neural structures relating to hearing have been damaged 39.Olfactory fatigue- g. Rapid adaptation of olfactory receptors to odors 40.Olfactory neurons- j.Receptors located in the superior nasal concha 41.Optic disk- t.Area of retina tha lacks photoreceptors; blind spot 42.presbyopia- m.Farsightedness; inability to focus on close objects 43.Rinne test- c.Differentiates between nerve and conduction deafness 44.salty taste- x.produced by cations of ionized salts 45.sour taste- i.produced by acids and detected on lateral edges of tongue 46.sweet taste- q.detected on tip of tongue 47.tympanic membrane- k.vibrates when soundwaves hit it; eardrum 48.weber test- f.base of tuning fork placed on forehead during hearing test Solution 24. Accomodation - n. Ability of lens to chhange shape diminishes as one ages 25. Astigmatism - o.Unequal curvatures of lens or cornea causing blurred vision 26.Audiometer - h. Measures frequency and intensity of audible range of sound 27.Auditory ossicles- l. transmit sound waves from tympanic membrane to inner ear 28.bitter taste- u.Produced by alkaloids detected on posterior tongue 29.Cochlea- b.contains sensory organs for hearing 30.conduction deafness y.intereference with conduction of sound vibrations to fluids of inner ear 31.emmetropia- p.Normal vision: light focuses on retina 32.glaucoma- v.increased intraocular pressure due to insufficient drainage of aqueous humor 33.gustatory cells- e.dendrites project through the pores in the taste bud 34. hypermyopia- d. Ability to focus for close vision under 20 feet 35.Iris- r. regulates the amount of light entering through the pupil of the eye 36.Myopia- a. near sightedness; inability to focus on objects farther away 37.near point- w. Closest point at which clear focus is possible 38.Nerve deafness- s.Neural structures relating to hearing have been damaged 39.Olfactory fatigue- g. Rapid adaptation of olfactory receptors to odo.

24. Accomodation - n. Ability of lens to chhange shape diminishes as.pdf

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1.They trade away higher fecundity for future reproduction. 2.Resources devoted to one function or trait cannot be devoted to another. For all organisms,natural selection favors allocation strategies that optimize resource use over the life course. Because energy and resources are inherently limited,all organisms face important trade-offs in how they divide and use their resources at any given point in the life course.The laws of thermodynamics dictate that energy allocated for one task cannot simultaneously be allocated for another task. Solution 1.They trade away higher fecundity for future reproduction. 2.Resources devoted to one function or trait cannot be devoted to another. For all organisms,natural selection favors allocation strategies that optimize resource use over the life course. Because energy and resources are inherently limited,all organisms face important trade-offs in how they divide and use their resources at any given point in the life course.The laws of thermodynamics dictate that energy allocated for one task cannot simultaneously be allocated for another task..

1.They trade away higher fecundity for future reproduction.2.Resou.pdf

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solution of question no.6inputPresent stateNext stateoutput.pdf

1. solution of question no.6 input Present state Next state output 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0 1 S1 S1 0 0 S2 S3 0 1 S2 S1 0 0 S3 S0 0 1 S3

2. S4 0 0 S4 S2 1 1 S4 S1 1 library ieee; use IEEE.std_logic_1164.all; entity moore is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end moore; architecture behavioral of moore is type state_type is (s0,s1,s2,s3,s4); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process;

3. --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0" if(input ='0') then output <= '0'; next_s <= s0; else output <= '0'; next_s <= s1; end if; when s1 =>; --when current state is "s1" if(input ='0') then output <= '0'; next_s <= s2; else output <= '0'; next_s <= s1; end if; when s2 => --when current state is "s2" if(input ='0') then output <= '0'; next_s <= s3; else output <= '0'; next_s <= s1; end if; when s3 => --when current state is "s3" if(input ='0') then output <= '1';

4. next_s <= s0; else output <= '0'; next_s <= s4; end if; when s4 => --when current state is "s4" if(input ='0') then output <= '1'; next_s <= s2; else output <= '1'; next_s <= s1; end if; end case; end process; end behavioral; solution of question no.7 input Present state Next state output 0 S0 S1 0 1 S0 S0 0 0 S1 S1 0 1

5. S1 S2 0 0 S2 S3 0 1 S2 S0 0 0 S3 S1 0 1 S3 S2 1 library ieee; use IEEE.std_logic_1164.all; entity mealy is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end mealy; architecture behavioral of moore is type state_type is (s0,s1,s2,s3); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin

6. process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0" if(input ='0') then output <= '0'; next_s <= s1; else output <= '0'; next_s <= s0; end if; when s1 =>; --when current state is "s1" if(input ='0') then output <= '0'; next_s <= s1; else output <= '0'; next_s <= s2; end if; when s2 => --when current state is "s2" if(input ='0') then output <= '0'; next_s <= s3;

7. else output <= '0'; next_s <= s1; end if; when s3 => --when current state is "s3" if(input ='0') then output <= '0'; next_s <= s1; else output <= '1'; next_s <= s2; end if; end case; end process; end behavioral; input Present state Next state output 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0

8. 1 S1 S1 0 0 S2 S3 0 1 S2 S1 0 0 S3 S0 0 1 S3 S4 0 0 S4 S2 1 1 S4 S1 1 Solution solution of question no.6 input Present state Next state output

9. 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0 1 S1 S1 0 0 S2 S3 0 1 S2 S1 0 0 S3 S0 0 1 S3 S4 0 0 S4 S2 1

10. 1 S4 S1 1 library ieee; use IEEE.std_logic_1164.all; entity moore is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end moore; architecture behavioral of moore is type state_type is (s0,s1,s2,s3,s4); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0"

11. if(input ='0') then output <= '0'; next_s <= s0; else output <= '0'; next_s <= s1; end if; when s1 =>; --when current state is "s1" if(input ='0') then output <= '0'; next_s <= s2; else output <= '0'; next_s <= s1; end if; when s2 => --when current state is "s2" if(input ='0') then output <= '0'; next_s <= s3; else output <= '0'; next_s <= s1; end if; when s3 => --when current state is "s3" if(input ='0') then output <= '1'; next_s <= s0; else output <= '0'; next_s <= s4; end if; when s4 => --when current state is "s4"

12. if(input ='0') then output <= '1'; next_s <= s2; else output <= '1'; next_s <= s1; end if; end case; end process; end behavioral; solution of question no.7 input Present state Next state output 0 S0 S1 0 1 S0 S0 0 0 S1 S1 0 1 S1 S2 0 0 S2 S3

13. 0 1 S2 S0 0 0 S3 S1 0 1 S3 S2 1 library ieee; use IEEE.std_logic_1164.all; entity mealy is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end mealy; architecture behavioral of moore is type state_type is (s0,s1,s2,s3); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then

14. current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0" if(input ='0') then output <= '0'; next_s <= s1; else output <= '0'; next_s <= s0; end if; when s1 =>; --when current state is "s1" if(input ='0') then output <= '0'; next_s <= s1; else output <= '0'; next_s <= s2; end if; when s2 => --when current state is "s2" if(input ='0') then output <= '0'; next_s <= s3; else output <= '0'; next_s <= s1; end if;

15. when s3 => --when current state is "s3" if(input ='0') then output <= '0'; next_s <= s1; else output <= '1'; next_s <= s2; end if; end case; end process; end behavioral; input Present state Next state output 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0 1 S1 S1 0 0 S2

16. S3 0 1 S2 S1 0 0 S3 S0 0 1 S3 S4 0 0 S4 S2 1 1 S4 S1 1

solution of question no.6inputPresent stateNext stateoutput.pdf

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