The document describes a digital clock design project implemented in VHDL. The clock displays hours and minutes in 24-hour format using 7-segment displays. Key components include a clockSecond module to generate clock pulses, a counter7seg module to count the time, an anodeController module to multiplex the displays, and a sevenSelect module to select the correct display digit based on the anode lines. The design was tested and able to correctly count and display the time in hours and minutes.

1. SEP
DGEST
INSTITUTO
TECNOLÓGICO
DE
SNEST
MATAMOROS
DEPARTAMENTO DE INGENIERÍA ELÉCTRICA Y ELECTRÓNICA
Diseño Digital con VHDL
Equipo:
Alumno(s):
Núm. de control:
Mario Arturo Cruz Colunga
11260077
Miguel Angel Fierros Peña
11260081
Hermenegildo Martínez de la Cruz
11260095
Jorge Alejandro Reyes Torres
11260108
H. MATAMOROS, TAM.
1 de Noviembre del 2013

2. Practica 9
Objetivo:
Realizar la implementación de un reloj que muestre las horas y minutos en formato 24 horas.
Material:
Laptop
Kit spartan3e
Software aldec HDL, xilinx ISE, adept.
Procedimiento:
Se crea nuevo proyecto en aldec HDL
Diagrama bde del reloj
U1
rst
rs t
U2
c lk O ut
c lk
c lk
clk
an0
an1
an2
anodeClock
U3
U5
an3
anodeController
rs t
an3
an0
an1
an2
an3
s e v enO ut(7:0 )
c lk O ut
an2
U8
c lk
clockSecond
U4
b inary In(3 :0 )
c lk
d ig itO ne (3:0 )
rs t
d ig itT e n(3 :0 )
binary7decoder
U6
b inary In(3 :0 )
start
pause
continue
s tart
d ig ithr00 (3:0 )
p aus e
d ig ithr11 (3:0 )
c o ntinue
counter7seg
an1
s e v enS eg m e nt(7:0 )
s e v enS eg m e nt(7:0 )
binary7decoder
U9
b inary In(3 :0 )
s e v enO ne (7:0 )
s e v enS eg m e nt(7:0 )
binary7decoder
U7
b inary In(3 :0 )
an0
s e v enS eg m e nt(7:0 )
binary7decoder
s e v e nT e n(7 :0 )
s e v e nhr0 (7 :0 )
s e v e nhr1 (7 :0 )
sevenSelect
sevenOut(7:0)

3. Código clocksecond
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityclockSecondis
port (
rst : in std_logic;
clk : in std_logic;
clkOut : outstd_logic
);
endclockSecond;
architecturebehavioral of clockSecondis
-- signalassignments
signalcounter : std_logic_Vector (27 downto 0);
signalclkOutSignal : std_logic;
begin
process (clk, rst)
begin
if (rst = '1') then
clkOutSignal<= '0';
counter<= (others => '0');
elsif (clk'event and clk = '1') then
if (counter = "1011111010111100001000000")then
counter<= (others => '0');
clkOutSignal<= notclkOutSignal;
else
counter<= counter + 1;
endif;
endif;
endprocess;
-- output assignments
clkOut<= clkOutSignal;
endbehavioral;
código counter7seg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binary7decoder is
port (
binaryIn : in std_logic_vector (3 downto 0);
sevenSegment : outstd_logic_vector (7 downto 0)
);
end binary7decoder;
architecturebehavioral of binary7decoder is
-- signaldeclerations

4. signalsevenSegmentSignal : std_logic_vector (7 downto 0);
begin
process (binaryIn)
begin
casebinaryInis
when "0000" =>
sevenSegmentSignal (6 downto 0) <= "1000000";
when "0001" =>
sevenSegmentSignal (6 downto 0) <= "1111001";
when "0010" =>
sevenSegmentSignal (6 downto 0) <= "0100100";
when "0011" =>
sevenSegmentSignal (6 downto 0) <= "0110000";
when "0100" =>
sevenSegmentSignal (6 downto 0) <= "0011001";
when "0101" =>
sevenSegmentSignal (6 downto 0) <= "0010010";
when "0110" =>
sevenSegmentSignal (6 downto 0) <= "0000010";
when "0111" =>
sevenSegmentSignal (6 downto 0) <= "1111000";
when "1000" =>
sevenSegmentSignal (6 downto 0) <= "0000000";
whenothers =>
sevenSegmentSignal (6 downto 0) <= "0010000";
end case;
endprocess;
-- dpisalwayszero
sevenSegmentSignal(7) <= '1';
-- output assignments
sevenSegment<= sevenSegmentSignal;
endbehavioral;
código binary7decoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter7seg is
port (
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
pause : in std_logic;
continue : in std_logic;
digitOne : outstd_logic_vector (3 downto 0);
digitTen : outstd_logic_vector (3 downto 0);
digithr00 :outstd_logic_vector (3 downto 0);

5. digithr11 :outstd_logic_vector (3 downto 0)
);
end counter7seg;
architecturebehavioral of counter7seg is
-- signalassignments
signaldigitOneSignal : std_logic_vector (3 downto 0);
signaldigitTenSignal : std_logic_vector (3 downto 0);
signal digithr0: std_logic_vector (3 downto 0);
signal digithr1 : std_logic_vector (3 downto 0);
typestatesis (resetState, countState, pauseState);
signalstate : states;
begin
process (clk, rst)
begin
if (rst = '1') then
state<= resetState;
elsif (clk'event and clk = '1') then
casestateis
whenresetState =>
digitOneSignal<= (others => '0');
digitTenSignal<= (others => '0');
if (start = '1') then
state<= countState;
endif;
whencountState =>
if (pause = '1') then
state<= pauseState;
endif;
if (digitOneSignal = "1001") then
digitOneSignal<= (others => '0');
digitTenSignal<= digitTenSignal + '1';
if (digitTenSignal = "0110") then
digitTenSignal<= (others =>'0');
digithr0 <= digithr0 + '1';
if (digithr0 ="0101") then
digithr0 <= (others =>'0');
digithr1 <= digithr1 + '1';
if (digithr1 = "0011")then
digithr1 <= (others =>'0');
endif;
endif;
endif;
else
digitOneSignal<= digitOneSignal + '1';
endif;
whenpauseState =>

6. if (continue = '1') then
state<= countState;
endif;
end case;
endif;
endprocess;
-- output signalassignments
digitOne<= digitOneSignal;
digitTen<= digitTenSignal;
digithr00 <= digithr0;
digithr11 <= digithr1;
endbehavioral;
anodecontroller
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityanodeControlleris
port (
clk : in std_logic;
an0 :outstd_logic;
an1 :outstd_logic;
an2 :outstd_logic;
an3 :outstd_logic
);
endanodeController;
architecturebehavioral of anodeControlleris
-- signaldeclerations
signal an0Signal : std_logic;
signal an1Signal : std_logic;
signal an2Signal : std_logic;
signal an3Signal : std_logic;
begin
process (clk)
begin
ifclk'event and clk='1' then
if an3Signal='1' then
an3Signal <= '0';
an2Signal <= '1';
an1Signal <= '0';
an0Signal <= '0';
endif;
if an2Signal='1' then
an2Signal <= '0';
an1Signal <= '1';
an3Signal <= '0';

7. an0Signal <= '0';
endif;
if an1Signal='1' then
an1Signal <= '0';
an0Signal <= '1';
an2Signal <= '0';
an3Signal <= '0';
endif;
if an0Signal='1' then
an0Signal <= '0';
an3Signal <= '1';
an3Signal <= '0';
an3Signal <= '0';
endif;
endif;
endprocess;
an0 <= not an0Signal;
an1 <= not an1Signal;
an2 <= not an2Signal;
an3 <= not an3Signal;
endbehavioral;
anodeclock
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityanodeClockis
port (
rst : in std_logic;
clk : in std_logic;
clkOut : outstd_logic
);
endanodeClock;
architecturebehavioral of anodeClockis
-- signalassignments
signalcounter : std_logic_Vector (19 downto 0);
signalclkOutSignal : std_logic;
begin
process (clk, rst)
begin
if (rst = '1') then
clkOutSignal<= '0';
counter<= (others => '0');
elsif (clk'event and clk = '1') then
if (counter = x"c350")then
counter<= (others => '0');

8. clkOutSignal<= notclkOutSignal;
else
counter<= counter + 1;
endif;
endif;
endprocess;
clkOut<= clkOutSignal;
endbehavioral;
códigosevenselect
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entitysevenSelectis
port (
an3 : in std_logic;
an2 : in std_logic;
an1 : in std_logic;
an0 : in std_logic;
sevenOne : in std_logic_vector (7 downto 0);
sevenTen : in std_logic_vector (7 downto 0);
sevenhr0 : in std_logic_vector (7 downto 0);
sevenhr1 : in std_logic_vector (7 downto 0);
sevenOut : outstd_logic_vector (7 downto 0)
);
endsevenSelect;
architecturebehavioral of sevenSelectis
signalsevenOutSignal : std_logic_vector (7 downto 0);
begin
process (an0,an1,an2, an3,sevenhr0,sevenhr1, sevenOne, sevenTen)
begin
if (an3 = '0') then
sevenOutSignal<= sevenone;
elsif (an2='0') then
sevenOutSignal<= seventen;
elsif (an1='0') then
sevenoutsignal<= sevenhr0;
else
sevenoutsignal<= sevenhr1;
endif;
endprocess;
sevenOut<= sevenOutSignal;
endbehavioral;
Observaciones y conclusiones:
El programa realiza la función de un reloj, contando las horas y minutos en formato de 24 horas, se realizó
mediante la modificación de la prácticadel cronometro.