1. A 32-bit single-cycle MIPS processor was implemented by coding each component in VHDL and connecting them together. The code was synthesized and a report showed a total memory usage of 270752 kilobytes. 2. To implement a 32-bit multi-cycle MIPS processor, changes were made to the single-cycle code including defining four registers between stages and connecting the input and output ports of corresponding components. Signals were defined to allow data transfer between register stages. The register files were then connected using port maps.

1. ‫کار‬ ‫گسارش‬
‫کامپیوتر‬ ‫معماری‬ ‫آزمایشگاه‬
‫تیمارچی‬ ‫استاد‬
:‫گروه‬ ‫اعضای‬
‫الهدی‬ ‫نجم‬ ‫الدین‬ ‫حسام‬ ‫سید‬
‫پور‬ ‫کریم‬ ‫امید‬
‫قمری‬ ‫حسام‬
‫بهار‬3131

2. :‫اول‬ ‫پروژه‬
32-bit single-cycle MIPS processor
‫ًام‬ ‫با‬ ‫ًْایی‬ ‫کذ‬ ‫در‬ ‫اتصاالت‬ ‫ًْایت‬ ‫در‬ ٍ ‫شذ‬ ُ‫زد‬ ‫هجسا‬ ‫طَر‬ ِ‫ب‬ ‫اجساء‬ ‫از‬ ‫ّرکذام‬ ‫کذ‬cpu.‫شذ‬ ‫اًجام‬
‫در‬ ِ‫گرفت‬ ‫قرار‬ ُ‫استفاد‬ ‫هَرد‬ ‫حجن‬ ُ‫پرٍش‬ ‫ایي‬ ‫در‬SynthesisReport:‫شذ‬ ‫گسارش‬ ‫زیر‬ ‫صَرت‬ ِ‫ب‬
Total memory usage is 270752 kilobytes

3. :‫دوم‬ ‫پروژه‬
32-bit multi-cycle MIPS processor
‫در‬ ُ‫شذ‬ ‫اعوال‬ ‫تغییرات‬‫کذ‬‫برای‬ ‫اٍل‬ ُ‫پرٍش‬:‫الیي‬ ‫پایپ‬ ‫کذ‬ ‫ًَشتي‬
1.‫بایذ‬ ‫ابتذا‬‫چْار‬register‫کرد‬ ‫تعریف‬ ‫را‬ ‫هیاًی‬:
‫ایي‬Register‫ّا‬ُ‫رًٍذ‬ ‫باال‬ ‫ی‬ ِ‫لب‬ ‫در‬‫ی‬clk،‫کٌٌذ‬ ‫هی‬ ُ‫رخیر‬ ‫خَد‬ ‫در‬ ‫را‬ ‫ّا‬ ‫ٍرٍدی‬:
if (clk'event and clk = '1') then …

4. ‫ی‬ ِ‫لب‬ ‫در‬ ٍُ‫رًٍذ‬ ‫پاییي‬‫ی‬clk:‫دٌّذ‬ ‫هی‬ ‫اًتقال‬ ‫خرٍجی‬ ِ‫ب‬ ‫را‬ ُ‫شذ‬ ُ‫رخیر‬ ‫اطالعات‬ ،
if (clk'event and clk = '0') then …
‫کذ‬Register‫ّا‬:‫است‬ ‫زیر‬ ‫صَرت‬ ِ‫ب‬
-‫رجیستر‬،‫اٍل‬IF/ID:
ENTITY fetch IS
Port (
pcin : in STD_LOGIC_VECTOR (31 downto 0);
pcout : out STD_LOGIC_VECTOR (31 downto 0);
instin : in STD_LOGIC_VECTOR (31 downto 0);
instout : out STD_LOGIC_VECTOR (31 downto 0);
clk : in STD_LOGIC
);
END fetch;
Architecture Behavioral of FETCH is
signal pc : std_logic_vector(31 downto 0);
signal instruction : std_logic_vector(31 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
pcout <= pc;
instout <= instruction;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '0') then
pc <= pcin;
instruction <= instin;

5. end if;
end process;
end Behavioral;
-‫رجیستر‬،‫دٍم‬ID/EXE:
Entity IDEX is
Port ( CLK : in std_logic;
PC4in : in STD_LOGIC_VECTOR (31 downto 0);
sgnextin : in STD_LOGIC_VECTOR (31 downto 0);
readdata1in : in STD_LOGIC_VECTOR (31 downto 0);
readdata2in : in STD_LOGIC_VECTOR (31 downto 0);
instruction2016in : in STD_LOGIC_VECTOR (4 downto 0);
instruction1115in : in STD_LOGIC_VECTOR (4 downto 0);
Alusrcin : in STD_LOGIC;
aluopin : in STD_LOGIC_VECTOR (1 downto 0);
regdstin : in STD_LOGIC;
branchcntin : in STD_LOGIC;
memwritecntin : in STD_LOGIC;
readmemcntin : in STD_LOGIC;
memtoregin : in STD_LOGIC;
regwritein : in STD_LOGIC;
PC4out : out STD_LOGIC_VECTOR (31 downto 0);
sgnextout : out STD_LOGIC_VECTOR (31 downto 0);
readdata1out : out STD_LOGIC_VECTOR (31 downto 0);
readdata2out : out STD_LOGIC_VECTOR (31 downto 0);
instruction2016out : out STD_LOGIC_VECTOR (4 downto 0);
instruction1115out : out STD_LOGIC_VECTOR (4 downto 0);
Alusrcout : out STD_LOGIC;
aluopout : out STD_LOGIC_VECTOR (1 downto 0);
regdstout : out STD_LOGIC;
branchcntout : out STD_LOGIC;
memwritecntout : out STD_LOGIC;
readmemcntout : out STD_LOGIC;
memtoregout : out STD_LOGIC;

6. regwriteout : out STD_LOGIC);
end IDEX;
Architecture Behavioral of IDEX is
signal PC4 : STD_LOGIC_VECTOR (31 downto 0):=X"00000000";
signal sgnext : STD_LOGIC_VECTOR (31 downto 0);
signal readdata1 : STD_LOGIC_VECTOR (31 downto 0);
signal readdata2 : STD_LOGIC_VECTOR (31 downto 0);
signal instruction2016 : STD_LOGIC_VECTOR (4 downto 0);
signal instruction1115 : STD_LOGIC_VECTOR (4 downto 0);
signal Alusrc : STD_LOGIC;
signal aluop : STD_LOGIC_VECTOR (1 downto 0);
signal regdst : STD_LOGIC;
signal branchcnt : STD_LOGIC;
signal memwritecnt : STD_LOGIC;
signal readmemcnt : STD_LOGIC;
signal memtoreg,regwrite : STD_LOGIC;
--signal PCsrc : STD_LOGIC;
begin
process (clk)
begin
if (clk'event and clk='1') then
PC4out <= PC4;
sgnextout <= sgnext;
readdata1out <= readdata1;
readdata2out <= readdata2;
instruction2016out <= instruction2016;
instruction1115out <= instruction1115;
alusrcout <= alusrc;
aluopout <= aluop;
regdstout <= regdst;
branchcntout <= branchcnt;
memwritecntout <= memwritecnt;
readmemcntout <= readmemcnt;
memtoregout <= memtoreg;

7. regwriteout<= regwrite;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '0') then
PC4 <= PC4in;
sgnext <= sgnextin;
readdata1 <= readdata1in;
readdata2 <= readdata2in;
instruction2016 <= instruction2016in;
instruction1115 <= instruction1115in;
alusrc <= alusrcin;
aluop <= aluopin;
regdst <= regdstin;
branchcnt <= branchcntin;
memwritecnt <= memwritecntin;
readmemcnt <= readmemcntin;
memtoreg <= memtoregin;
regwrite<= regwritein;
end if;
end process;
End Behavioral;
-‫رجیستر‬‫سَم‬،EXE/MEM:
Entity EXMEM is
Port ( mux5in : in STD_LOGIC_VECTOR (4 downto 0);
readdata2in : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
zeroin : in STD_LOGIC;
adderresultin : in STD_LOGIC_VECTOR (31 downto 0);
branchin : in STD_LOGIC;
memreadin : in STD_LOGIC;

8. memwritein : in STD_LOGIC;
memtoregin : in STD_LOGIC;
regwritein : in STD_LOGIC;
mux5out : out STD_LOGIC_VECTOR (4 downto 0);
readdata2out : out STD_LOGIC_VECTOR (31 downto 0);
aluresultout : out STD_LOGIC_VECTOR (31 downto 0);
zeroout : out STD_LOGIC;
adderresultout : out STD_LOGIC_VECTOR (31 downto 0);
branchout : out STD_LOGIC;
memreadout : out STD_LOGIC;
memwriteout : out STD_LOGIC;
memtoregout : out STD_LOGIC;
regwriteout : out STD_LOGIC;
clk : in STD_LOGIC);
end EXMEM;
Architecture Behavioral of EXMEM is
signal mux5 : STD_LOGIC_VECTOR (4 downto 0);
signal readdata2 : STD_LOGIC_VECTOR (31 downto 0);
signal aluresult : STD_LOGIC_VECTOR (31 downto 0);
signal zero : STD_LOGIC;
signal adderresult : STD_LOGIC_VECTOR (31 downto 0);
signal branch : STD_LOGIC;
signal memread : STD_LOGIC;
signal memwrite : STD_LOGIC;
signal memtoreg : STD_LOGIC;
signal regwrite : STD_LOGIC;
begin
process (clk)
begin
if (clk'event and clk='1') then
mux5out <= mux5;
readdata2out <= readdata2;
aluresultout <= aluresult;
zeroout <= zero;

9. adderresultout <= adderresult;
branchout <= branch;
memreadout <= memread;
memwriteout <= memwrite;
memtoregout <= memtoreg;
regwriteout <= regwrite;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '0') then
mux5 <= mux5in;
readdata2 <= readdata2in;
aluresult <= aluresultin;
zero <= zeroin;
adderresult <= adderresultin;
branch <= branchin;
memread <= memreadin;
memwrite <= memwritein;
memtoreg <= memtoregin;
regwrite <= regwritein;
end if;
end process;
End Behavioral;
-‫رجیستر‬‫چْارم‬،MEM/WB:
Entity MEMWB is
Port ( mux5in : in STD_LOGIC_VECTOR (04 downto 0);
aluresultin : in STD_LOGIC_VECTOR (031 downto 0);
datamemin : in STD_LOGIC_VECTOR (031 downto 0);
memtoregin : in STD_LOGIC;
regwritein : in STD_LOGIC;

10. clk : in STD_LOGIC;
mux5out : out STD_LOGIC_VECTOR (04 downto 0);
aluresultout : out STD_LOGIC_VECTOR (031 downto 0);
datamemout : out STD_LOGIC_VECTOR (031 downto 0);
memtoregout : out STD_LOGIC;
regwriteout : out STD_LOGIC);
end MEMWB;
Architecture Behavioral of MEMWB is
signal mux5 : STD_LOGIC_VECTOR (04 downto 0);
signal aluresult : STD_LOGIC_VECTOR (031 downto 0);
signal datamem : STD_LOGIC_VECTOR (031 downto 0);
signal memtoreg : STD_LOGIC;
signal regwrite : STD_LOGIC;
Begin
process (clk)
begin
if (clk'event and clk='1') then
mux5out <= mux5;
datamemout <= datamem;
aluresultout <= aluresult;
memtoregout <= memtoreg;
regwriteout <= regwrite;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '0') then
mux5 <= mux5in;
datamem <= datamemin;
aluresult <= aluresultin;
memtoreg <= memtoregin;
regwrite <= regwritein;

11. End if;
End process;
End Behavioral;
2.‫کردى‬ ‫تعریف‬ ‫از‬ ‫بعذ‬Registerِ‫ب‬ ‫ًَبت‬ ‫ّا‬Port Map.‫رسذ‬ ‫هی‬ ‫ّا‬ ‫آى‬ ‫کردى‬
‫بایذ‬ ‫ابتذا‬ ‫کار‬ ‫ایي‬ ‫برای‬Signal‫ّا‬ ‫سیگٌال‬ ‫ایي‬ ِ‫ک‬ ‫ای‬ ًَِ‫گ‬ ِ‫ب‬ ،‫کٌین‬ ‫تعریف‬ ‫را‬ ‫جذیذی‬ ‫ّای‬‫بتَاًٌذ‬‫ّای‬ ‫قسوت‬ ‫خرٍجی‬
‫ٍرٍدی‬ ِ‫ب‬ ‫را‬ ‫ًظر‬ ‫هَرد‬Register‫خرٍجی‬ ٍ ،‫ّا‬Register‫کٌذ‬ ‫هتصل‬ ِ‫هربَط‬ ‫ّای‬ ‫قسوت‬ ‫ٍرٍدی‬ ِ‫ب‬ ‫را‬ ‫ّا‬.
‫هثال‬ ‫برای‬ِ‫ب‬ ‫ًیاز‬ ،ٍ‫رٍبر‬ ‫حالت‬ ‫در‬
‫یک‬ ‫تعریف‬Register32-bit‫دارین‬ِ‫ب‬ ،
‫خرٍجی‬ ِ‫ک‬ ‫صَرتی‬ID/EX registerِ‫ب‬ ‫را‬
‫ٍرٍدی‬ALU:‫کٌذ‬ ‫هتصل‬
signal Readdata1_id : STD_LOGIC_VECTOR (31 downto 0);
ِ‫ب‬ ‫بایذ‬ ‫بعذ‬ ِ‫هرحل‬ ‫در‬Port Map‫کردى‬Register‫ّا‬‫هیاًی‬ ‫ی‬.‫بپردازین‬
‫هث‬ ‫برای‬:‫کٌین‬ ‫هی‬ ‫عول‬ ‫شکل‬ ‫ایي‬ ِ‫ب‬ ،‫باال‬ ‫حالت‬ ‫در‬ ‫ال‬
u4 : Register_File Port Map (...,Readdata1,...);
‫در‬ ِ‫ک‬،‫حالت‬ ‫ایي‬Readdata1،‫قسوت‬ ‫خرٍجی‬ ‫سیگٌال‬Register_File‫ٍرٍدی‬ ِ‫ب‬ ‫را‬ ‫آى‬ ‫بایذ‬ ٍ ‫است‬IDEX Register
:‫کٌین‬ ‫هتصل‬
u19 : IDEX Port Map (clk,...,Readdata1,...);

12. 3.‫از‬ ‫بعذ‬Port Map‫کردى‬Register‫بایذ‬ ،‫ّا‬Port Mapِ‫ک‬ ‫را‬ ‫ّایی‬ ‫قسوت‬‫از‬ ‫را‬ ‫شاى‬ ‫ٍرٍدی‬Register‫هی‬ ‫ّا‬
.‫کٌین‬ ‫اصالح‬ ،‫گیرًذ‬
‫ه‬ ‫برای‬‫ث‬:‫دارین‬ ‫باال‬ ‫حالت‬ ‫در‬ ‫ال‬
u19 : IDEX Port Map (clk,...,Readdata1_id,...);
‫در‬ ِ‫ک‬،‫حالت‬ ‫ایي‬Readdata1_id،‫قسوت‬ ‫خرٍجی‬ ‫سیگٌال‬IDEX Register‫ٍرٍدی‬ ِ‫ب‬ ‫را‬ ‫آى‬ ‫بایذ‬ ٍ ‫است‬ALU
:‫کٌین‬ ‫هتصل‬
u8 : ALU Port Map (Readdata1_id, ALUinput2, ALUfunc, Zero, ALUOutput);
4‫در‬ ‫تغییراتی‬ ‫بایذ‬ ‫ًْایت‬ ‫در‬ .Mux‫ی‬ِ‫ک‬‫ٍرٍدی‬PC.‫کٌین‬ ‫اعوال‬ ،‫کٌذ‬ ‫هی‬ ‫هشخص‬ ‫را‬
ُ‫استفاد‬ ‫هَرد‬ ‫حجن‬ ُ‫پرٍش‬ ‫ایي‬ ‫در‬(‫تاخیر‬ ‫ًیس‬ ٍDelay)،‫در‬SynthesisReport:‫شذ‬ ‫گسارش‬ ‫زیر‬ ‫صَرت‬ ِ‫ب‬
Total memory usage is 239904 kilobytes.
Minimum period: 12.098ns (Maximum Frequency: 82.658MHz)
Minimum input arrival time before clock: 4.361ns
Maximum output required time after clock: 4.749ns
ُ‫پرٍش‬ ٍ‫د‬ ‫ّر‬ ‫کاهل‬ ‫کذ‬.‫گردد‬ ‫هی‬ ِ‫ارائ‬ ‫پیَست‬ ِ‫ب‬