This document describes the design and implementation of a traffic light controller using an 8255 PPI (Programmable Peripheral Interface) chip in an 8085 microprocessor environment. It includes circuit diagrams for the traffic light signals, coding for the traffic light sequences, and an assembly language program that uses delays in a loop to control the light sequences. Memory-mapped I/O is used to control the 8255 PPI pins that output to the traffic lights. Formulas are provided to calculate delay times based on the number of T-states (clock cycles) needed by each instruction.

1. Department of Electrical and Electronic
Engineering
Khulna University of Engineering & Technology
Khulna-9203
Course code : EE 3214
Sessional on
Microprocessors, Micro-controllers and Peripherals
Presented By
Amit Kumer Podder
Experiment No. 04

2. Design and implementation of traffic light
controller using 8255 PPI in 8085
microprocessor environment
Experiment Name
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3. G3 Y3 R3
G4 Y4 R4G2 Y2 R2
G1 Y1 R1Road 1
Road 3 Road 4
Road 2
Traffic Signal Flow diagram
Road 3 & Road 4 are allowing Traffic
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4. G3 Y3 R3
G4 Y4 R4G2 Y2 R2
G1 Y1 R1Road 1
Road 3 Road 4
Road 2
Traffic Signal Flow diagram
Road 3 and Road 4 are allowing Traffic but in
delay mode
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5. G3 Y3 R3
G4 Y4 R4G2 Y2 R2
G1 Y1 R1Road 1
Road 3 Road 4
Road 2
Traffic Signal Flow diagram
Road 1 & Road 2 are allowing Traffic
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6. G3 Y3 R3
G4 Y4 R4G2 Y2 R2
G1 Y1 R1Road 1
Road 3 Road 4
Road 2
Traffic Signal Flow diagram
Road 1 and Road 2 are allowing Traffic but
in delay mode
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7. Traffic signal generating coding table
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
0 0 G2 Y2 R2 G1 Y1 R1 0 0 G4 Y4 R4 G3 Y3 R3
R1 R2 G3 G4 0 0 0 0 1 0 0 1
= 09H
0 0 1 0 0 1 0 0
=24H
Y1 Y2 Y3 Y4 0 0 0 1 0 0 1 0
= 12H
0 0 0 1 0 0 1 0
= 12H
R3 R4 G1 G2 0 0 1 0 0 1 0 0
= 24H
0 0 0 0 1 0 0 1
= 09H
Y1 Y2 Y3 Y4 0 0 0 0 1 0 1 0
= 12H
0 0 0 1 0 0 1 0
= 12H
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8. Main Program in 8085: Traffic signal Control
Label Mnemonics
Opcode Operand
Start MVI A,80H
OUT 23H
MVI A,09H
OUT 20H
MVI A,24H
OUT 21H
CALL DELAY
MVI A,12H
OUT 20H
MVI A,12H
OUT 21H
CALL DELAY
MVI A,24H
OUT 20H
MVI A,09H
OUT 21H
CALL DELAY
MVI A,12H
OUT 20H
MVI A,12H
OUT 21H
CALL DELAY
JMP START
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9. Subroutine: Delay
Label Mnemonics T-States
Opcode Operand
Delay MVI D,FFH 7
LOOP1 NOP 4
NOP 4
NOP 4
NOP 4
NOP 4
MVI E,FFH 7
LOOP2 NOP 4
NOP 4
NOP 4
NOP 4
NOP 4
DCR E 4
JNZ LOOP2 7/10
DCR D 4
JNZ LOOP1 7/10
RET 10
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10. Delay Calculation
Delays
• Each instruction passes through different combinations of
Fetch, Memory Read, and Memory Write cycles.
• Knowing the combinations of cycles, one can calculate how
long such an instruction would require to complete.
• The table in Appendix F of the book contains a column with
the title B/M/T. – B for Number of Bytes – M for Number of
Machine Cycles – T for Number of T-State.
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11. Cycles and States
• From the above discussion, we can define terms that will become
handy later on:
• T- State: One subdivision of an operation. A T-state lasts for one
clock period.
• An instruction’s execution length is usually measured in a
number of T-states. (clock cycles).
• Machine Cycle: The time required to complete one operation of
accessing memory, I/O, or acknowledging an external request.
• This cycle may consist of 3 to 6 T-states.
• Instruction Cycle: The time required to complete the execution of
an instruction.
• In the 8085, an instruction cycle may consist of 1 to 6 machine
cycles.
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12. Contd.
• Knowing how many T-States an instruction requires, and
keeping in mind that a T-State is one clock cycle long, we
can calculate the time using the following formula: Delay =
No. of T-States / Frequency
• For example a “MVI” instruction uses 7 T-States. Therefore,
if the Microprocessor is running at 2 MHz, the instruction
would require 3.5 µSeconds to complete.
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13. • We can use a loop to produce a certain amount of time delay
in a program.
• The following is an example of a delay loop:
MVI C, FFH 7 T-States
LOOP DCR C 4 T-States
JNZ LOOP 10/7 T-States
• The first instruction initializes the loop counter and is
executed only once requiring only 7 T-States.
• The following two instructions form a loop that requires 14
T-States to execute and is repeated 255 times until C
becomes 0.
Contd.
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14. • We need to keep in mind though that in the last iteration
of the loop, the JNZ instruction will fail and require
only 7 T-States rather than the 10.
• Therefore, we must deduct 3 T-States from the total
delay to get an accurate delay calculation.
• To calculate the delay, we use the following formula:
Tdelay = TO + TL – Tdelay
= total delay – TO
= delay outside the loop – TL
= delay of the loop
• TO is the sum of all delays outside the loop.
Contd.
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15. Using these formulas, we can calculate the time delay
for the previous example:
TO = 7 T-States – Delay of the MVI instruction
TL = (14 X 255) - 3
= 3567 T-States
14 T-States for the 2 instructions repeated 255 times
(FF16 = 25510) reduced by the 3 T-States for the
final JNZ.
Contd.
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16. Now,
Do The Experiment
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