Programming, Memory Interfacing

1. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Programming, Memory Interfacing
UNIT 3

2. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Timing and Delays

3. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
●The MP system consists of two basic components : harware and software. The
software components controls and operates the hardware to get the desired
output with the help of instructions.
●To execute these instructions, MP takes fixed time as per the instruction, since it
is driven by the constant frequency clock. This makes it possible to introduce
delay for specific time between two events.
●Every MP has an internal clock that regulates the speed at it which it executes
the instructions and also synchronize it with other components.
●The speed at which MP executes instructions is called clock speed (1MHz to
1GHz).

4. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Time Delay Using NOP Instruction
● NOP instruction comes under machine control instructions.
● When this instruction is executed by the MP, MP perform no operation.
● The NOP instruction does nothing but takes 3 clock cycles of processor time
to execute.
● By executing NOP instruction in between two instructions we can generate
delay of 3 clock cycles.
● Hence NOP is a useful instruction to generate a delay.

5. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Time Delay Using Counters
● Counting can create time delays. Since the execution times of the instructions
used in a counting routine are known, the initial value of the counter requires
specific time.
Clock cycles required
MOV CX, COUNT : load count 4
BACK: DEC CX : decrement count 2
JNZ BACK : if count!=0, repeat 16/4
If count!=0 If count=0

6. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● In this program, the instruction DEC CX and JNZ BACK execute number of
times equal to count value stored in the CX register. In this way delay
generated.
● The time taken by this program for execution can be calculated with the help
of clock cycles. The column to the right of the comments indicates the number
of clock cycles required for the execution of each instruction.
● Two values are specified for the number of clock cycles for the JNZ
instruction, the smaller value is applied when the condition is not met and
larger is applied when condition is met.

7. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Here the first instruction MOV CX, count is executed only once and requires 4 clock
cycles.
● There are count – 1 passes through the loop where the condition is met and control is
transferred back to the first instruction in the loop(DEC CX)
● The number of clock cycles that elapse while CX register is not zero are (count - 1)*
(2+16)
● On the last pass through the loop, when the condition is not met the loop is terminated.
The number of clock cycles that elapses in this pass are (2+4).
● There total clock cycles required to execute the given program is
4 + (count - 1)* (2+16) + (2+4)
MOV CX, Count
Loop Count!=0
Last loop Count=0

8. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Assuming operating frequency of 8086 MP is 10MHz then time required for
1clock-cycle = 1/10MHz = 0.1µsec.
● Therefore, time required for execution of a given program with count = 100 is
179.2 µsec (1792 * 0.1)
= [4 + (100 - 1)* (2+16) + (2+4)] = 1792
● Which means 179.2 µsec of delay occurs when the program runs with count
value of 100.

9. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Time delay when time is known
● In the previous program we have calculated the time required for the
execution of program or delay introduced by program when count value is
given.
● However when the delay time is known it is necessary to determine the count
that is to be loaded in CX register.
● Let us consider that we have to generate a delay of 50msec using 8086 MP
that runs at 10MHz clock frequency.
● For the same program we can calculate the count value as follows

10. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Step 1: Calculate the number of required clock cycles
Number of required clock cycles = Required delay time
Time for 1clock cycle
= 50msec/0.1µsec = 500000
Step 2: Find the required count
Count = No. of required clock cycles – 4 – (2+4)
Execution time for one loop
= 500000 – 4 – 6
16+2
+1
+1 = 27778 = 6C82H

11. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Time Delay Using Nested Loops
● In this program one more external loop is added to execute the internal loop
multiple times so that we can get larger delays.
● The inner loop is nothing but the program we have seen in the previous
section.
MOV BX, Multiplier count : load multiplier count
REPE: MOV CX, COUNT : load count
BACK: DEC CX : decrement count
JNZ BACK : if count!=0, repeat
DEC BX : decrement multiplier count
JNZ REPE : if not zero repeat

12. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● In delay calculations of nested loops, the delay introduced by inner loop is very large in
comparison with the delay produced by external loop i.e. MOV BX, COUNT , DEC BX and
JNZ instructions.
● Therefore it is not necessary to consider the last loop for external loop delay calculations
separately. The inner loop calculations will remain as it is.
● Clock cycles required to execute the given program is
● For count = 100 and multiplier count = 50, the number of clock cycles required are
[4 + (100 - 1) * (2+16) + (2+4)] * 50
= 89600
[4 + (count - 1)* (2+16) + (2+4)] * Multiplier count

13. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Assuming operating frequency of 8086 MP is 10MHz
● Total time required for execution of a given program
= 89600 * 0.1µsec = 8.96msec (delay generated by nested loop)

14. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Program: Write an 8086 ALP to generate a delay of 1minute if 8086 system
frequency is 10MHz.
Step 1: Calculate the delay generated by inner loop with maximum count(FFFFH)
Delay generated by inner loop when count = FFFFH = 65535
= [4 + (65535 - 1) * (2+16) + (2+4)] * 0.1µsec
= 117.9622msec
Step 2: Calculate the multiplier count to get delay of 1minute
Multiplier count = required delay/delay provided by inner loop
= 1*60 sec/ 117.9622msec = 509 = 1FDH

15. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
DATA CONVERSIONS

16. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● User communicates with computer using input device and computer gives outcome
of process / result on the display devices or hardcopy devices such as printer or
plotter.
● Most commonly used input device is keyboard and most commonly used output
device is a display device i.e. video monitor.
● These devices understand the information in ASCII format.
● Keyboard gives the pressed key number or character in its ASCII equivalent and for
display we have to send the ASCII equivalent of number or character to the display
device.
● On the other hand, processor does not understand the ASCII format. It uses binary
numbers.
● Therefore it is necessary to convert input from keyboard to its binary equivalent
(ASCII to binary) and convert processed data by processor into ASCII format for
display (binary to ASCII conversion)

17. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Routines To Convert Binary to ASCII
1) By AAM Instruction (For number less than 100)
● The AAM instruction converts the value in AX into a two-digit unpacked BCD
number in AX.
● For example, if number in AX is 0059 (89 decimal) before execution of AAM
instruction.
● AX contains 0809 after execution of AAM instruction. Now we can get ASCII
equivalent by adding 3030H to AX.

18. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
00 59 08 09
08 09 38 39
AX
AH AL AH AL
AX
AH AL AH AL
AAM
ADD AX, 3030H

19. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Start
Save Registers
Get the Hex number
Convert into its decimal (BCD)
equivalent
Unpack the BCD digits
Add 30H in each BCD digit to
get its ASCII equivalent
Restore registers
Display each digit
End

20. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Algorithm
● Save the contents of all registers which are used in the routine.
● Get the data in AL register and make AH equal to 00.
● Use AAM instruction to convert number in its decimal equivalent in the
unpacked format
● ADD 30H in each digit to get its ASCII equivalent.
● Display digit one by one using function 2 of INT 21H
● Restore contents of registers.

21. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
2) By Series of Decimal Division
● If number is greater than 99 we cannot use AAM instruction to convert given
number in the BCD format.
● In such a case we use scheme of dividing by 10 to convert any whole number
from binary to an ASCII coded character string that can be displayed on the
monitor.
Assume : Hex number is 7BH

22. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
A 7Bh C
-78h
03
A C 1
- A
2
A 1 0
- 0
1
Quotient
01
02
03
01 + 30H = 31
02 + 30H = 32
03 + 30H = 33
ASCII
Remainder

23. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
10 123 12
-120
3
10 12 1
-10
2
10 1 0
- 0
1
Quotient
01
02
03
01 + 30H = 31
02 + 30H = 32
03 + 30H = 33
ASCII
Remainder Here 7B = 123

24. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Algorithm
● Save contents of all registers which are used in the routine.
● Divide the number by 10 and save the reminder on the stack as a significant
BCD digit.
● Save the quotient as a number
● Repeat step 1 and 2 until quotient is 0
● Retrieve each reminder from stack and add 30H to convert to ASCII before
displaying or printing.
● Restore contents of registers.

25. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Routine to Convert ASCII to Binary
● When we accept decimal number from keyboard we get ASCII code of each
decimal digit.
● The information from the keyboard must be converted from ASCII to binary.
● When a Single key is pressed conversion can be achieved by subtracting 30H
● However when more than one key is typed conversion from ASCII to binary
requires 30H to be subtracted.
● After subtracting 30H the number is added to the result after the prior result is
first multiplied by 10.

26. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Algorithm
● Save contents of all registers which are used in the routine
● Make binary result = 0
● Subtract 30H from the character typed on the keyboard to convert it to BCD
● Multiply the result by 10, and then add the new BCD digit.
● Repeat steps 2 and 3 until the character typed is not an ASCII coded number
● Restore register contents

27. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Ex: 256 D 100 H
Keystroke Key I/p Sub 30H Calculation
2 32H 32H – 30H 02
x 0A
14H
5 35H 35H – 30H + 05H
19H
x 0AH
FAH
6 36H 36H – 30H + 06H
100H
Multiply by 10
Multiply by 10
Add next digit
Add next digit

28. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Routine To Read Hexadecimal Data
● We know that hexadecimal numbers range from 0 to 9 and from A to F
● The keyboard gives ASCII codes for these hexadecimal numbers
● It gives 30h to 39H for numbers 0 to 9, gives 41H to 46H for A to F and 61H
to 66H for a to f letters.
● Hence to convert ASCII input from keyboard to corresponding hexadecimal
number we have to first check whether it is number or letter.
● If letter, check if its lower case or upper case letter.

29. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Algorithm
● Save registers
● Make result = 0
● Get the ASCII code for the character from keyboard and
■ Subtract 30H from it if character is 0 – 9
■ Subtract 37H from it if character is A – F
■ Subtract 57H from it if character is a – f
● Shift the result by 4-bits and add digit to pack binary digits
● Repeat steps 2 and 3 four times to get 4-digit hex number
● Restore registers

30. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Routine To Display Hexadecimal Data
● To display hexadecimal data we have to first unpack each digit (nibble) in the
given number.
● Then by adding 30H to digit having number between 0 to 9 and by adding
37H to digit having letter between A to F we can get ASCII equivalent of given
hexadecimal number.
● This can be achieved by rotating number left (nibble by nibble) and adding
30H or 37H into it.
● By rotating left we can display left most digit (MSD) first

31. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Algorithm
1. Save registers
2. Get the number and unpack digit from it
3. Add 30H if digit is 0 – 9 or add 37H if digit is A – F to get the ASCII code of
digit.
4. Display digit
5. Repeat steps 2, 3 and 4
6. Restore registers.

32. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
LOOK UP Tables for Data Conversion
● When number of possible conversions are small then lookup tables are often used
to convert data from one form to another form.
● For example, for conversion of BCD to 7-segment code there are 10 possible
conversions.
● A look up table is nothing but an array form in memory as a list of data that is
referenced by a procedure to perform conversions.
● A look up table can be stored in code segment or data segment.
● XLAT instruction by default access, byte from data segment
● To access a byte from code segment we have to modify XLAT instruction as
XLAT CS: TABLE

33. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Modular programming
● Modular programming is defined as the process of dividing a larger program
into smaller sub programs[modules].
● Each module is written and tested separately.
● When all modules are tested, they are linked together to form a large
program.
● Three assembly language components are used for the development of
modular program
1) Structure
2) Procedures or subroutines
3) Macros.

34. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Whenever we need to use a group of instructions several times throughout a
program there are two ways we can avoid having to write the group of
instructions each time we want to use them.
● One way is to write the group of instructions as separate procedure.
● For calling the procedure we need to store the return address onto the stack.
This process takes some time.
● If group of instructions is big enough then overhead time is negligible with
respect to execution time.
● But if group of instructions is too short, the overhead time and execution time
are comparable.
● For such cases we can use Macros
● The assembler places the macro instructions in the program each time it is
invoked. This procedure is known as Macro expansion.

35. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Procedure in 8086 Microprocessor
● Procedure is a set of instructions stored as separate program in the memory.
● Procedure is used to perform a specific task which can be called from the
main program whenever required.
Instructions used in procedure:
1) CALL – call procedure from main program
2) RET – return back to main program

36. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Types:
Depends on where the procedure is stored in the memory
i) Near Procedure
In this type, the procedure is present in the same code segment where
the main program is stored in the memory. For near procedure, CALL
instruction pushes only the IP register value on to the stack and no change in
the code segment.
ii) Far Procedure
In this type, the procedure is not available in the same code segment.
CALL instruction pushes both the contents of IP and CS register to call the
procedure.

37. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
iii) Reentrant Procedure
In this method, the flow of program execution reenters the procedure 1
from procedure 2 and then the main program. It is also called as Nested
procedure.

38. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
iv) Recursive Procedure
It is a procedure which calls itself. It is used to simplify the complex data
structures.
● Recursion depth N – defines the number of times the procedure to be
executed. N is decremented after each procedure call and continues till N=0.

39. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Passing parameters in Procedure
● Procedure requires some data or address variables from the main program
for its processing.
● The data or address variables are passed to the procedure using any one of
the following method.
a. Passing parameters using registers
b. Using memory
c. Using pointers
d. Using stack

40. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Macros in 8086 Microprocessor
● Macro is a sequence of instructions that is written within the macro assembler
directives.
● Machine code can be generated each time the macro is called.
● Parameters are passed as a part of statement which calls the macro program.
Format for creation of Macro:
INIT MACRO Define macro
---------
----------
ENDM; End of macro
Body of macro

41. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Advantages:
● CALL and RET instructions are not used in Macros
● No overhead time
● It executes faster than procedure
● It supports modular programming
Disadvantages:
● It requires more memory
● Machine code can be generated each time when the macro is called.

42. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA

43. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
8086 Signal Description (Pin Diagram)

44. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● The 8086 can be configured to work in either of two modes:
♦ The minimum mode is selected by applying logic 1 to the MN /MX input. It is
typically used for smaller single microprocessor systems.
♦ The maximum mode is selected by applying logic 0 to the MN /MX input. It
is typically used for larger multiprocessor systems.
● Depending on the mode of operation selected, the 8086 signals can be
categorized in three groups.
♦ The first are the signal having common functions in minimum as well as
maximum mode.
♦ The second are the signals which have special functions for minimum
mode.
♦ The third are the signals having special functions for maximum mode.

45. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA

46. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8
8086 Microprocessor
Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are
multiplexed with data.
When AD lines are used to transmit
memory address the symbol A is used
instead of AD, for example A0-A15.
When data are transmitted over AD lines
the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are
multiplexed with status signals

47. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
1. S3, S4 indicates the status flags that are used to select segment
registers.
2. S5- current setting of interrupt flag
3. S6 – status of the bus master and is always zero.
S3 S4 Register
0 0 ES
0 1 SS
1 0 CS
1 1 DS

48. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
9
8086 Microprocessor
Common signals
BHE (Active Low)/S7 (Output)
Bus High Enable/Status
Used to indicate transfer of data using
data bus. It is multiplexed with status
signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation.
It is an output signal.
It is active when low.

49. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
BHE S7
0 0 All 16 bits (word) will be accessed
0 1 Upper byte (AD15 – AD8) from odd address
1 0 Lower byte (AD7 – AD0) from even address
1 1 Idle state

50. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8086 Microprocessor
10
Common signals
TEST
𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’
instruction.
8086 will enter a wait state after execution of
the WAIT instruction and will resume
execution only when the 𝐓𝐄𝐒𝐓 is made low by
an active hardware.
This is used to synchronize an external activity
to the processor internal operation.
READY
This is the acknowledgement from the slow
device or memory that they have completed the
data transfer.
When this signal is low, 8086 enters wait state.
If its high it indicates that the device is ready to
transfer data.
This signal is used primarily to synchronize
slower peripherals with MP.

51. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8086 Microprocessor
11
Common signals
RESET (Input)
Causes the processor to immediately
terminate its present activity. Used to restart the
execution.
The signal must be active HIGH for at
least four clock cycles.
CLK
The clock input provides the basic timing for
processor operation and bus control activity. Its
an asymmetric square wave with 33% duty
cycle.
INTR Interrupt Request
This is sampled during the last clock cycles of
each instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the interrupt
acknowledge cycle.
This signal is active high and internally
synchronized

52. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8086 Microprocessor
Min/ Max Pins
13
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.
• In the minimum mode of operation the MP don’t
associate with any coprocessors and cannot be used
for multiprocessor systems.
• In maximum mode 8086 can work in multiprocessor
or coprocessor configuration.
• Maximum and Minimum modes are decided by the
pin MN/MX (Active low).
• When the pin is high 8086 operates in minimum
mode, otherwise it operates in maximum mode.

53. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8086 Microprocessor
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)
8086 itself generates all the bus control signals
D
T
/
𝐑
ഥ (Data Transmit/ Receive) To decide the direction of data flow.
1 - Transmit 0 - Receive
𝐃𝐄𝐍 (Data Enable) This signal informs the transceivers that the CPU
is ready to send or receive data.
ALE (Address Latch Enable) Used to demultiplex the
address and data lines using external latches
M/𝐈𝐎 Used to differentiate memory access and I/O access. For
memory reference instructions, it is high. For IN and OUT
instructions, it is low.
𝐖𝐑 Write control signal; asserted low Whenever
processor writes data to memory or I/O port
𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt request is accepted
by the processor, the output is low on this line.
14
Minimum mode signals

54. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8086 Microprocessor
HOLD Input signal to the processor form the bus masters as a request to
grant the control of the bus.
Usually used by the DMA controller to get the control of the
bus.
It indicates the processor that external devices are
requesting to access the address/data bus.
HLDA (Hold Acknowledge) Acknowledge signal by the processor to the
bus master requesting the control of the bus through HOLD.
The acknowledge is asserted high, when the
processor accepts HOLD.
Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)
8086 itself generates all the bus control signals
15

55. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)
Pins 24 -31 are reassigned
𝑺𝟎, 𝑺𝟏, 𝑺𝟐 Status signals; used by the 8086 bus controller to generate bus
timing and control signals. Indicate the type of transfer to take
place. These are decoded as shown.
Maximum mode signals
16

56. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)
Pins 24 -31 are reassigned
𝑸𝑺𝟎, 𝑸𝑺𝟏 (Queue Status) The processor provides the status of queue in
these lines.
The queue status can be used by external device to
track the internal status of the queue in 8086.
The output on QS0 and QS1 can be interpreted as
shown in the table.
Maximum mode signals
17

57. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Pins and Signals
8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)
Pins 24 -31 are reassigned
𝐑𝐐/𝐆𝐓𝟎,
𝐑𝐐/𝐆𝐓𝟏
(Bus Request/ Bus Grant) These requests are used by other local
bus masters to force the processor to release the local bus at the
end of the processor’s current bus cycle.
These pins are bidirectional.
The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏
𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix
instruction.
Remains active until the completion of the
instruction prefixed by LOCK.
The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while executing an instruction
prefixed by LOCK to prevent other bus masters from gaining control
of the system bus.
Maximum mode signals
18

58. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Physical Memory Organization

59. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Memory Banking
● 8086 has 20-bit address bus and 16-bit data bus.
● It can address 2 20 byte addressable memory locations i.e. 1MB
● Memory segmentation is related to logical organization
● Memory Banking is related to physical organization.
● If we have total memory 1MB in one chip, two memory read/write bus cycles are
required to access 16-bit data.
● Separating the memory into two equal banks is the solution.
● Total memory is 1MB = 1024KB = 512KB + 512KB
● Each bank of size 512KB
● A19 to A0 are address lines (20-bit address bus)
● We choose A0 to divide the memory into two parts.

60. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● A0 = 0 represent even address and A0 = 1 represent odd address
● Even bank/ lower bank is to store even addressed data
● Odd bank/ higher bank is to store odd addressed data
● To understand why banking is done let us assume 16 x 8 memory
● To represent these 16 locations you require 4 bits
● Each location holds 8-bit of data

61. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
16
X
8
Memory
0 - 0000
1 - 0001
2 - 0010
3 - 0011
4 - 0100
5 - 0101
6 - 0110
7 - 0111
8 - 1000
9 - 1001
10 - 1010
11 - 1011
12 - 1100
13 - 1101
14 - 1110
15 - 1111
Processor
16 – bit address
bus and data
bus
Consider it wants to access 16-bit
data from location 8
But only 8 bits are moving
Remaining 8-bits are moving
Each 8 bits when moved two times it requires 2
clock cycles and the data bus is not fully utilized
i.e. out of 16 lines only 8 lines are used.

62. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
16
X
8
Memory
0 - 0000
1 - 0001
2 - 0010
3 - 0011
4 - 0100
5 - 0101
6 - 0110
7 - 0111
8 - 1000
9 - 1001
10 - 1010
11 - 1011
12 - 1100
13 - 1101
14 - 1110
15 - 1111
To reduce that let us look into the solution i.e. divide
this 16 x 8 memory into 2 banks.
0 - 0000
2 - 0010
4 - 0100
6 - 0110
8 - 1000
10 - 1010
12 - 1100
14 - 1110
1 - 0001
3 - 0011
5 - 0101
7 - 0111
9 - 1001
11 - 1011
13 - 1101
15 - 1111
Even Bank Odd Bank
8 bytes 8 bytes
A3 A2 A1 A0 A3 A2 A1 A0

63. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Now apply the same concept for 8086 microprocessor 1MB memory
Even Bank
512KB
00000
.
.
.
FFFFE
Odd Bank
512KB
00001
.
.
.
FFFFF
8086 MP
A0 BHE

64. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● 8086 uses two signals to select the banks. A0 for Even Bank and BHE for
Odd Bank
● A19 – A1 are used to address memory banks
● A0 is used to select Even/ Lower Bank
● BHE is used to select Odd/ Higher Bank
● Common chip select signal is not used
● Because the processor doesn’t always need 16-bit data access.

65. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
FFFFE
FFFFC
.
.
.
00004
00002
00000
FFFFF
FFFFD
.
.
.
00005
00003
00001
A0
BHE
D7 – D0
A19 – A1
D15 – D8
Even Bank Odd Bank

66. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● A19 – A1 representing any address, that particular address will point out two
corresponding locations, one from odd and one from even.
● After locating the particular memory location, the data is loaded into data bus,
where the odd addressed data will be moved through D8 – D15 data lines
and even addressed data will be moved through the D0 – D7 data lines.
● Coming to pin diagram these address and data lines are multiplexed where
same lines are used for address and data with the division of time.
● With time sharing, lines hold the address as well as data.

67. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
S.No Operation BHE A0 Data Lines Used
1. Read / Write a byte from an even address 1 0 D7 – D0
2. Read / Write a byte from an odd address 0 1 D15 – D8
3. Read / Write a word from an even address 0 0 D15 – D0
4. None 1 1 -
5. Read / Write a word from an odd address
0 1 D15 – D8
1 0 D7 – D0

68. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Every MP based system has a memory system. Almost all systems contain two
basic types of memory. Read Only Memory (ROM) and Random Access Memory
(RAM).
● ROM contains system software and permanent data of system i.e. lookup tables
etc. while RAM contains temporary data and application software.
● ROMs/ PROMs/ EPROMs are mapped to cover the CPUs reset address, since
these are non volatile.
● When 8086 is reset, the next instruction is fetched from memory location FFFF0H.
So in 8086 systems, the location FFFF0H must be ROM location.
● Certain locations in 1Mbyte are reserved and some are dedicated to specific CPU
operations.

69. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
I/O Addressing Capacity

70. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA

71. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Memory mapped I/O and Isolated I/O
● As a processor needs to communicate with various memory and I/O devices
and we know that data between the processor and these devices flow with
the help of system bus.
● There are three ways in which the system bus can be allotted to them.
1. Separate set of address, control and data bus to I/O and memory
2. Have common bus for I/O and memory (data & address) but separate
control lines. - Isolated I/O
3. Have common bus (data, address and control) for I/O and memory –
Memory Mapped I/O

72. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA

73. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
I/O Addressing Capacity
● For memory operation and I/O operation the address bus is common i.e. for
memory access and I/O access the address bus is common.
● Total address lines are 20. While accessing the memory the entire 20 lines are
used.
● Whenever the processor wants to access I/O devices, it uses only 16 address
lines A0-A15 to specify I/O address.
● The remaining upper address lines (A16 – A19) are at logic 0 level during the I/O
operations.
● This means 8086 microprocessor can address up to 64kbyte I/O registers or 32K
word registers, i.e. 8086 generate 16-bit of I/O address.

74. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● The I/O address appears on the address lines A0 – A15 for one clock cycle
T1. It may then be latched using ALE signal.
● The upper address lines (A16 – A19) are at logic 0 level during the I/O
operations.
● The 16-bit register DX is used as 16-bit I/O address pointer with full capability
to address up to 64K devices.
● The I/O ports are addressed in the same manner as memory locations.
● Even addressed bytes are transferred on the D7-D0 data bus lines and odd
addressed bytes on D15 – D8.
● Intel has reserved 00F8 to 00FF locations.

75. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
8 bit I/O
address in
I/O
instruction
DIRECT
16 bit I/O
address in
register DX
INDIRECT
8 bit
DATA
AX 16bit
I/O space
64KB
Select
LOGIC
A0 – A7 & A8 – A15
A16 - A19 = 0
D0 – D7
D8 – D15
IORD
IOWD
Processor

76. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA

77. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
General 8086 System Bus Structure and Operation

78. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● The 8086 has a combined address and data bus commonly referred as a time
multiplexed address and data bus.
● The main reason behind multiplexing address and data over the same pins is
the maximum utilization of processor pins and it facilitates the use of 40 pin
standard DIP package.
● The bus can be demultiplexed using a few latches and transceivers, when
ever required.

79. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Basically, all the processor bus cycles consist of at least four clock cycles.
These are referred to as T1, T2, T3, and T4. The address is transmitted by
the processor during T1. It is present on the bus only for one cycle.
● The negative edge of this ALE pulse is used to separate the address and the
data or status information. In maximum mode, the status lines S0, S1 and S2
are used to indicate the type of operation.
● Status bits S3 to S7 are multiplexed with higher order address bits and the
BHE signal. Address is valid during T1 while status bits S3 to S7 are valid
during T2 through T4.

80. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA

81. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA

82. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Minimum Mode
Configuration

83. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.
● In minimum mode,8086 is the only processor in the system which provides all the
control signals which are needed for memory operations and I/O interfacing.
● Here the circuit is simple but it does not support multiprocessing.
● The other components which are transceivers, latches, 8284 clock generator,
74138 decoder, memory and i/o devices are also present in the system.
● The address bus of 8086 is 20 bits long. By this we can access 220 byte memory
i.e. 1MB . Out of 20 bits, 16 bits A0 to A15(or 16 lines) are multiplexed with a data
bus.
● By multiplexing, it means they will act as address lines during the first T state of
the machine cycle and in the rest, they act as data lines. A16 to A19 are multiplexed
S3 to S6 and BHE’ is multiplexed with S7.

84. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Control signals provided by 8086 for memory operations and i/o interfacing
● They are used to identifying whether the bus is carrying a valid address or
not.
● In which direction data is needed to be transferred over the bus, when there is
valid write data on the data bus and when to put read data on the system bus.
● Therefore, their sequence pattern makes all the operations successful in a
particular machine cycle.

85. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
8282 (8 bits) latch :
The latches are buffered. They are used to separate the valid address from the
multiplexed Address/data bus by using the control signal ALE, which is connected to
strobe(STB) of 8282. The ALE is active high signal. Here three such latches are required
because the address is 20 bits.
8286 (8 bits) transceivers :
They are bidirectional buffers and also known as data amplifiers. They are used to separate
the valid data from multiplexed add/data bus. Two such transceivers are needed
because the data bus is 16 bits long. 8286 is connected to DT/R’ and DEN’ signals. They are
enabled through the DEN signal .The direction of data on the data bus is controlled by the
DT/R’ signal. DT/R’ is connected to T and DEN’ is connected to OE’.

86. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● 8284 clock generator is used to provide the clock.
● M/IO’= 1,then I/O transfer is performed over the bus. and when M/IO’ = 0,
then I/O operation is performed.

87. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● The signals RD’ and write WR’ are used to identify whether a read bus cycle or a write bus cycle is
performing. When WR’ = 0 ,then it indicates that valid output data on the data bus.
● RD’ indicates that the 8086 is performing a read data or instruction fetch process is occurring .During
read operations, one other control signal is also used, which is DEN ( data enable) and it indicates the
external devices when they should put data on the bus.
● Control signals for all operations are generated by decoding M/IO’, RD’, WR’. They are decoded by
74138 3:8 decoder.

88. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
INTR and INTA :
● When INTR = 1,then there is an interrupt to 8086 by other devices for their
service. When INTA’= 0,then it indicates that the processor is ready to
service them.
● The bus request is made by other devices using the HOLD signal and the
processor acknowledges them using the HLDA output signal.

89. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Maximum Mode
Configuration

90. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Circuit explanation:
● When MN/ MX’ = 0 , 8086 works in max mode.
● Clock is provided by 8284 clock generator.
● 8288 bus controller- Address form the address bus is latched into 8282 8-bit
latch. Three such latches are required because address bus is 20 bit. The
ALE(Address latch enable) is connected to STB(Strobe) of the latch. The ALE
for latch is given by 8288 bus controller.
● The data bus is operated through 8286 8-bit transceiver. Two such transceivers
are required, because data bus is 16-bit. The transceivers are enabled the DEN
signal, while the direction of data is controlled by the DT/R signal. DEN is
connected to OE’ and DT/ R’ is connected to T. Both DEN and DT/ R’ are given
by 8288 bus controller.

91. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Control signals for all operations are generated by decoding S’2, S’1 and S’0 using 8288
bus controller.
DEN (of 8288) DT/R’ Action
0 X Transceiver is disabled
1 0 Receive data
1 1 Transmit data

92. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ0/GT0 has
more priority than RQ1/GT1.
● INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
● In max mode, the advanced write signals get enabled one T-state in advance
as compared to normal write signals. This gives slower devices more time to
get ready to accept the data, therefore it reduces the number of cycles.

93. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Basic Concepts in Memory Interfacing
Memory is an integral part of a microcomputer system. There are two main types
of memory.
(i) Read only memory (ROM): As the name indicates this memory is available
only for reading purpose. The various types available under this category are
PROM, EPROM, EEPROM which contain system software and permanent system
data.
(ii) Random Access memory (RAM): This is also known as Read Write Memory.
It is a volatile memory. RAM contains temporary data and software programs
generally for different applications.

94. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● While executing particular task it is necessary to access memory to get
instruction codes and data stored in memory.
● The microprocessor should be able to read from or write into the specified
register.
● The basic concepts of memory interfacing involve three different tasks such
as selection of the required chip, identify the required register and enable the
appropriate buffers.

95. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Schematic Representation
of Memory

96. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Memory device must contain address lines , Input, output lines, selection input and
control input to perform read or write operation.
● All memory devices have address inputs that select memory location within the memory
device. These lines are labeled as AO ...... AN.
● The number of address lines indicates the total memory capacity of the memory
device. A 1K memory requires 10 address lines A0-A9. Similarly a 1MB requires 20 lines A0-
A19 (in the case of 8086).
● The memory devices may have separate I/O lines or a common set of bidirectional I/O lines.
Using these lines data can be transferred in either direction.
● Whenever output buffer is activated, the data is read and whenever input buffers are
activated the data is written. These lines are labeled as I/O ... I/On or DO .............Dn.

97. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● The size of a memory location is dependent upon the number of data bits. If
the numbers of data lines are eight ,then 8 bits or 1 byte of data can be stored in
each location.
● Similarly if numbers of data bits are 16, then the memory size is 2 bytes.
● For example 2K x 8 indicates there are 2048 memory locations and each memory
location can store 8 bits of data.
● Memory devices may contain one or more inputs which are used to select
the memory device or to enable the memory device.
● This pin is denoted by CS (Chip select) or CE (Chip enable).
● When this pin is at logic '0' then only the memory device performs a read or a
write operation. If this pin is at logic ‘1’ the memory chip is disabled.

98. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
10 address lines 1K memory
11 address lines 2K memory
12 address lines 4K memory
13 address lines 8K memory
14 address lines 16K memory
15 address lines 32K memory
16 address lines 64K memory
17 address lines 128K memory
18 address lines 256K memory
19 address lines 512K memory
20 address lines 1M Byte memory

99. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● All memory devices will have one or more control inputs.
● When ROM is used , OE (output enable) pin allows data to flow out of the
output data pins. To perform this task both CS and OE must be active.
● A RAM contains one or two control inputs. They are R /W or RD and WR .
● If there is only one input R/W then it performs read operation when R/W pin
is at logic 1. If it is at logic 0 it performs write operation.

100. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
General Procedure of Memory Interfacing
● Arrange the available memory chips so as to obtain 16-bit data bus width. The
upper 8-bit bank is called odd address memory bank and lower 8-bit bank is called
even address memory bank.
● Connect available memory address lines of memory chips with those of the MP
and also connect memory RD and WR input/output to the corresponding
processor control signals.
● The remaining address lines of MP along with BHE, A0 used for decoding the
required chip select signals for the odd and even memory banks. CS is derived
from output of decoding circuit.

101. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
Problem: Interfacing two 4k x 8 RAM chips and two 4k x 8 EPROM chips with
8086 microprocessor.
Sol: Two ROM
Two RAM
● So to address these memory chips how many address lines of 8086 MP are
required, we can calculate by using the formula
Where ,
N = number of memory locations I memory chip
n= number of address lines
2n = N
4k x 8
4k x 8
4k x 8
4k x 8

102. Prepared by M.V.Bhuvaneswari, Asst.Prof, CSE, MVGRA
● Now we can calculate number of memory locations required
In total we have 8k for each memory chip
8k = 8192 locations
● We know that 8086 has 20 address lines (a0 – A19)
● Out of these 20 address lines only 13 are required to address the memory chip (A0 – A12).
● The remaining address lines (A13 – A19) are used to form the CS signal with BHE signal and A).
● Arrange the memory chips in such a way that we get a complete 16 bit data width.
● We can see that these chips can save 8bit data at each memory location. But we need 16bit data
width. Hence we arrange two EPROMs and two RAMs in parallel to each other such that upper and
lower bytes of data can be fetched consecutively.
 2n = 8k  2n = 213 n=13