This document discusses timers, the CCP module, ADC, and serial communication in PIC microcontrollers. It provides details on the different timer modules including Timer 0, Timer 1, and Timer 2, and describes their control and count registers. It also summarizes the functions of the CCP module, ADC module, and components used for serial communication like TXSTA, RCSTA, and related registers.
8051 timer counter
Introduction
TMOD Register
TCON Register
Modes of Operation
Counters
The microcontroller 8051 has two 16 bit Timer/ Counter registers namely Timer 0 (T0) and Timer 1 (T1) .
When used as a “Timer” the microcontroller is programmed to count the internal clock pulse.
When used as a “Counter” the microcontroller is programmed to count external pulses.
Maximum count rate is 1/24 of the oscillator frequency.
8051 timer counter
Introduction
TMOD Register
TCON Register
Modes of Operation
Counters
The microcontroller 8051 has two 16 bit Timer/ Counter registers namely Timer 0 (T0) and Timer 1 (T1) .
When used as a “Timer” the microcontroller is programmed to count the internal clock pulse.
When used as a “Counter” the microcontroller is programmed to count external pulses.
Maximum count rate is 1/24 of the oscillator frequency.
The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their main purpose is to measure time and count external events. Besides, they can be used for generating clock pulses to be used in serial communication, so called Baud Rate.
The presentation explain about the timers and associated registers in 8051
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The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their main purpose is to measure time and count external events. Besides, they can be used for generating clock pulses to be used in serial communication, so called Baud Rate.
The presentation explain about the timers and associated registers in 8051
Computer Science Training,IT Training,CS Training,Computer Training Institute,Technogroovy
like our page for more updates:
https://www.facebook.com/Technogroovyindia
With Best Regard's
Technogroovy Systems India Pvt. Ltd.
www.technogroovy.com
Call- +91-9582888121
Whatsapp- +91-8800718323
this ppt only for beginner who want to understand concept of Timer counter operation of LPC2148 step by step.
hope it may help u.
always welcoming ur suggestion.
It has four 32-bit Timer blocks
Each Timer block can be used as a ‘Timer’ (like for e.g. triggering an interrupt every ‘t’ microseconds) or as a ‘Counter’ and can be also used to demodulate PWM signals given as input.
Each Timer module has its own Timer Counter(TC) and Prescale Register(PR) associated with it.
When a Timer is Reset and Enabled, the TC is set to 0 and incremented by 1 every ‘PR+1’ clock cycles
It has four 32-bit Timer blocks
Each Timer block can be used as a ‘Timer’ (like for e.g. triggering an interrupt every ‘t’ microseconds) or as a ‘Counter’ and can be also used to demodulate PWM signals given as input.
Each Timer module has its own Timer Counter(TC) and Prescale Register(PR) associated with it.
When a Timer is Reset and Enabled, the TC is set to 0 and incremented by 1 every ‘PR+1’ clock cycles
Closed Circuit Television(CCTV) is the use of video cameras to transmit a signal to a specific place on a limited set of monitors.
CCTV comprises of camera, wires, monitoring screen, recorder.
It may employ point to point, point to multipoint or wireless links.
A rice cooker or rice steamer is an automated kitchen appliance designed to boil or steam rice.
It consists of a heat source, a cooking bowl, and a thermostat.
The thermostat measures the temperature of the cooking bowl and controls the heat.
An environmental control system that cooling and dehumidification will require a means of removing heat from the conditioned spaces.
A refrigeration system extracts heat from a substance at a temperature lower than the ambient and transfers the extracted heat to the atmosphere at a temperature higher than the ambient
Supervisor call and pendable service callPriyangaKR1
Generates system function calls.
When a user program wants to use certain hardware, it generates the SVC exception using SVC instructions
The software exception handler in the operating system is executed and provides the service the user application requested
SVC can also make software more portable because the user application does not need to know the programming details of the hardware
W . R . Evans – 1948
Analysis of Control Systems
To achieve desired system performances
Open Loop Transfer Function
K = 0 The roots are given by open loop poles
K= ∞ The roots are given by open loop zeros
The path taken 0 to ∞ is called ROOT LOCUS or ROOT LOCI
Batch Operating Systems
Time Sharing Operating Systems
Distributed Operating Systems
Network Operating Systems
Real Time Operating Systems
Hard real time
Soft real time
Tasks:
It consists of a sequentially executable program and a state
Task status, Task Structure and Task Control Block
Tasks States:
Idle
Ready
Running
Blocked
Instruction sets picc done by Priyanga KRPriyangaKR1
Complete set: 35 instructions.
MC Architecture: RISC microcontroller.
Instruction Types:
1. Data Processing Operations:
– Copy data between registers.
– Manipulate data in a single register.
2. Arithmetic and Logic operations:
3. Bit Operation:
4. Program Sequence Control Operations:
– Unconditional Jump.
– Conditional Jump.
– Call.
– Control.
RAM,
flash memory,
Timers/Counters,
EEPROM,
I/O Ports,
USART,
CCP (Capture/Compare/PWM module),
Comparator,
ADC (analog to digital converter),
LCD and
ICSP (in circuit serial programming)
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
Timers done by Priyanga KR
1. Timers, CCP Module, ADC
and Serial Communication
Done by,
Ms.K.R.Priyanga
Assistant Professor,
Department of ECE,
Avinashilingam Institute
2. • To measure the time or generate the accurate
time delay
• To count clock pulses(Internal/External)
TIMERS
3. Different Timers
• PIC Timer 0
• PIC Timer 1
• PIC Timer 2
Timer Size
Control
Register
Count
Register
Min Delay Max Delay
TIMER0 8-bit
OPTION_RE
G
TMR0 0.2usec 13.107ms
TIMER1 16-bit T1CON
TMR1H,TMR
1L
0.2usec 104.857ms
TIMER2 8-bit T2CON TMR2 0.2usec 819usec
4. Timer 0
• OPTION_REG - configure the TIMER0
Prescalar, Clock Source
• TMR0 - holds the timer count value which will
be incremented depending on prescalar
configuration
• INTCON - contains the Timer0 overflow
flag(TMR0IF) and corresponding Inetrrupt
Enable flag(TMR0IE).
5. Option_ Register
RBPU: PORT B Pull up enable Bit
1 - Disabled
0 - connected to pull-resistors
INTEDG: Interrupt Edge Select Bit
1 – Interrupt on rising edge of the INT pin (0-1)
0 - Interrupt on falling edge of the INT pin (1-0)
T0CS: TMR0 Clock Source Select bit
1-Transition on T0CKI pin
0-Internal instruction cycle clock (CLKO)
T0SE: TMR0 Source Edge Select bit
1-Increment on high-to-low transition on T0CKI pin
0-Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1-Prescaler is assigned to the WDT
0-Prescaler is assigned to the Timer0
PS2:PS0: Prescaler Rate Select bits
6.
7. Timer 1
• T1CON: Configure the TIMER1 Prescalar, Clock
Source
• TMRIH: Holds the higher 8-bits of timer value
• TMRIL: Holds the lower 8-bits of timer value
• PIR1: Contains the Timer1 overflow
flag(TMR1IF)
• PIE1: Contains the Timer1 Interrupt Enable
flag(TMR1IE)
8. T1CON
• T1CKPS1:T1CKPS0:Timer1 Input Clock Prescale Select bits
11 = 1:8 prescale value
10 = 1:4 prescale value
01 = 1:2 prescale value
00 = 1:1 prescale value
• T1OSCEN: Timer1 Oscillator Enable Control bit
1-Oscillator is enabled
0-Oscillator is shut-off
• T1SYNC: Timer1 External Clock Input Synchronization Control bit
1-Do not synchronize external clock input
0-Synchronize external clock input
• TMR1CS: Timer1 Clock Source Select bit
1-External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0-Internal clock (FOSC/4)
• TMR1ON: Timer1 On bit
1-Enables Timer1
0-Stops Timer1
9. Timer 2
• T2CON: Configure the TIMER2 Prescalar, Clock
Source
• TMR2: holds the timer count value which will
be incremented depending on prescalar
configuration
• PIR1: contains the Timer2 overflow
flag(TMR2IF)
• PIE1: contains the Timer2 Interrupt Enable
flag(TMR2IE)
10. T2CON
• TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 postscale
0001 = 1:2 postscale
0010 = 1:3 postscale
•
•
•
1111 = 1:16 postscale
• TMR2ON: Timer2 On bit
1-Timer2 is on
0-Timer2 is off
• T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
12. ADC
• 8 input ADC pins
• 10 bit digital number
• Registers
• ADCON0 – ADC Control Register 0
• ADCON1 – ADC Control Register 1
• ADRESH – ADC result High Register
• ADRESL – ADC result Low Register
13. Serial Communication
• TXSTA: Transmit status and control register
• RCSTA: Receive status and control register
• SPBRG: USART Baud rate generator
• TXREG: USART Transmit register.(transmitted
on UART)
• RCREG: USART Transmit register.(received
from UART)
14. TXSTA – 8 bits
• CSRC: Clock Source select bit
• TX9: 9-bit transmit enable bit
• TXEN: transmit enable bit (1-enabled; 0-disabled)
• SYNC: USART Mode select bit (1 – Syn; 0 - ASyn)
• BRGH: High Baud rate select bit (1- high speed; 0-low speed)
• TRMT: Transmit shift register status bit
• TX9D: 9th bit transmit data
15. RCSTA – 8 bits
• SPEN: Serial port enable bit (1-enable; 0-disable)
• RX9: 9 bit Receive Enable Bit
• SREN: Single receive enable bit
• CREN: Continuous receive enable bit
• ADDEN: Address detect enable bit
• FERR: Framing error bit
• OERR: Overrun error bit
• RX9D: 9th bit of received data
