SlideShare a Scribd company logo
?
A semantic model for VHDL-AMS
Natividad Mart´ınez Madrid, Peter T. Breuer, Carlos Delgado Kloos
Universidad Carlos III de Madrid
<nmadrid,ptb,cdk>@it.uc3m.es
CHARME ’97, Montr´eal, Canada - October 1997 1
Objectives ?
• explain behaviour of VHDL-AMS processes
– not a detailed syntactic mapping
– provide sufficient primitives
• present an underlying model that . . .
– extends existing model for VHDL
CHARME ’97, Montr´eal, Canada - October 1997 2
Content of the talk ?
• Introduction
• A process algebraic analysis
• Semantics
• The analog solver with example
CHARME ’97, Montr´eal, Canada - October 1997 3
Main idea ?
VHDL semantics analog extension
imperative
discrete-event
diff. equations
real time domain
declarative
continuous-time
ց ւ
INTEGRATION
CHARME ’97, Montr´eal, Canada - October 1997 4
Name space division & Properties ?
VARIABLES assigned
instantaneously
not scheduled
SIGNALS at least δ-delayed preemptively
scheduled
QUANTITIES assigned
instantaneously
governed by diff. eqns.
PROCESSES invariant invariant
CHARME ’97, Montr´eal, Canada - October 1997 5
Semantics of assignment ?
00
00
00
0
0000000000000000000000000
11
11
11
1
1111111111111111111111111
0000000000000000000000000
0000000000000000000000000
0000000000000000000000000
00000000000000000000000000000000000000000000000000
1111111111111111111111111
1111111111111111111111111
1111111111111111111111111
11111111111111111111111111111111111111111111111111
000000000000000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000
0000000000000000000000000
111111111111111111111111111111111111111111111111111111111111111111111111111
1111111111111111111111111
1111111111111111111111111
00000000000000000000000000
0000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000
11111111111111111111111111
1111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111
00000111110011 "Forced" signal assignment
a <= 1 after 4
00000000000000000000
00000000000000000000
00000000000000000000
11111111111111111111
11111111111111111111
11111111111111111111
a
000000000000000000000000000000000000000000000000000000000000000000000000000000
111111111111111111111111111111111111111111111111111111111111111111111111111111
.
v =
x
.
00000111110011 "Relaxed" quantity update
0
00
000
0000
1
11
111
1111
0
00
000
0000
1
11
111
1111
000
111
000
111000000000000000000000000000000000000000000000000000000000000000000000000000000
111111111111111111111111111111111111111111111111111111111111111111111111111111x
a
= v
CHARME ’97, Montr´eal, Canada - October 1997 6
Semantic Domains ?
WorldLine = Time → State
State = Id → V alue
VHDL Statements
Semantics = (WorldLine, Time) ↔ (WorldLine, Time)
Time = Int
VHDL-AMS Statements
Semantics = (EqnSet, WorldLine, Time) ↔ (EqnSet, WorldLine, Time)
Time = Real
CHARME ’97, Montr´eal, Canada - October 1997 7
Parallel decomposition ?
LRM view of basic VHDL compositionality:
• processes in parallel (+ kernel)
• process body loops continuously
• imperative commands in process body run sequentially
Our view:
• no kernel
CHARME ’97, Montr´eal, Canada - October 1997 8
VHDL-AMS: integer time → real time
Analog Solver
Process algebraic analysis ?
000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000
111111111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111
00000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
11111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
Ai
Aj
Σj
Σi
Σj
Pj’
Pi’
Pi
Pj
Ki
Kj
Σi
00000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000
11111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111
000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111
AS
Ai
Aj
Σj
Σi
Σj
Pj’
Pi’
Pj
Ki
Kj
Σi
Pi
CHARME ’97, Montr´eal, Canada - October 1997 9
Process algebraic analysis (II) ?
000000000000000000000000000000000000000
000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000
000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000
111111111111111111111111111111111111111
111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111
111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111
000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000
000000000000000000000000000000000000000
111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111
111111111111111111111111111111111111111
00000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
00000000000000000000
000000000000000000000000000000000000000000000000000000000000
11111111111111111111
1111111111111111111111111111111111111111
1111111111111111111111111111111111111111
1111111111111111111111111111111111111111
11111111111111111111
111111111111111111111111111111111111111111111111111111111111
00000000000000000000
00000000000000000000
000000000000000000000000000000000000000000000000000000000000
00000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
0000000000000000000000000000000000000000
11111111111111111111
11111111111111111111
111111111111111111111111111111111111111111111111111111111111
11111111111111111111
1111111111111111111111111111111111111111
1111111111111111111111111111111111111111
1111111111111111111111111111111111111111
iΣ
Σj
’iΣ
’jΣ
K’i
Σ
Σ
Q
AS
Q
AS
KAj
KAi
Pi
Pj
Ai
Aj K’j
Pj’
Pi’
CHARME ’97, Montr´eal, Canada - October 1997 10
Denotational semantics ?
S[a; b] = S[a]; S[b]
P[a; b] = P[a] ∪ S[a]; P[b]
S[while(true)do a end] = { }
P[while(true)do a end] = P[a] ∪ S[a]; P[while(true)do a end]
= µR : Semantics . R = P[a] ∪ S[a]; R
S[a||b] = S[a] ∩ S[b]
P[a||b] = P[a] ∩ P[b]
CHARME ’97, Montr´eal, Canada - October 1997 11
Wait & Assignment semantics ?
Wait Semantics
(e, w0, t0)S[wait until p](e, w1, t1) = w0 = w1
∧ wt1 |= p ∧ ∀t ∈ [t0, t1) . wt |= p
(e, w0, t0)P[wait until p](e, w1, t1) = w0 = w1
∧ ∀t ∈ [t0, t1] . wt |= p
Assignment Semantics
(e, w0, t0)S[x ⇐ y after τ](e, w1, t1) = t0 = t1
∧ w1 = relax(e, t0)(force assign(w0))
P[x ⇐ y after τ] = { }
CHARME ’97, Montr´eal, Canada - October 1997 12
Wait semantics ?
0
00
00
0
000
0
00
1
11
11
1
111
1
11
00000000000000000000
0000000000000000000000000000000000000000
11111111111111111111
1111111111111111111111111111111111111111
Generalized Wait
a
x
wait until a = 1
on signals -> discrete time
00000000000000000000
0000000000000000000000000000000000000000
11111111111111111111
1111111111111111111111111111111111111111
00
0
0
000
0
000
0
11
1
1
111
1
111
1
00000000000000000000
00000000000000000000
00000000000000000000
11111111111111111111
11111111111111111111
11111111111111111111
0
0
00
0
0
000
0
00
1
1
11
1
1
111
1
11
wait until x >= 2/3
on quantities -> continuous time
CHARME ’97, Montr´eal, Canada - October 1997 13
Sequential composition ?
;
000000000000111111111111
000000000000
0000
0000
00000000
00000000
00000000
00000000
0000
000000000000
0000
000000000000
0000
000000000000
0000
0000
111111111111
1111
1111
11111111
11111111
11111111
11111111
1111
111111111111
1111
111111111111
1111
111111111111
1111
1111
a
x
000000
000
000
000000000
000
000000
000000
000
000000000
000
000000000
000
000
111111
111
111
111111111
111
111111
111111
111
111111111
111
111111111
111
111
00000000000001111111111111
0000
00
00
000000
00
0000
0000
00
000000
00
000000
00
00
1111
11
11
111111
11
1111
1111
11
111111
11
111111
11
11
000000000000111111111111
000000000000111111111111
000000000000
0000
0000
00000000
00000000
00000000
00000000
0000
000000000000
0000
000000000000
0000
000000000000
0000
0000
111111111111
1111
1111
11111111
11111111
11111111
11111111
1111
111111111111
1111
111111111111
1111
111111111111
1111
1111
a
x
000000
000
000
000000000
000
000000
000000
000
000000000
000
000000000
000
000
111111
111
111
111111111
111
111111
111111
111
111111111
111
111111111
111
111
00000000000001111111111111
0000
00
00
000000
00
0000
0000
00
000000
00
000000
00
00
1111
11
11
111111
11
1111
1111
11
111111
11
111111
11
11
000000000000111111111111
000000000000111111111111
000000000000
0000
0000
00000000
00000000
00000000
00000000
0000
000000000000
0000
000000000000
0000
000000000000
0000
0000
111111111111
1111
1111
11111111
11111111
11111111
11111111
1111
111111111111
1111
111111111111
1111
111111111111
1111
1111
a
x
000000
000
000
000000000
000
000000
000000
000
000000000
000
000000000
000
000
111111
111
111
111111111
111
111111
111111
111
111111111
111
111111111
111
111
00000000000001111111111111
0000
00
00
000000
00
0000
0000
00
000000
00
000000
00
00
1111
11
11
111111
11
1111
1111
11
111111
11
111111
11
11
000000000000111111111111
.
v =
x
. a
= v
wait until x >= 2/3wait until x >= 2/3wait until x >= 2/3a <= 1 after 4
CHARME ’97, Montr´eal, Canada - October 1997 14
Analog solution ?
Bouncing ball example
ds
dt = v
dv
dt = −g ± av2
Local approximation s(t) = 1
v(t) = −gt
origin at
s = 1
v = 0
t = 0
Linear approximation (s, v) = (s0, v0) + (t − t0)(v0, −g ± av2
0)
Recursion
(s, v)(t0,s0,v0)(t) ∼



(s0, v0) + (t − t0)(v0, −g ± av2
0) t ∈ [t0, t1)
(s, v)(t1,s1,v1)(t)
s1 = s0 + v0∆t
v1 = v0 + (−g ± av2
0)∆t
t1 = t0 + ∆t
CHARME ’97, Montr´eal, Canada - October 1997 15
Example ?
proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ]
ds/dt == v;
dv/dt == -g + if v<0 then a else -a end * v * v;
begin
wait until s < 0;
v := -v;
s := 0 ;
end
∆t = 0.02
CHARME ’97, Montr´eal, Canada - October 1997 16
Example Cont. ?
proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ]
ds/dt == v;
dv/dt == -g + if v<0 then a else -a end * v * v;
begin
wait until s < 0;
v := 1.4142 * (g * s + 0.5 * v * v)**0.5 ;
s := 0 ;
end
g ∗ 0 + v′2
2 =
g ∗ s + v2
2
∆t = 0.06
CHARME ’97, Montr´eal, Canada - October 1997 17
Example Cont. (II) ?
Height
Speed
∆t = 0.06
CHARME ’97, Montr´eal, Canada - October 1997 18
Unresolved areas ?
• Implementation of the parallel composition of pro-
cesses if quantities are shared between processes
• Errors in the analog solver may require us to rewrite
our program
• The proper execution of the analog solver in δ time
when the processes are in parallel
CHARME ’97, Montr´eal, Canada - October 1997 19
Conclusion ?
• What? Extension of our VHDL semantics to cover
VHDL-AMS
• How? Embedding of the VHDL semantics in a bigger,
continuous time domain, which contains an oracular
analog solver
• Why? Clarify the draft standard document
CHARME ’97, Montr´eal, Canada - October 1997 20

More Related Content

What's hot

qlp
qlpqlp
CRDTs and Redis
CRDTs and RedisCRDTs and Redis
CRDTs and Redis
Carlos Baquero
 
Shor’s algorithm the ppt
Shor’s algorithm the pptShor’s algorithm the ppt
Shor’s algorithm the ppt
Mrinal Mondal
 
MMath Paper, Canlin Zhang
MMath Paper, Canlin ZhangMMath Paper, Canlin Zhang
MMath Paper, Canlin Zhangcanlin zhang
 
no U-turn sampler, a discussion of Hoffman & Gelman NUTS algorithm
no U-turn sampler, a discussion of Hoffman & Gelman NUTS algorithmno U-turn sampler, a discussion of Hoffman & Gelman NUTS algorithm
no U-turn sampler, a discussion of Hoffman & Gelman NUTS algorithm
Christian Robert
 
Resource theory of asymmetric distinguishability
Resource theory of asymmetric distinguishabilityResource theory of asymmetric distinguishability
Resource theory of asymmetric distinguishability
Mark Wilde
 

What's hot (7)

qlp
qlpqlp
qlp
 
CRDTs and Redis
CRDTs and RedisCRDTs and Redis
CRDTs and Redis
 
Shor’s algorithm the ppt
Shor’s algorithm the pptShor’s algorithm the ppt
Shor’s algorithm the ppt
 
MMath Paper, Canlin Zhang
MMath Paper, Canlin ZhangMMath Paper, Canlin Zhang
MMath Paper, Canlin Zhang
 
no U-turn sampler, a discussion of Hoffman & Gelman NUTS algorithm
no U-turn sampler, a discussion of Hoffman & Gelman NUTS algorithmno U-turn sampler, a discussion of Hoffman & Gelman NUTS algorithm
no U-turn sampler, a discussion of Hoffman & Gelman NUTS algorithm
 
Chapter04
Chapter04Chapter04
Chapter04
 
Resource theory of asymmetric distinguishability
Resource theory of asymmetric distinguishabilityResource theory of asymmetric distinguishability
Resource theory of asymmetric distinguishability
 

Viewers also liked

Ddhdl 15
Ddhdl 15Ddhdl 15
Ddhdl 15
Akhil Maddineni
 
Vhdl introduction
Vhdl introductionVhdl introduction
Vhdl introduction
Dhaval Shukla
 
Introduction to Pandas
Introduction to PandasIntroduction to Pandas
Introduction to Pandas
Jason Myers
 
Introduction to VHDL
Introduction to VHDLIntroduction to VHDL
Introduction to VHDL
Mohamed Samy
 
Modeling Style and Delay Model of VHDL By Ap
Modeling Style and Delay Model of VHDL By ApModeling Style and Delay Model of VHDL By Ap
Modeling Style and Delay Model of VHDL By Ap
Er. Ashish Pandey
 
Vlsi_vhdl and pcb designing ppt
Vlsi_vhdl and pcb designing pptVlsi_vhdl and pcb designing ppt
Vlsi_vhdl and pcb designing ppt
Pallavi Bharti
 
VHDL
VHDLVHDL
How to design Programs using VHDL
How to design Programs using VHDLHow to design Programs using VHDL
How to design Programs using VHDL
Eutectics
 
Synthesis
SynthesisSynthesis
Synthesis
Mantra VLSI
 
Combinational Circuits & Sequential Circuits
Combinational Circuits & Sequential CircuitsCombinational Circuits & Sequential Circuits
Combinational Circuits & Sequential Circuits
gourav kottawar
 
Basic structures in vhdl
Basic structures in vhdlBasic structures in vhdl
Basic structures in vhdlRaj Mohan
 
Introduction to FPGA, VHDL
Introduction to FPGA, VHDL  Introduction to FPGA, VHDL
Introduction to FPGA, VHDL
Amr Rashed
 
Sequential circuits in digital logic design
Sequential circuits in digital logic designSequential circuits in digital logic design
Sequential circuits in digital logic design
Nallapati Anindra
 
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGNSEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
QAU ISLAMABAD,PAKISTAN
 
Digital 1 8
Digital 1 8Digital 1 8
Digital 1 8
Sayan Chakraborty
 
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Rahul Borthakur
 
STLD-Combinational logic design
STLD-Combinational  logic design STLD-Combinational  logic design
STLD-Combinational logic design
Abhinay Potlabathini
 

Viewers also liked (20)

Ddhdl 15
Ddhdl 15Ddhdl 15
Ddhdl 15
 
Data Flow Modeling
Data Flow ModelingData Flow Modeling
Data Flow Modeling
 
Vhdl introduction
Vhdl introductionVhdl introduction
Vhdl introduction
 
Introduction to Pandas
Introduction to PandasIntroduction to Pandas
Introduction to Pandas
 
Introduction to VHDL
Introduction to VHDLIntroduction to VHDL
Introduction to VHDL
 
Modeling Style and Delay Model of VHDL By Ap
Modeling Style and Delay Model of VHDL By ApModeling Style and Delay Model of VHDL By Ap
Modeling Style and Delay Model of VHDL By Ap
 
Vlsi_vhdl and pcb designing ppt
Vlsi_vhdl and pcb designing pptVlsi_vhdl and pcb designing ppt
Vlsi_vhdl and pcb designing ppt
 
VHDL
VHDLVHDL
VHDL
 
How to design Programs using VHDL
How to design Programs using VHDLHow to design Programs using VHDL
How to design Programs using VHDL
 
Synthesis
SynthesisSynthesis
Synthesis
 
Combinational Circuits & Sequential Circuits
Combinational Circuits & Sequential CircuitsCombinational Circuits & Sequential Circuits
Combinational Circuits & Sequential Circuits
 
Basic structures in vhdl
Basic structures in vhdlBasic structures in vhdl
Basic structures in vhdl
 
Introduction to FPGA, VHDL
Introduction to FPGA, VHDL  Introduction to FPGA, VHDL
Introduction to FPGA, VHDL
 
Sequential circuits in digital logic design
Sequential circuits in digital logic designSequential circuits in digital logic design
Sequential circuits in digital logic design
 
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGNSEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
 
Digital 1 8
Digital 1 8Digital 1 8
Digital 1 8
 
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
 
Pcb designing
Pcb designingPcb designing
Pcb designing
 
STLD-Combinational logic design
STLD-Combinational  logic design STLD-Combinational  logic design
STLD-Combinational logic design
 
Chap 2 behaviour models
Chap 2 behaviour modelsChap 2 behaviour models
Chap 2 behaviour models
 

Similar to A Semantic Model for VHDL-AMS (CHARME '97)

A Semantic Model For VHDL-AMS
A Semantic Model For VHDL-AMSA Semantic Model For VHDL-AMS
A Semantic Model For VHDL-AMS
Lisa Riley
 
Tutorial: Formal Methods for Hardware Verification - Overview and Application...
Tutorial: Formal Methods for Hardware Verification - Overview and Application...Tutorial: Formal Methods for Hardware Verification - Overview and Application...
Tutorial: Formal Methods for Hardware Verification - Overview and Application...
Peter Breuer
 
myppt for health issues at IITB. Don't come to IITB
myppt for health issues at IITB. Don't come to IITBmyppt for health issues at IITB. Don't come to IITB
myppt for health issues at IITB. Don't come to IITB
dhvaniliitb
 
Time Series Processing with Solr and Spark: Presented by Josef Adersberger, Q...
Time Series Processing with Solr and Spark: Presented by Josef Adersberger, Q...Time Series Processing with Solr and Spark: Presented by Josef Adersberger, Q...
Time Series Processing with Solr and Spark: Presented by Josef Adersberger, Q...
Lucidworks
 
Time Series Processing with Solr and Spark
Time Series Processing with Solr and SparkTime Series Processing with Solr and Spark
Time Series Processing with Solr and Spark
Josef Adersberger
 
Time Series Analysis
Time Series AnalysisTime Series Analysis
Time Series Analysis
QAware GmbH
 
lecture-4-location-models-2.pdf
lecture-4-location-models-2.pdflecture-4-location-models-2.pdf
lecture-4-location-models-2.pdf
KIRANEC2
 
Data streaming algorithms
Data streaming algorithmsData streaming algorithms
Data streaming algorithms
Sandeep Joshi
 
ANN ARIMA Hybrid Models for Time Series Prediction
ANN ARIMA Hybrid Models for Time Series PredictionANN ARIMA Hybrid Models for Time Series Prediction
ANN ARIMA Hybrid Models for Time Series Prediction
M Baddar
 
Searching Informed Search.pdf
Searching Informed Search.pdfSearching Informed Search.pdf
Searching Informed Search.pdf
DrBashirMSaad
 
recursion.ppt
recursion.pptrecursion.ppt
recursion.ppt
gilvalerio
 
Module_2_rks in Artificial intelligence in Expert System
Module_2_rks in Artificial intelligence in Expert SystemModule_2_rks in Artificial intelligence in Expert System
Module_2_rks in Artificial intelligence in Expert System
NareshKireedula
 
Algorithm analysis.pptx
Algorithm analysis.pptxAlgorithm analysis.pptx
Algorithm analysis.pptx
DrBashirMSaad
 
Data Vault 2.0: Using MD5 Hashes for Change Data Capture
Data Vault 2.0: Using MD5 Hashes for Change Data CaptureData Vault 2.0: Using MD5 Hashes for Change Data Capture
Data Vault 2.0: Using MD5 Hashes for Change Data Capture
Kent Graziano
 
Cfd 0
Cfd 0Cfd 0
Fast Single-pass K-means Clusterting at Oxford
Fast Single-pass K-means Clusterting at Oxford Fast Single-pass K-means Clusterting at Oxford
Fast Single-pass K-means Clusterting at Oxford
MapR Technologies
 
The new time series kid on the block
The new time series kid on the blockThe new time series kid on the block
The new time series kid on the block
Florian Lautenschlager
 
Chronix Time Series Database - The New Time Series Kid on the Block
Chronix Time Series Database - The New Time Series Kid on the BlockChronix Time Series Database - The New Time Series Kid on the Block
Chronix Time Series Database - The New Time Series Kid on the Block
QAware GmbH
 
Optimal real-time landing using DNN
Optimal real-time landing using DNNOptimal real-time landing using DNN
Optimal real-time landing using DNN
홍배 김
 
RedisConf18 - CRDTs and Redis - From sequential to concurrent executions
RedisConf18 - CRDTs and Redis - From sequential to concurrent executionsRedisConf18 - CRDTs and Redis - From sequential to concurrent executions
RedisConf18 - CRDTs and Redis - From sequential to concurrent executions
Redis Labs
 

Similar to A Semantic Model for VHDL-AMS (CHARME '97) (20)

A Semantic Model For VHDL-AMS
A Semantic Model For VHDL-AMSA Semantic Model For VHDL-AMS
A Semantic Model For VHDL-AMS
 
Tutorial: Formal Methods for Hardware Verification - Overview and Application...
Tutorial: Formal Methods for Hardware Verification - Overview and Application...Tutorial: Formal Methods for Hardware Verification - Overview and Application...
Tutorial: Formal Methods for Hardware Verification - Overview and Application...
 
myppt for health issues at IITB. Don't come to IITB
myppt for health issues at IITB. Don't come to IITBmyppt for health issues at IITB. Don't come to IITB
myppt for health issues at IITB. Don't come to IITB
 
Time Series Processing with Solr and Spark: Presented by Josef Adersberger, Q...
Time Series Processing with Solr and Spark: Presented by Josef Adersberger, Q...Time Series Processing with Solr and Spark: Presented by Josef Adersberger, Q...
Time Series Processing with Solr and Spark: Presented by Josef Adersberger, Q...
 
Time Series Processing with Solr and Spark
Time Series Processing with Solr and SparkTime Series Processing with Solr and Spark
Time Series Processing with Solr and Spark
 
Time Series Analysis
Time Series AnalysisTime Series Analysis
Time Series Analysis
 
lecture-4-location-models-2.pdf
lecture-4-location-models-2.pdflecture-4-location-models-2.pdf
lecture-4-location-models-2.pdf
 
Data streaming algorithms
Data streaming algorithmsData streaming algorithms
Data streaming algorithms
 
ANN ARIMA Hybrid Models for Time Series Prediction
ANN ARIMA Hybrid Models for Time Series PredictionANN ARIMA Hybrid Models for Time Series Prediction
ANN ARIMA Hybrid Models for Time Series Prediction
 
Searching Informed Search.pdf
Searching Informed Search.pdfSearching Informed Search.pdf
Searching Informed Search.pdf
 
recursion.ppt
recursion.pptrecursion.ppt
recursion.ppt
 
Module_2_rks in Artificial intelligence in Expert System
Module_2_rks in Artificial intelligence in Expert SystemModule_2_rks in Artificial intelligence in Expert System
Module_2_rks in Artificial intelligence in Expert System
 
Algorithm analysis.pptx
Algorithm analysis.pptxAlgorithm analysis.pptx
Algorithm analysis.pptx
 
Data Vault 2.0: Using MD5 Hashes for Change Data Capture
Data Vault 2.0: Using MD5 Hashes for Change Data CaptureData Vault 2.0: Using MD5 Hashes for Change Data Capture
Data Vault 2.0: Using MD5 Hashes for Change Data Capture
 
Cfd 0
Cfd 0Cfd 0
Cfd 0
 
Fast Single-pass K-means Clusterting at Oxford
Fast Single-pass K-means Clusterting at Oxford Fast Single-pass K-means Clusterting at Oxford
Fast Single-pass K-means Clusterting at Oxford
 
The new time series kid on the block
The new time series kid on the blockThe new time series kid on the block
The new time series kid on the block
 
Chronix Time Series Database - The New Time Series Kid on the Block
Chronix Time Series Database - The New Time Series Kid on the BlockChronix Time Series Database - The New Time Series Kid on the Block
Chronix Time Series Database - The New Time Series Kid on the Block
 
Optimal real-time landing using DNN
Optimal real-time landing using DNNOptimal real-time landing using DNN
Optimal real-time landing using DNN
 
RedisConf18 - CRDTs and Redis - From sequential to concurrent executions
RedisConf18 - CRDTs and Redis - From sequential to concurrent executionsRedisConf18 - CRDTs and Redis - From sequential to concurrent executions
RedisConf18 - CRDTs and Redis - From sequential to concurrent executions
 

More from Peter Breuer

Avoiding Hardware Aliasing
Avoiding Hardware AliasingAvoiding Hardware Aliasing
Avoiding Hardware Aliasing
Peter Breuer
 
Empirical Patterns in Google Scholar Citation Counts (CyberPatterns 2014)
Empirical Patterns in Google Scholar Citation Counts (CyberPatterns 2014)Empirical Patterns in Google Scholar Citation Counts (CyberPatterns 2014)
Empirical Patterns in Google Scholar Citation Counts (CyberPatterns 2014)
Peter Breuer
 
Certifying (RISC) Machine Code Safe from Aliasing (OpenCert 2013)
Certifying (RISC) Machine Code Safe from Aliasing  (OpenCert 2013)Certifying (RISC) Machine Code Safe from Aliasing  (OpenCert 2013)
Certifying (RISC) Machine Code Safe from Aliasing (OpenCert 2013)
Peter Breuer
 
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
Peter Breuer
 
Higher Order Applicative XML (Monterey 2002)
Higher Order Applicative XML (Monterey 2002)Higher Order Applicative XML (Monterey 2002)
Higher Order Applicative XML (Monterey 2002)
Peter Breuer
 
Raiding the Noosphere
Raiding the NoosphereRaiding the Noosphere
Raiding the Noosphere
Peter Breuer
 
Abstract Interpretation meets model checking near the 1000000 LOC mark: Findi...
Abstract Interpretation meets model checking near the 1000000 LOC mark: Findi...Abstract Interpretation meets model checking near the 1000000 LOC mark: Findi...
Abstract Interpretation meets model checking near the 1000000 LOC mark: Findi...
Peter Breuer
 
Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux ...
Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux ...Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux ...
Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux ...
Peter Breuer
 
Open Source Verification under a Cloud (OpenCert 2010)
Open Source Verification under a Cloud (OpenCert 2010)Open Source Verification under a Cloud (OpenCert 2010)
Open Source Verification under a Cloud (OpenCert 2010)
Peter Breuer
 

More from Peter Breuer (9)

Avoiding Hardware Aliasing
Avoiding Hardware AliasingAvoiding Hardware Aliasing
Avoiding Hardware Aliasing
 
Empirical Patterns in Google Scholar Citation Counts (CyberPatterns 2014)
Empirical Patterns in Google Scholar Citation Counts (CyberPatterns 2014)Empirical Patterns in Google Scholar Citation Counts (CyberPatterns 2014)
Empirical Patterns in Google Scholar Citation Counts (CyberPatterns 2014)
 
Certifying (RISC) Machine Code Safe from Aliasing (OpenCert 2013)
Certifying (RISC) Machine Code Safe from Aliasing  (OpenCert 2013)Certifying (RISC) Machine Code Safe from Aliasing  (OpenCert 2013)
Certifying (RISC) Machine Code Safe from Aliasing (OpenCert 2013)
 
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
 
Higher Order Applicative XML (Monterey 2002)
Higher Order Applicative XML (Monterey 2002)Higher Order Applicative XML (Monterey 2002)
Higher Order Applicative XML (Monterey 2002)
 
Raiding the Noosphere
Raiding the NoosphereRaiding the Noosphere
Raiding the Noosphere
 
Abstract Interpretation meets model checking near the 1000000 LOC mark: Findi...
Abstract Interpretation meets model checking near the 1000000 LOC mark: Findi...Abstract Interpretation meets model checking near the 1000000 LOC mark: Findi...
Abstract Interpretation meets model checking near the 1000000 LOC mark: Findi...
 
Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux ...
Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux ...Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux ...
Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux ...
 
Open Source Verification under a Cloud (OpenCert 2010)
Open Source Verification under a Cloud (OpenCert 2010)Open Source Verification under a Cloud (OpenCert 2010)
Open Source Verification under a Cloud (OpenCert 2010)
 

Recently uploaded

aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
siemaillard
 
Home assignment II on Spectroscopy 2024 Answers.pdf
Home assignment II on Spectroscopy 2024 Answers.pdfHome assignment II on Spectroscopy 2024 Answers.pdf
Home assignment II on Spectroscopy 2024 Answers.pdf
Tamralipta Mahavidyalaya
 
678020731-Sumas-y-Restas-Para-Colorear.pdf
678020731-Sumas-y-Restas-Para-Colorear.pdf678020731-Sumas-y-Restas-Para-Colorear.pdf
678020731-Sumas-y-Restas-Para-Colorear.pdf
CarlosHernanMontoyab2
 
The French Revolution Class 9 Study Material pdf free download
The French Revolution Class 9 Study Material pdf free downloadThe French Revolution Class 9 Study Material pdf free download
The French Revolution Class 9 Study Material pdf free download
Vivekanand Anglo Vedic Academy
 
Language Across the Curriculm LAC B.Ed.
Language Across the  Curriculm LAC B.Ed.Language Across the  Curriculm LAC B.Ed.
Language Across the Curriculm LAC B.Ed.
Atul Kumar Singh
 
Overview on Edible Vaccine: Pros & Cons with Mechanism
Overview on Edible Vaccine: Pros & Cons with MechanismOverview on Edible Vaccine: Pros & Cons with Mechanism
Overview on Edible Vaccine: Pros & Cons with Mechanism
DeeptiGupta154
 
Guidance_and_Counselling.pdf B.Ed. 4th Semester
Guidance_and_Counselling.pdf B.Ed. 4th SemesterGuidance_and_Counselling.pdf B.Ed. 4th Semester
Guidance_and_Counselling.pdf B.Ed. 4th Semester
Atul Kumar Singh
 
Embracing GenAI - A Strategic Imperative
Embracing GenAI - A Strategic ImperativeEmbracing GenAI - A Strategic Imperative
Embracing GenAI - A Strategic Imperative
Peter Windle
 
Thesis Statement for students diagnonsed withADHD.ppt
Thesis Statement for students diagnonsed withADHD.pptThesis Statement for students diagnonsed withADHD.ppt
Thesis Statement for students diagnonsed withADHD.ppt
EverAndrsGuerraGuerr
 
1.4 modern child centered education - mahatma gandhi-2.pptx
1.4 modern child centered education - mahatma gandhi-2.pptx1.4 modern child centered education - mahatma gandhi-2.pptx
1.4 modern child centered education - mahatma gandhi-2.pptx
JosvitaDsouza2
 
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...
Levi Shapiro
 
Introduction to AI for Nonprofits with Tapp Network
Introduction to AI for Nonprofits with Tapp NetworkIntroduction to AI for Nonprofits with Tapp Network
Introduction to AI for Nonprofits with Tapp Network
TechSoup
 
Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46
Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46
Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46
MysoreMuleSoftMeetup
 
Model Attribute Check Company Auto Property
Model Attribute  Check Company Auto PropertyModel Attribute  Check Company Auto Property
Model Attribute Check Company Auto Property
Celine George
 
A Strategic Approach: GenAI in Education
A Strategic Approach: GenAI in EducationA Strategic Approach: GenAI in Education
A Strategic Approach: GenAI in Education
Peter Windle
 
Synthetic Fiber Construction in lab .pptx
Synthetic Fiber Construction in lab .pptxSynthetic Fiber Construction in lab .pptx
Synthetic Fiber Construction in lab .pptx
Pavel ( NSTU)
 
The Accursed House by Émile Gaboriau.pptx
The Accursed House by Émile Gaboriau.pptxThe Accursed House by Émile Gaboriau.pptx
The Accursed House by Émile Gaboriau.pptx
DhatriParmar
 
The geography of Taylor Swift - some ideas
The geography of Taylor Swift - some ideasThe geography of Taylor Swift - some ideas
The geography of Taylor Swift - some ideas
GeoBlogs
 
Operation Blue Star - Saka Neela Tara
Operation Blue Star   -  Saka Neela TaraOperation Blue Star   -  Saka Neela Tara
Operation Blue Star - Saka Neela Tara
Balvir Singh
 
Adversarial Attention Modeling for Multi-dimensional Emotion Regression.pdf
Adversarial Attention Modeling for Multi-dimensional Emotion Regression.pdfAdversarial Attention Modeling for Multi-dimensional Emotion Regression.pdf
Adversarial Attention Modeling for Multi-dimensional Emotion Regression.pdf
Po-Chuan Chen
 

Recently uploaded (20)

aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
 
Home assignment II on Spectroscopy 2024 Answers.pdf
Home assignment II on Spectroscopy 2024 Answers.pdfHome assignment II on Spectroscopy 2024 Answers.pdf
Home assignment II on Spectroscopy 2024 Answers.pdf
 
678020731-Sumas-y-Restas-Para-Colorear.pdf
678020731-Sumas-y-Restas-Para-Colorear.pdf678020731-Sumas-y-Restas-Para-Colorear.pdf
678020731-Sumas-y-Restas-Para-Colorear.pdf
 
The French Revolution Class 9 Study Material pdf free download
The French Revolution Class 9 Study Material pdf free downloadThe French Revolution Class 9 Study Material pdf free download
The French Revolution Class 9 Study Material pdf free download
 
Language Across the Curriculm LAC B.Ed.
Language Across the  Curriculm LAC B.Ed.Language Across the  Curriculm LAC B.Ed.
Language Across the Curriculm LAC B.Ed.
 
Overview on Edible Vaccine: Pros & Cons with Mechanism
Overview on Edible Vaccine: Pros & Cons with MechanismOverview on Edible Vaccine: Pros & Cons with Mechanism
Overview on Edible Vaccine: Pros & Cons with Mechanism
 
Guidance_and_Counselling.pdf B.Ed. 4th Semester
Guidance_and_Counselling.pdf B.Ed. 4th SemesterGuidance_and_Counselling.pdf B.Ed. 4th Semester
Guidance_and_Counselling.pdf B.Ed. 4th Semester
 
Embracing GenAI - A Strategic Imperative
Embracing GenAI - A Strategic ImperativeEmbracing GenAI - A Strategic Imperative
Embracing GenAI - A Strategic Imperative
 
Thesis Statement for students diagnonsed withADHD.ppt
Thesis Statement for students diagnonsed withADHD.pptThesis Statement for students diagnonsed withADHD.ppt
Thesis Statement for students diagnonsed withADHD.ppt
 
1.4 modern child centered education - mahatma gandhi-2.pptx
1.4 modern child centered education - mahatma gandhi-2.pptx1.4 modern child centered education - mahatma gandhi-2.pptx
1.4 modern child centered education - mahatma gandhi-2.pptx
 
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...
 
Introduction to AI for Nonprofits with Tapp Network
Introduction to AI for Nonprofits with Tapp NetworkIntroduction to AI for Nonprofits with Tapp Network
Introduction to AI for Nonprofits with Tapp Network
 
Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46
Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46
Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46
 
Model Attribute Check Company Auto Property
Model Attribute  Check Company Auto PropertyModel Attribute  Check Company Auto Property
Model Attribute Check Company Auto Property
 
A Strategic Approach: GenAI in Education
A Strategic Approach: GenAI in EducationA Strategic Approach: GenAI in Education
A Strategic Approach: GenAI in Education
 
Synthetic Fiber Construction in lab .pptx
Synthetic Fiber Construction in lab .pptxSynthetic Fiber Construction in lab .pptx
Synthetic Fiber Construction in lab .pptx
 
The Accursed House by Émile Gaboriau.pptx
The Accursed House by Émile Gaboriau.pptxThe Accursed House by Émile Gaboriau.pptx
The Accursed House by Émile Gaboriau.pptx
 
The geography of Taylor Swift - some ideas
The geography of Taylor Swift - some ideasThe geography of Taylor Swift - some ideas
The geography of Taylor Swift - some ideas
 
Operation Blue Star - Saka Neela Tara
Operation Blue Star   -  Saka Neela TaraOperation Blue Star   -  Saka Neela Tara
Operation Blue Star - Saka Neela Tara
 
Adversarial Attention Modeling for Multi-dimensional Emotion Regression.pdf
Adversarial Attention Modeling for Multi-dimensional Emotion Regression.pdfAdversarial Attention Modeling for Multi-dimensional Emotion Regression.pdf
Adversarial Attention Modeling for Multi-dimensional Emotion Regression.pdf
 

A Semantic Model for VHDL-AMS (CHARME '97)

  • 1. ? A semantic model for VHDL-AMS Natividad Mart´ınez Madrid, Peter T. Breuer, Carlos Delgado Kloos Universidad Carlos III de Madrid <nmadrid,ptb,cdk>@it.uc3m.es CHARME ’97, Montr´eal, Canada - October 1997 1
  • 2. Objectives ? • explain behaviour of VHDL-AMS processes – not a detailed syntactic mapping – provide sufficient primitives • present an underlying model that . . . – extends existing model for VHDL CHARME ’97, Montr´eal, Canada - October 1997 2
  • 3. Content of the talk ? • Introduction • A process algebraic analysis • Semantics • The analog solver with example CHARME ’97, Montr´eal, Canada - October 1997 3
  • 4. Main idea ? VHDL semantics analog extension imperative discrete-event diff. equations real time domain declarative continuous-time ց ւ INTEGRATION CHARME ’97, Montr´eal, Canada - October 1997 4
  • 5. Name space division & Properties ? VARIABLES assigned instantaneously not scheduled SIGNALS at least δ-delayed preemptively scheduled QUANTITIES assigned instantaneously governed by diff. eqns. PROCESSES invariant invariant CHARME ’97, Montr´eal, Canada - October 1997 5
  • 6. Semantics of assignment ? 00 00 00 0 0000000000000000000000000 11 11 11 1 1111111111111111111111111 0000000000000000000000000 0000000000000000000000000 0000000000000000000000000 00000000000000000000000000000000000000000000000000 1111111111111111111111111 1111111111111111111111111 1111111111111111111111111 11111111111111111111111111111111111111111111111111 000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000 0000000000000000000000000 111111111111111111111111111111111111111111111111111111111111111111111111111 1111111111111111111111111 1111111111111111111111111 00000000000000000000000000 0000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000 11111111111111111111111111 1111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111 00000111110011 "Forced" signal assignment a <= 1 after 4 00000000000000000000 00000000000000000000 00000000000000000000 11111111111111111111 11111111111111111111 11111111111111111111 a 000000000000000000000000000000000000000000000000000000000000000000000000000000 111111111111111111111111111111111111111111111111111111111111111111111111111111 . v = x . 00000111110011 "Relaxed" quantity update 0 00 000 0000 1 11 111 1111 0 00 000 0000 1 11 111 1111 000 111 000 111000000000000000000000000000000000000000000000000000000000000000000000000000000 111111111111111111111111111111111111111111111111111111111111111111111111111111x a = v CHARME ’97, Montr´eal, Canada - October 1997 6
  • 7. Semantic Domains ? WorldLine = Time → State State = Id → V alue VHDL Statements Semantics = (WorldLine, Time) ↔ (WorldLine, Time) Time = Int VHDL-AMS Statements Semantics = (EqnSet, WorldLine, Time) ↔ (EqnSet, WorldLine, Time) Time = Real CHARME ’97, Montr´eal, Canada - October 1997 7
  • 8. Parallel decomposition ? LRM view of basic VHDL compositionality: • processes in parallel (+ kernel) • process body loops continuously • imperative commands in process body run sequentially Our view: • no kernel CHARME ’97, Montr´eal, Canada - October 1997 8
  • 9. VHDL-AMS: integer time → real time Analog Solver
  • 10. Process algebraic analysis ? 000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 111111111111111111111111111111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111111111111111111111111 00000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 11111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 Ai Aj Σj Σi Σj Pj’ Pi’ Pi Pj Ki Kj Σi 00000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000 11111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111 1111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111 000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000 111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111 AS Ai Aj Σj Σi Σj Pj’ Pi’ Pj Ki Kj Σi Pi CHARME ’97, Montr´eal, Canada - October 1997 9
  • 11. Process algebraic analysis (II) ? 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000 111111111111111111111111111111111111111 111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111 111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111 000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111 111111111111111111111111111111111111111 00000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 00000000000000000000 000000000000000000000000000000000000000000000000000000000000 11111111111111111111 1111111111111111111111111111111111111111 1111111111111111111111111111111111111111 1111111111111111111111111111111111111111 11111111111111111111 111111111111111111111111111111111111111111111111111111111111 00000000000000000000 00000000000000000000 000000000000000000000000000000000000000000000000000000000000 00000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 11111111111111111111 11111111111111111111 111111111111111111111111111111111111111111111111111111111111 11111111111111111111 1111111111111111111111111111111111111111 1111111111111111111111111111111111111111 1111111111111111111111111111111111111111 iΣ Σj ’iΣ ’jΣ K’i Σ Σ Q AS Q AS KAj KAi Pi Pj Ai Aj K’j Pj’ Pi’ CHARME ’97, Montr´eal, Canada - October 1997 10
  • 12. Denotational semantics ? S[a; b] = S[a]; S[b] P[a; b] = P[a] ∪ S[a]; P[b] S[while(true)do a end] = { } P[while(true)do a end] = P[a] ∪ S[a]; P[while(true)do a end] = µR : Semantics . R = P[a] ∪ S[a]; R S[a||b] = S[a] ∩ S[b] P[a||b] = P[a] ∩ P[b] CHARME ’97, Montr´eal, Canada - October 1997 11
  • 13. Wait & Assignment semantics ? Wait Semantics (e, w0, t0)S[wait until p](e, w1, t1) = w0 = w1 ∧ wt1 |= p ∧ ∀t ∈ [t0, t1) . wt |= p (e, w0, t0)P[wait until p](e, w1, t1) = w0 = w1 ∧ ∀t ∈ [t0, t1] . wt |= p Assignment Semantics (e, w0, t0)S[x ⇐ y after τ](e, w1, t1) = t0 = t1 ∧ w1 = relax(e, t0)(force assign(w0)) P[x ⇐ y after τ] = { } CHARME ’97, Montr´eal, Canada - October 1997 12
  • 14. Wait semantics ? 0 00 00 0 000 0 00 1 11 11 1 111 1 11 00000000000000000000 0000000000000000000000000000000000000000 11111111111111111111 1111111111111111111111111111111111111111 Generalized Wait a x wait until a = 1 on signals -> discrete time 00000000000000000000 0000000000000000000000000000000000000000 11111111111111111111 1111111111111111111111111111111111111111 00 0 0 000 0 000 0 11 1 1 111 1 111 1 00000000000000000000 00000000000000000000 00000000000000000000 11111111111111111111 11111111111111111111 11111111111111111111 0 0 00 0 0 000 0 00 1 1 11 1 1 111 1 11 wait until x >= 2/3 on quantities -> continuous time CHARME ’97, Montr´eal, Canada - October 1997 13
  • 15. Sequential composition ? ; 000000000000111111111111 000000000000 0000 0000 00000000 00000000 00000000 00000000 0000 000000000000 0000 000000000000 0000 000000000000 0000 0000 111111111111 1111 1111 11111111 11111111 11111111 11111111 1111 111111111111 1111 111111111111 1111 111111111111 1111 1111 a x 000000 000 000 000000000 000 000000 000000 000 000000000 000 000000000 000 000 111111 111 111 111111111 111 111111 111111 111 111111111 111 111111111 111 111 00000000000001111111111111 0000 00 00 000000 00 0000 0000 00 000000 00 000000 00 00 1111 11 11 111111 11 1111 1111 11 111111 11 111111 11 11 000000000000111111111111 000000000000111111111111 000000000000 0000 0000 00000000 00000000 00000000 00000000 0000 000000000000 0000 000000000000 0000 000000000000 0000 0000 111111111111 1111 1111 11111111 11111111 11111111 11111111 1111 111111111111 1111 111111111111 1111 111111111111 1111 1111 a x 000000 000 000 000000000 000 000000 000000 000 000000000 000 000000000 000 000 111111 111 111 111111111 111 111111 111111 111 111111111 111 111111111 111 111 00000000000001111111111111 0000 00 00 000000 00 0000 0000 00 000000 00 000000 00 00 1111 11 11 111111 11 1111 1111 11 111111 11 111111 11 11 000000000000111111111111 000000000000111111111111 000000000000 0000 0000 00000000 00000000 00000000 00000000 0000 000000000000 0000 000000000000 0000 000000000000 0000 0000 111111111111 1111 1111 11111111 11111111 11111111 11111111 1111 111111111111 1111 111111111111 1111 111111111111 1111 1111 a x 000000 000 000 000000000 000 000000 000000 000 000000000 000 000000000 000 000 111111 111 111 111111111 111 111111 111111 111 111111111 111 111111111 111 111 00000000000001111111111111 0000 00 00 000000 00 0000 0000 00 000000 00 000000 00 00 1111 11 11 111111 11 1111 1111 11 111111 11 111111 11 11 000000000000111111111111 . v = x . a = v wait until x >= 2/3wait until x >= 2/3wait until x >= 2/3a <= 1 after 4 CHARME ’97, Montr´eal, Canada - October 1997 14
  • 16. Analog solution ? Bouncing ball example ds dt = v dv dt = −g ± av2 Local approximation s(t) = 1 v(t) = −gt origin at s = 1 v = 0 t = 0 Linear approximation (s, v) = (s0, v0) + (t − t0)(v0, −g ± av2 0) Recursion (s, v)(t0,s0,v0)(t) ∼    (s0, v0) + (t − t0)(v0, −g ± av2 0) t ∈ [t0, t1) (s, v)(t1,s1,v1)(t) s1 = s0 + v0∆t v1 = v0 + (−g ± av2 0)∆t t1 = t0 + ∆t CHARME ’97, Montr´eal, Canada - October 1997 15
  • 17. Example ? proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ] ds/dt == v; dv/dt == -g + if v<0 then a else -a end * v * v; begin wait until s < 0; v := -v; s := 0 ; end ∆t = 0.02 CHARME ’97, Montr´eal, Canada - October 1997 16
  • 18. Example Cont. ? proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ] ds/dt == v; dv/dt == -g + if v<0 then a else -a end * v * v; begin wait until s < 0; v := 1.4142 * (g * s + 0.5 * v * v)**0.5 ; s := 0 ; end g ∗ 0 + v′2 2 = g ∗ s + v2 2 ∆t = 0.06 CHARME ’97, Montr´eal, Canada - October 1997 17
  • 19. Example Cont. (II) ? Height Speed ∆t = 0.06 CHARME ’97, Montr´eal, Canada - October 1997 18
  • 20. Unresolved areas ? • Implementation of the parallel composition of pro- cesses if quantities are shared between processes • Errors in the analog solver may require us to rewrite our program • The proper execution of the analog solver in δ time when the processes are in parallel CHARME ’97, Montr´eal, Canada - October 1997 19
  • 21. Conclusion ? • What? Extension of our VHDL semantics to cover VHDL-AMS • How? Embedding of the VHDL semantics in a bigger, continuous time domain, which contains an oracular analog solver • Why? Clarify the draft standard document CHARME ’97, Montr´eal, Canada - October 1997 20