2. Structural modeling
● Structural VHDL models the structure of a circuit;
similar to circuit schematic
– Defines the circuit components
– Describes how components are connected
3. Modeling the Structural way
● Structural architecture
– implements the module as a composition of
subsystems
– contains
● component instances
– instances of previously declared entity/architecture pairs
● signal declarations, for internal interconnections
– the entity ports are also treated as signals
● port maps in component instances
– connect signals to component ports
7. Component Declarations
● Component declarations reference the components
that are to be connected
– Identified by keyword „component’
● Definition terminated by ‘end component’
– Port statement define the interface
● Identifier, direction, type same as in port statement in design
entity interface definition
– Component to entity association is defined by a
„configuration‟
● Default configuration associates components and entities that
have the same interface
8. Example - Structural VHDL Body
architecture STRUCTURE of MAJORITY is
-- Declaration of components and local signals
component AND2_OP
port (A, B : in BIT; Z : out BIT);
end component;
component OR3_OP
port (A, B, C : in BIT; Z : out BIT);
end component;
signal INT1, INT2, INT3 : BIT;
9. Signal Declarations
● Instantiated components need connecting; signals
do this
– Effectively form the internal gate-to-gate wiring
– Keyword is ‘signal’
– Must specify identifier(s) and type
10. Component Instantiation Statements
● Component instantiation statements define specific,
names instances of components
– Prefaced with a label: identifier (names the part)
– Followed by the component name
– Followed by keyword ‘port map’
– Followed by signal map list
● Associates signals with component interface entity
● Connectivity is either positional association or named
association
11. Example VHDL Statement Part
begin
-- Define the component connections
A1: AND2_OP port map (A_IN, B_IN, INT1);
A2: AND2_OP port map (A_IN, C_IN, INT2);
A3: AND2_OP port map (B_IN, C_IN, INT3);
O1: OR3_OP port map (INT1, INT2, INT3, Z_OUT);
end STRUCTURE;
12. Port Map Associations
● Positional association connects port identifiers to port
map identifiers in order of occurrence
● Named association explicitly identifies the connection
between port identifiers and port map identifiers
– Association is “port name => signal name”
– left side: "formals" (port names from component declaration)
– right side: "actuals" (architecture signals)
– Associations can appear in any order
● Both associations can appear in one port map
– Positional before named
A1: AND2_OP port map (Z=>INT1, B=>B_IN, A=>A_IN);
14. ● HDL allows for a hierarchical model layout, which
means that a module can be assembled out of several
submodules. The connections between these submodules
are defined within the architecture of a top module.
● As you can see, a fulladder can be built with the help of
two halfadders (module1, module2) and an OR gate
(module3).
● A purely structural architecture does not describe any
functionality and contains just a list of components, their
instantiation and the definition of their interconnections.
15. entity FULLADDER is
port (A,B, CARRY_IN: in bit;
SUM, CARRY: out bit);
end FULLADDER;
architecture STRUCT of FULLADDER is
signal W_SUM, W_CARRY1, W_CARRY2 : bit;
component HALFADDER
port (X, Y : in bit;
S, C : out bit);
end component;
component ORGATE
port (IP1, IP2 : in bit;
OP : out bit);
end component;
16. begin
MODULE1: HALFADDER port map (A, B,
W_SUM, W_CARRY1 );
MODULE2: HALFADDER port map (W_SUM,
CARRY_IN, SUM, W_CARRY2 );
MODULE3: ORGATE port map (W_CARRY2,
W_CARRY1, CARRY);
end STRUCT;
17. Design entities – Half adder
entity HALFADDER
port (X, Y : in bit;
S, C : out bit);
end entity;
Architecture BEH of HALFADDER is
Begin
S<=X xor Y;
C<= X and Y;
End beh;
18. Design entities – OR gate
entity ORGATE
port (IP1, IP2 : in bit;
OP : out bit);
end entity;
Architecture BEH of ORGATE is
Begin
OP<=IP1 or IP2;
end BEH
19. ● As the fulladder consists of several submodules,
they have to be "introduced" first. In a component
declaration all module types which will be used,
are declared.
● This declaration has to occur before the 'begin'
keyword of the architecture statement. Note, that
just the interface of the modules is given here and
their use still remains unspecified.
20. entity FULLADDER is
port (A,B, CARRY_IN: in bit;
SUM, CARRY: out bit);
end FULLADDER;
architecture STRUCT of FULLADDER is
component HALFADDER
port (X, Y : in bit;
S, C: out bit);
end component;
. . .
21. signal W_SUM, W_CARRY1, W_CARRY2 : bit;
begin
MODULE1: HALFADDER
port map (X => A,
S => W_SUM,
Y => B,
C => W_CARRY1 );
. . .
end STRUCT;
25. Design entities used in Structural VHDL
code of 9-bit Parity generator circuit –
XOR gate
Entity XOR2 is
Port (A,B: in std_logic; Z:out STD_LOGIC);
End XOR2;
Architecture BEH of XOR2 is
Begin
Z<=A xor B;
End BEH;
26. Design entities used in Structural VHDL
code of 9-bit Parity generator circuit –
XOR gate
Entity INV2 is
Port (A: in std_logic; Z:out STD_LOGIC);
End INV2;
Architecture BEH of INV2 is
Begin
Z<=not A;
End BEH;
30. Design entities used in Structural VHDL
code of Decade counter – JK F/F
entity JK_FF is
port (J, K, ck: in std_logic;
Q, NQ: Buffer std_logic);
end JK_FF;
architecture behv of JK_FF is
begin
input <= J & K; -- combine inputs into vector
31. p: process (ck)
begin
if (ck=„1‟ and ck‟event) then
case (input) is
when "11" =>
Q<=not Q; NQ<=not Nbar;
when "10" =>
Q <= '1'; NQ<=0;
when "01" =>
Q <= '0'; NQ<=1;
when others =>
null;
end case;
end if;
end process;
end behv;
32. And gate
Entity AND_GATE is
Port (A,B:in std_logic; C:out STD_LOGIC);
End AND_GATE;
Architecture BEH of AND_GATE is
Begin
C<=A and B;
End BEH;
33. References
● [1]. “Digital Systems Design Using VHDL” by
Charles H Roth, Jr., Thomson Learining,
Brooks/Cole.
● [2]. “VHDL Primer” by J Bhasker, PHI, Third
edition.
