A Prototype Storage Subsystem based on Phase Change MemoryIBM Research
IBM scientists for the first time demonstrated a hybrid storage and caching subsystem, code-named Project Theseus, at the recent 2014 Non-Volatile Memories Workshop in San Francisco, California. And the amazing achievement is that they were using two year old PCM chip prototypes.
IDT DDR4 RCD register and DB data buffer enable RDIMM and LRDIMM to faster speeds and deeper memories. This video helps you understand the DDR4 feature enhancements of IDT's DDR4 RCD and DB compared to earlier DDR3 technology. An introduction into some available LeCroy testing and debug tools completes the video. Presented by Douglas Malech, Product Marketing Manager at IDT and Mike Micheletti, Product Manager at Teledyne LeCroy. To learn more about IDT's leading portfolio of memory interface products, visit www.idt.com/go/MIP.
Advanced and innovative features of DDR4 designs enable high speed operation and broad applicability in a variety including servers, laptops, desktop PCs and consumer products. It aims at simplifying migration and enabling adoption of an industry-wide standard.
Highlighted notes while studying Concurrent Data Structures:
DDR3 SDRAM
Source: Wikipedia
Double Data Rate 3 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR3 SDRAM, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
A Prototype Storage Subsystem based on Phase Change MemoryIBM Research
IBM scientists for the first time demonstrated a hybrid storage and caching subsystem, code-named Project Theseus, at the recent 2014 Non-Volatile Memories Workshop in San Francisco, California. And the amazing achievement is that they were using two year old PCM chip prototypes.
IDT DDR4 RCD register and DB data buffer enable RDIMM and LRDIMM to faster speeds and deeper memories. This video helps you understand the DDR4 feature enhancements of IDT's DDR4 RCD and DB compared to earlier DDR3 technology. An introduction into some available LeCroy testing and debug tools completes the video. Presented by Douglas Malech, Product Marketing Manager at IDT and Mike Micheletti, Product Manager at Teledyne LeCroy. To learn more about IDT's leading portfolio of memory interface products, visit www.idt.com/go/MIP.
Advanced and innovative features of DDR4 designs enable high speed operation and broad applicability in a variety including servers, laptops, desktop PCs and consumer products. It aims at simplifying migration and enabling adoption of an industry-wide standard.
Highlighted notes while studying Concurrent Data Structures:
DDR3 SDRAM
Source: Wikipedia
Double Data Rate 3 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR3 SDRAM, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
Persistent memory holds a lot of promise: what's not to like about vast amounts of directly-attached memory that remembers its contents over a power cycle? For some years we have been told that large persistent-memory arrays are coming; now it seems that they are about to arrive. In this lecture we will be covering the following:
What is Persistent Memory , The upcoming storage class memory (SCM)devices.
Difference between NVMe and SCM
How to use it and emulate it
Challenge : Durability / Consistency
Remote access
Implication for Next Generation Architecture
In this talk, we describe the latest trends and advancements in storage-class memory (a.k.a. Non-Volatile Memory) and its impact on data infrastructure as it exists today. We also describe how Ampool is building a product that allows Big Data analysis solutions to work together with a smart storage class memory layer to allow fast & complex end to end analytical pipelines, thus lowering the time-to-insights significantly.
Controller design for multichannel nand flash memory for higher efficiency in...eSAT Journals
Abstract Flash based storage system is presently very attractive in the market than the previous Magnetic disk drives. Flash memory is basically Non-Volatile memory; it means it can electrically erasable and programmable. The Flash memory has less power consumption and less latency compare to previous magnetic disk drives, this makes flash more attractive and popular. Flash memory basically comprises of three basic operations, they are Read, Write (program), and Erase. The Flash memory will be written in pages and will be erased in blocks. Functions of the multi-channel parallel controller are validated according to a wide spread of workloads. The proposed Flash controller develops its own method for the reorganization and mapping of invalid blocks in a Flash chip. This paper explains about new flash controller design and control signals for flash operations and also exploits the parallelism by using multiple channels or multiple controllers for single flash memory in order to reduce the further latency in read, write and erase operation. Keywords: NAND Flash Controller; Multichannel; SSD;
Keynote presentation from Flash Memory Summit 2016 by Dr. Siva Sivaram.
Learn his perspective on opportunities and challenges in developing a memory cell solution for the Storage Class Memory market, and lessons learned from 3D NAND.
Persistent memory holds a lot of promise: what's not to like about vast amounts of directly-attached memory that remembers its contents over a power cycle? For some years we have been told that large persistent-memory arrays are coming; now it seems that they are about to arrive. In this lecture we will be covering the following:
What is Persistent Memory , The upcoming storage class memory (SCM)devices.
Difference between NVMe and SCM
How to use it and emulate it
Challenge : Durability / Consistency
Remote access
Implication for Next Generation Architecture
In this talk, we describe the latest trends and advancements in storage-class memory (a.k.a. Non-Volatile Memory) and its impact on data infrastructure as it exists today. We also describe how Ampool is building a product that allows Big Data analysis solutions to work together with a smart storage class memory layer to allow fast & complex end to end analytical pipelines, thus lowering the time-to-insights significantly.
Controller design for multichannel nand flash memory for higher efficiency in...eSAT Journals
Abstract Flash based storage system is presently very attractive in the market than the previous Magnetic disk drives. Flash memory is basically Non-Volatile memory; it means it can electrically erasable and programmable. The Flash memory has less power consumption and less latency compare to previous magnetic disk drives, this makes flash more attractive and popular. Flash memory basically comprises of three basic operations, they are Read, Write (program), and Erase. The Flash memory will be written in pages and will be erased in blocks. Functions of the multi-channel parallel controller are validated according to a wide spread of workloads. The proposed Flash controller develops its own method for the reorganization and mapping of invalid blocks in a Flash chip. This paper explains about new flash controller design and control signals for flash operations and also exploits the parallelism by using multiple channels or multiple controllers for single flash memory in order to reduce the further latency in read, write and erase operation. Keywords: NAND Flash Controller; Multichannel; SSD;
Keynote presentation from Flash Memory Summit 2016 by Dr. Siva Sivaram.
Learn his perspective on opportunities and challenges in developing a memory cell solution for the Storage Class Memory market, and lessons learned from 3D NAND.
NVMe PCIe and TLC V-NAND It’s about TimeDell World
With an explosion in data and the relentless growth in demand for information, identifying a much more efficient means of storage has become extremely important. In this session, we will cover the key drivers behind the need for faster and more efficient storage. NVMe, a standardized protocol for PCIe-based storage, is giving users the huge leap in bandwidth required for demanding applications. Samsung, who makes the fastest NVMe SSDs on the market, will cover the benefits enabled by such technology, in areas such as fraud prevention and surgical procedures.
The technology behind flash drives – NAND memory – will be spotlighted in this presentation. Memory manufacturers have improved NAND’s value by migrating from single-level-cell to multi-level-cell designs, but the most significant evolution will be a marriage of triple-level-cell and V-NAND flash manufacturing technologies. Samsung will also provide an overview of the prospects for TLC V-NAND with mobile device manufacturers, while examining the strong potential for a much wider TLC V-NAND market in data centers.
PCI Express* based Storage: Data Center NVM Express* Platform TopologiesOdinot Stanislas
(FR)
Le PCI Express se démocratise de plus en plus dans les serveurs. Présents depuis des années comme bus pour les cartes d'extensions, on va maintenant le trouver en façades des serveurs pour servir des disque flash 2,5 pouces (connecteur SF-8639) et sous la forme de câble appelés OCulink.
(EN)
PCI Express is becoming more and more present in servers. As a communication bus for extension cards since years, now it will serve 2.5 inches flash drive and through PCIe cables named OCulink.
Auteurs/Authors:
Michael Hall
Director of Technology Solutions Enabling, Data Center Group, Intel Corporation
Jonmichael Hands
Technical Program Manager, Non-Volatile Memory Solutions Group, Intel Corporation
Intel and DataStax: 3D XPoint and NVME Technology Cassandra Storage ComparisonDataStax Academy
Does your choice of storage really matter in a Cassandra deployment? Intel and Datastax engineers will discuss results of recent performance testing on a variety of storage devices including classic spinning media, SATA SSD’s and NVMe SSD’s. Session will include an overview of the various storage types, and technology trends. Next we will discuss our recent testing and look at some preliminary results. Even if you are only at the early stages of considering a Cassandra deployment, fully understanding the impact storage choices have on your results can be critical to your projects success.
Moving to PCI Express based SSD with NVM ExpressOdinot Stanislas
Une très bonne présentation qui introduit la technologie NVM Express qui sera à coup sure l'interface du futur (proche) des "disques" SSD. Adieu SAS et SATA, bienvenu au PCI Express dans les serveurs (et postes clients)
RAM.pptx it is about random access memory which is used Pcravigareja045
PPT ABOUT THE RANDOM ACCESS MEMORY . It is used in operating system it is very useful
Random-access memory (RAM; /ræm/) is a form of electronic computer memory that can be read and changed in any order, typically used to store working data and machine code.[1][2] A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.Random-access memory (RAM; /ræm/) is a form of electronic computer memory that can be read and changed in any order, typically used to store working data and machine code.[1][2] A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.Random-access memory (RAM; /ræm/) is a form of electronic computer memory that can be read and changed in any order, typically used to store working data and machine code.[1][2] A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
Random-access memory (RAM; /ræm/) is a form of electronic computer memory that can be read and changed in any order, typically used to store working data and machine code.[1][2] A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
Random-access memory (RAM; /ræm/) is a form of electronic computer memory that can be read and changed in an
Some key value stores using log-structureZhichao Liang
This slides presents three key-value stores using log-structure, includes Riak, RethinkDB, LevelDB. BTW, i state that RethinkDB employs append-only B-tree and that is an estimate made by combining guessing wih reasoning!
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
SAP Sapphire 2024 - ASUG301 building better apps with SAP Fiori.pdfPeter Spielvogel
Building better applications for business users with SAP Fiori.
• What is SAP Fiori and why it matters to you
• How a better user experience drives measurable business benefits
• How to get started with SAP Fiori today
• How SAP Fiori elements accelerates application development
• How SAP Build Code includes SAP Fiori tools and other generative artificial intelligence capabilities
• How SAP Fiori paves the way for using AI in SAP apps
Generative AI Deep Dive: Advancing from Proof of Concept to ProductionAggregage
Join Maher Hanafi, VP of Engineering at Betterworks, in this new session where he'll share a practical framework to transform Gen AI prototypes into impactful products! He'll delve into the complexities of data collection and management, model selection and optimization, and ensuring security, scalability, and responsible use.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Welocme to ViralQR, your best QR code generator.ViralQR
Welcome to ViralQR, your best QR code generator available on the market!
At ViralQR, we design static and dynamic QR codes. Our mission is to make business operations easier and customer engagement more powerful through the use of QR technology. Be it a small-scale business or a huge enterprise, our easy-to-use platform provides multiple choices that can be tailored according to your company's branding and marketing strategies.
Our Vision
We are here to make the process of creating QR codes easy and smooth, thus enhancing customer interaction and making business more fluid. We very strongly believe in the ability of QR codes to change the world for businesses in their interaction with customers and are set on making that technology accessible and usable far and wide.
Our Achievements
Ever since its inception, we have successfully served many clients by offering QR codes in their marketing, service delivery, and collection of feedback across various industries. Our platform has been recognized for its ease of use and amazing features, which helped a business to make QR codes.
Our Services
At ViralQR, here is a comprehensive suite of services that caters to your very needs:
Static QR Codes: Create free static QR codes. These QR codes are able to store significant information such as URLs, vCards, plain text, emails and SMS, Wi-Fi credentials, and Bitcoin addresses.
Dynamic QR codes: These also have all the advanced features but are subscription-based. They can directly link to PDF files, images, micro-landing pages, social accounts, review forms, business pages, and applications. In addition, they can be branded with CTAs, frames, patterns, colors, and logos to enhance your branding.
Pricing and Packages
Additionally, there is a 14-day free offer to ViralQR, which is an exceptional opportunity for new users to take a feel of this platform. One can easily subscribe from there and experience the full dynamic of using QR codes. The subscription plans are not only meant for business; they are priced very flexibly so that literally every business could afford to benefit from our service.
Why choose us?
ViralQR will provide services for marketing, advertising, catering, retail, and the like. The QR codes can be posted on fliers, packaging, merchandise, and banners, as well as to substitute for cash and cards in a restaurant or coffee shop. With QR codes integrated into your business, improve customer engagement and streamline operations.
Comprehensive Analytics
Subscribers of ViralQR receive detailed analytics and tracking tools in light of having a view of the core values of QR code performance. Our analytics dashboard shows aggregate views and unique views, as well as detailed information about each impression, including time, device, browser, and estimated location by city and country.
So, thank you for choosing ViralQR; we have an offer of nothing but the best in terms of QR code services to meet business diversity!
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
When stars align: studies in data quality, knowledge graphs, and machine lear...
Storage Class Memory: Technology Overview & System Impacts
1. Phase Change Memory
Storage Class Memory:
Technology Overview & System Impacts
Zhichao Liang
frankey0207@gmail.com
Storage Class Memory
2. Phase Change Memory
Outline
• Why & what is storage class memory?
• A typical storage class memory device: PCM
• The impacts of SCM on database system
• Conclusion
Storage Class Memory
3. Phase Change Memory
Outline
• Why & what is storage class memory?
• A typical storage class memory device: PCM
• The impacts of SCM on database system
• Conclusion
Storage Class Memory
7. Phase Change Memory
HDD access time (cont. )
Access time
rotation time seek time
HDD with a faster than HDD size will transform
15,000 rpm almost from 3.5-inch to 2.4-inch
impossible within the and then 1.8-inch for the
next 10 years! best case.
Storage Class Memory
8. Phase Change Memory
HDD power
• The power P supplied to a disk drive is given by P = I
+ M +S.
- I : power for interface & control logic;
- M: motor to spin the disk;
- S : move head to the new track.
I & M already close to S can be improved on smaller
their theoretical size disk drive or shutting down
efficiency limits! completely when not in use!
Storage Class Memory
9. Phase Change Memory
SSD disadvantage
• The short life time of SSD is an obstacle for its use in
industrial-length applications.
Device Endurance
DRAM 10 power 15
Disk drive 10 power 12
Flash memory 10 power 4 ~ 5
• The limited scalability of SSD
hinder its capacity increasing
& price decreasing.
Storage Class Memory
10. Phase Change Memory
Definition of SCM
• Storage Class Memory (SCM) is IBM’s term for a new
class of data storage and memory devices.
• SCM blurs the distinction between Memory (fast,
expensive, volatile) and Storage (slow, cheap, non-volatile).
• Features of SCM:
- Solid state, no moving parts
- Short Access times (within an order-of-magnitude of DRAM)
- Low cost per bit (DISK like, within an order-of-magnitude)
- Non-volatile ( ~ 10 years)
Storage Class Memory
14. Phase Change Memory
Outline
• Why & what is storage class memory?
• A typical storage class memory device: PCM
• The impacts of SCM on database system
• Conclusion
Storage Class Memory
15. Phase Change Memory
Phase change memory
• Phase change memory (PCM) is the leading contender
for first true SCM.
• At least 18 companies are working
on PCM, such as Samsung, IBM,
Intel, Micro, etc.
• PCM is an electronic device using
two distinct solid phases
of a metal alloy to store
a bit.
Storage Class Memory
16. Phase Change Memory
PCM basic concept
• Ge-Sb-Te exists in a (quasi)stable amorphous and a
stable crystalline phase.
- Phases have very different electrical resistances – ratio of
1:100 to 1:1000, and different optical reflectivity.
• Transition between phases by controlled heating and
cooling
- Write ‘1’ (SET) : longer (50ns) weaker current pulse
- Write ‘0’ (RESET) : short (10ns) intense current pulse
- Read : short weak pulse senses resistance
Storage Class Memory
17. Phase Change Memory
PCM
A data cell at each
of the intersections
of a wordline and a
bitline!
Slow crystallization
affects write
performance!
Storage Class Memory
18. Phase Change Memory
PCM vs DRAM
Device Type DRAM PCM-S PCM-M
Capacity 16GB 128GB 16GB
Feature Size 32nm 32nm 32nm
Read Latency 60ns 800ns 300ns
Write Latency 60ns 1400ns 1400ns
Retention Time ms 2-10 years dependent
Write Endurance 10 power 15 10 power 8 10 power 12
An SCM cell at the maximum write times would be worn out within a few
minutes! So a wear-leveling layer maybe necessary!
Storage Class Memory
19. Phase Change Memory
Taxonomy of PCM system uses
Memory Oriented: Storage Oriented:
1) PCM replaces DRAM 1) PCM replaces HDD/SSD
completely; completely;
2) PCM stands by DRAM. 2) PCM as the cache of
HDD/SSD.
PCM replaces DRAM completely:
L2 & L3 PCM
CPU PCM
cache control
Storage Class Memory
20. Phase Change Memory
Taxonomy of PCM system uses
Memory Oriented: Storage Oriented:
1) PCM replaces DRAM 1) PCM replaces HDD/SSD
completely; completely;
2) PCM stands by DRAM. 2) PCM as the cache of
HDD/SSD.
PCM stands by DRAM:
DRAM
CPU VM contol
PCM
PCM
control
Storage Class Memory
21. Phase Change Memory
Taxonomy of PCM system uses
Memory Oriented: Storage Oriented:
1) PCM replaces DRAM 1) PCM replaces HDD/SSD
completely; completely;
2) PCM stands by DRAM. 2) PCM as the cache of
HDD/SSD.
PCM replaces HDD/SSD completely:
1) Via legacy
I/O buses?
CPU I/O control PCM 2) Via new
PCM
control interface?
3) Page device ?
Storage Class Memory
22. Phase Change Memory
Taxonomy of PCM system uses
Memory Oriented: Storage Oriented:
1) PCM replaces DRAM 1) PCM replaces HDD/SSD
completely; completely;
2) PCM stands by DRAM. 2) PCM as the cache of
HDD/SSD.
PCM as the cache of HDD/SSD:
PCM
DRAM I/O control PCM HDD
control
Storage Class Memory
23. Phase Change Memory
Outline
• Why & what is storage class memory?
• A typical storage class memory device: PCM
• The impacts of PCM on database system
• Conclusion
Storage Class Memory
24. Phase Change Memory
Database system overview
Read & Write
Applications
Access Methods Transaction
Data Page &
Log File
Lock
B+ Tree Index
Hash Index
Buffer Pool
HDD
LRU, Clock
Log
Storage Class Memory
25. Phase Change Memory
PCM replaces DRAM
• PCM buffer pool access (300ns) will be slower than
DRAM buffer pool access (60ns).
• PCM buffer pool write (1400ns) will be slower than
DRAM buffer pool write (60ns).
• Data durability can be guaranteed even database
server restart or power off.
• What about logging? Logging is still necessary?
• Wear-leveling can be a problem!
• Rethink of buffer pool replacement strategy!
Storage Class Memory
26. Phase Change Memory
PCM replaces DRAM (cont.)
• PCM buffer pool access (300ns) will be slower than
DRAM buffer pool access (60ns).
• PCM buffer pool write (1400ns) will be slower than
DRAM buffer pool write (60ns). How to reduce
Asymmetric read
& write on PCM write on PCM
• Data durability can be guaranteed even database
server restart or power off.
• What about logging? Logging is still necessary?
• Wear-leveling can be a problem!
• Rethink of buffer pool replacement strategy!
Storage Class Memory
27. Phase Change Memory
PCM with DRAM
• Using PCM to extend the DRAM, older data in DRAM
will be transmitted to PCM.
• Or using PCM and DRAM in parallel mode.
• Complete data durability can not be guaranteed but
can be improved much.
• Rethink of buffer pool replacement strategy!
• How to make use of DRAM and PCM to achieve the
optimized lifetime of PCM.
Storage Class Memory
28. Phase Change Memory
PCM with DRAM (cont.)
• Using PCM to extend the DRAM, older data in DRAM
will be transmitted to PCM.
• Or using PCM and DRAM in parallel mode.
Data
Cool and hot
• Complete data durability can not beplacement but
data
guaranteed
can be improved much.
distinction strategy
• Rethink of buffer pool replacement strategy!
• How to make use of DRAM and PCM to achieve the
optimized lifetime of PCM.
Storage Class Memory
29. Phase Change Memory
PCM replaces HDD
• In the near future, the capacity of PCM won’t be as
much as disk.
• Even if whole DB fits in PCM and even though PCM is
persistent, still need to externalize DB regularly, since
PCM won’t have good endurance!
• In-memory buffer pool can be obviated, or at least
read buffer can be obviated.
• The read performance of DBMS can be improved
much, whatever sequential read or random read.
Storage Class Memory
30. Phase Change Memory
PCM replaces HDD (cont.)
• Hardware-enforced block boundaries, such as sector
on HDD and page on SSD, are eliminated.
- Unlikely large amounts of data become suddenly unavailable
- More likely bits, or small ranges of bytes will fail together
- Eliminates need for read-modify-write for small updates
• Opportunity to rethink data structures
for implementing database system,
such as B+ Tree, record organization,
etc.
Storage Class Memory
31. Phase Change Memory
PCM with HDD
• Using PCM to extend HDD, fresh data in PCM & older
data in HDD.
• Or using PCM for special use, e.g., storing index data
on PCM or logging data on PCM.
• The write performance can be improved much,
whatever sequential write or random write.
• How to reduce the amount of write when storing
index data on PCM?
• The best configuration of PCM & HDD capacity?
Storage Class Memory
32. Phase Change Memory
Conclusion
• SCM is an promising technology for building large
storage system.
• PCM has some special characteristics different from
HDD & SSD, which need to be reconsidered for
system design.
• Research on PCM-based database system just catch
the attention of researchers and a lot opportunities
are there.
Storage Class Memory