Suraj Ramaswamy is seeking a position in the semiconductor industry as an RTL Design/Verification engineer. He has a M.Tech in VLSI Design from Vellore Institute of Technology and has experience with projects involving Ethernet interface design and verification using UVM, ECG encoder design for healthcare applications, CRC generator/checker design and verification, reconfigurable LFSR design for BIST, and FPGA implementation of a basic processor and object tracking algorithm. His technical skills include Verilog, SystemVerilog, UVM, C, Java, MATLAB, and CAD tools from Cadence and Altera.

1. Suraj Ramaswamy
M.TECH VLSI Design, Vellore Institute of Technology
Email: surajr31@gmail.com
Contact: +91-8110019247/ +91-9029425316
Linkedin profile: in.linkedin.com/in/surajramaswamy31
OBJECTIVE
To work in a challenging position in the semiconductor industry to contribute and improve
my knowledge and skills as an RTL Design/Verification engineer.
PROJECTS UNDERTAKEN
 Design of Ethernet Management Interface Master Block and its verification using UVM
( Nov 2014 - Ongoing) - Final Semester Masters Thesis
MDC/MDIO is a 2-wire interface used by Ethernet Station Management Entity to configure as well as
read status from various PHY devices connected to it. There can be a maximum of 31 PHY devices
sharing the bidirectional MDIO serial line. The Design was coded using Verilog HDL. Learnt System
Verilog and UVM for verification. Currently developing the Test Bench for the verification of the
block.
 VLSI Implementation of Efficient Lossless ECG Encoder Design (June 2014-Nov 2014)
VLSI implementation of low power area efficient electrocardiogram (ECG) signal encoder which can
be used for wireless healthcare monitoring application. By studying ECG signals, simple adaptive
predictor was designed which chooses one among two type of predictors.
 Design and Verification of CRC Generator and Checker using Verilog HDL (May 2014)
The Cyclic Redundancy Check(CRC), is a technique for detecting errors in digital data. It is primarily
used in data transmission. The DUT was designed according to the specifications and was verified
using various test cases using Verilog HDL. Learned the complete concepts of verification and the
components used in verification.
 Design of reconfigurable 2-D LFSR for BIST in System-On-Chips (Jan 2014 –May 2014)
Studied in detail the working of LFSRs, 2-D LFSRs to design a reconfigurable version that uses same
hardware to produce different deterministic ordered test patterns which could be used to test various
blocks in an SOC.
 Multiplier using UCSLA adder (Jan 2014 - May 2014)
Design of an 8-bit, 16-bit and 32-bit multiplier using Uniform Carry Select Adder in Verilog HDL.
Synthesis using various low power and DFT constraints and Physical Design was completed within
the stipulated time.
 FPGA Based Object Tracking Algorithm Implementation (July 2013 – Nov 2013)
Object Tracking was achieved using Background Subtraction Technique. Parallelism in hardware
was achieved by splitting the 80 x 80 image into 12 parts of 20 x 20 each. Simulation performed
successfully on MATLAB.
 FPGA implementation of an enhanced processor (July 2013- Nov 2013)
Design of a 16 bit processor in Verilog HDL to perform basic MOV, ADD, SUB, AND, OR
operations. Synthesized in Quartus II. Successfully implemented on Altera DE1 EP2C20F484C7
Board.

2. TECHNICAL SKILLS
 Operating Systems: Linux, Windows XP, Windows 7, Windows 8.
 Programming Languages: C, Java, MATLAB.
 HDL/HVL: Verilog HDL, System Verilog
 Verification Methodologies: UVM
 Scripting Languages: Perl, TCL.
 Softwares Tools: Circuit Design – Cadence Virtuoso.
Simulation – Model Sim, Questa Sim, Cadence NC-SIM.
Synthesis – Quartus II for FPGA, Cadence RC for ASIC.
Cadence Encounter for Physical Design
PERSONAL SKILLS
Self-motivated, Enthusiastic about learning new skills, Quick learner, Creative, Artistic,
Team oriented, Punctual.
EDUCATIONAL CREDENTIALS
 M. Tech VLSI DESIGN, July 2013 - Ongoing
VIT University
CGPA – 8.18 (Till Semester 3)
 B.E Electronics and Telecommunication, June 2008 - May 2012
S S Jondhale College Of Engineering, Mumbai University
Agg. Percentage: 62.06%
 HSC- Maharashtra State Board, May 2008
Birla College of Science, Kalyan
Percentage: 60%
 SSC- Maharashtra State Board, May 2006
St. Therese Convent High School, Dombivli
Percentage: 87.60%
PROFESSIONAL CERTIFICATION
Web Component Development using Java Technologies by NIIT, December 2012
PERSONAL DETAILS
D.O.B: 31/01/1991
Languages known: English, Hindi, Marathi, Tamil, German.
Hobbies: Solving Puzzles, Sketching, Origami, Table tennis.
Contact Address: H-904, John Kennedy Block, Men’s Hostel,
VIT University, Vellore -632 014