Arun Raja Manjini is seeking a position in electrical engineering. He has a M.S. in electrical engineering from Texas A&M University and a B.Tech. in electronics and communication from Pondicherry University in India. His skills include Verilog, SystemVerilog, C/C++, Python, UVM methodology, and FPGA design. As a teaching assistant at Texas A&M, he assisted students in digital design courses and labs. Previously, he developed Python scripts to automate device configuration at Tata Consultancy Services. His academic projects include designing an SPI controller with Verilog and an asynchronous FIFO.

1. Arun Raja Manjini
arunraja08@gmail.com | (361) 228-0045 | Kingsville, TX | linkedin.com/in/arunrjm/ | github.com/aaronrjmanj
EDUCATION
M.S., in Electrical Engineering Texas A&M University, TX, US Aug 2019 – May 2021 GPA: 4/4
B.Tech., in Electronics & Communication Pondicherry University, India Aug 2014 – May 2018 GPA: 3.5/4
SKILLS
HDLs/HVLs/Programming: Verilog, SystemVerilog, C/C++, Python
Methodology: UVM (Universal Verification Methodology)
Bus Protocols: AMBA APB, SPI, I2C
EDA/CAD Tools: Mentor ModelSim, Synopsys VCS, Xilinx ISE, LTSpice, Pycharm | Text-editor: GVIM
Relevant Concepts: ASIC design flow, SoC Architecture, SV Assertions, Coverage, RTL integration, Python Scripting,
FPGA, Logic Synthesis, Computer Architecture
Certifications: Python Fundamentals, Verilog HDL for Design & Verification, CCNA
EXPERINECE
Teaching Assistant, Texas A&M University Jan 2020 – Present
 Assisting junior students in Digital Design course and helping them overcome their difficulties in the logic design.
 Highly motivated in improving the hardware skills and complex design solutions, responsible to conducting tests
and helping students in labs.
Assistant System Engineer, Tata Consultancy Services Ltd., India Sep 2018 – Aug 2019
 Developed and tested python scripts to detect configuration changes in the device (cisco switch/router) and
automated the steps associated it for periodic monitoring and updating.
 Gained knowledge in python regular expression & file handling, networking tools, pre & post install checks.
 Tools and Tech: Networking, PyCharm, Putty, FTP server, HTML, SQL, Agile teams
ACADEMIC PROJECTS
SPI Controller
 The Verilog design interfaces the processor and SPI slave together with the SPI controller to have an effective
serial data transfers.
 The processor initiates the data transfers using APB protocol and SPI controller uses special registers like MOSI &
MISO and a reference clock to communicate between master and the slave.
 Verilog code implements the controller behaviour and difference FSM stages in the data transfers.
 Completed the RTL simulation, debugged and verified the waveform for better performance.
Asynchronous FIFO
 Designed an 8x16 entry asynchronous First In First Out buffer for effective data transfers between the SPI
controller and the processor since they run on different clocks speed.
 Implemented a sequential logic to design a memory with write, read, empty and full conditions.
 Used Verilog HDL (RTL development) to design the FIFO and the test bench to give stimulus to the DUT.
Watch-Dog Timer verification using System Verilog
 Implemented a hardware timer that automatically generates a system reset if the main program hangs due to
hardware or software fault.
 Programming the register (timeout value) with APB interface using behavioural representation of Verilog code.
 To produce functional coverage in a testbench environment in SV for functional verification of watchdog timer
DUT - checker, reference model, BFM, generator, scoreboard and mailbox
CMOS - 8 bit ripple carry adder
 Designed a 8 bit CMOS NAND gate full adder using MAGIC tool for IBM 0.25 micro-meter technology
 Worked on the circuit design using metal, diffusion layer, contacts and used LTSPICE for delay estimation and
transient analysis
Finding max & min number in an array using assembly programing
 8-bit 8-MHz 68HCS12 CISC Microcontroller kit, analysed the architecture and different instruction set and
address modes of the MC and developed an assembly program to solve the problem