I Aspire to be a VLSI Physical Design Engineer, to work with maximum potential in a challenging and dynamic environment towards own professional as well as the organization's growth and thereby have extensive exposure in the semiconductor industry.

1. SEBIN PUTHIYATH
sebinputhiyath@gmail.com, Mob: 9447103196
Career Objective
I Aspire to be a VLSI Physical Design Engineer, to work with maximum potential in a
challenging and dynamic environment towards own professional as well as the
organization’s growth and thereby have extensive exposure in the semiconductor
industry.
Core Competency
 Understanding of ASIC Flow and hands-on experience in one of the APR tools
Synopsys IC Compiler.
 Designed optimal Floor Plans enabling a smooth work flow for the rest of the
project. Implementation of Power Plan to connect all pins of macros and standard
cells to the supply voltage without any floating pins or shapes and achieved
specified IR Drop limit
 Implementation of Placement plan with power aware and a zero congestion
ensuring good routablility.
 Ability to differentiate possible false paths from the set of real paths and constraints
which could fix them. STA - Analysed and understood Timing Reports.
 Wrote TCL scripts for common tasks to improve work efficiency.
 Analysed and understood Design constraints to specify OCV, PVT Corners, false
- paths, half cycle paths, CRPR etc.
 Familiar with scripting languages like Perl. Basic understanding of Linux
commands.
 Low Power Implementation based on UPF (automatic grid synthesis, level shifters
& isolation cells insertion).
 Quick learner and good communication skills.
Education Details
Advanced Diploma in ASIC Design - Physical Design, 2019
RV-VLSI Design Centre, Bangalore
Bachelor Degree in Electronics and Communication Engineering, 2018
Cochin University of Science and Technology, Kerala, with 69 %
Diploma in Electronics Engineering, 2014
Carmel Polytechnic College, Kerala, with 82.4 %
SSLC 2011
Little Flower Public School and Junior College, Kerala, with 90 %

2. Domain Specific Projects
RV-VLSI & Embedded Systems Design Centre, Bengaluru
Graduate Trainee Engineer Nov-2018 to May-2019
Analysing, Writing and debugging TCL Scripts
Description: Writing various TCL scripts to extract information from ICC data base,
understanding TCL scripts generated by IC Compiler, Writing TCL to various examples.
Tools: Tclsh, TCL Tutor, Linux OS
Challenges: Debugging TCL Scripts and writing TCL to design examples.
Floor planning & Power planning in 40nm technology
Description: Technology - 40nm, Macro count - 34, Standard cell count - 38887, Area -
4.2mm2, Supply - 1.1V, Clock frequency - 833MHz, Number of metal layers - 7, Power
Budget - 600mW, IR drop < 55 mV.
Tools: Synopsys IC Compiler
Challenges
 Initial difficulty in understanding the TCL code and manual placement of macros at
the periphery of the core based on data flow diagram.
 Placement blockages and optimal spacing is used in between macros and to avoid
congestion.
 Multiple iterations of adjusting the offset and number of power straps, pitch and
their width to meet the IR drop target.
 Ensuring the design to be free from DRC violations of floating pins and floating
shapes by aligning the macros and giving placement blockages.
Placement and Clock Tree Synthesis
Description: Optimized design with acceptable congestion and distributed power with
minimum timing.
DRC's and building clock tree with optimized clock skew.
Tools: Synopsys IC Compiler
Challenges
 Achieving congestion free placement to have good routability for DFT aware
placement.
 Iteratively changing Floor plan for congestion free Placement and understanding
the timing reports after each step of APR flow, different placement switches for
optimization.
 Understanding the tool behaviour while Clock tree building and optimization of
clock & data paths for fixing timing violations by balancing the skew.
 Understanding the reason for timing violation of violating paths and guiding the tool
to tackle it.

3. Analysis of Timing Reports (STA)
Description : Detailed analysis of timing constraints and reports especially of timing
paths which includes flip flop and latch based designs considering OCV, uncertainty,
CRPR, Clock skews and certain exceptions (multi cycle paths) honouring the constraints
file.
Tools: Synopsys PrimeTime, Synopsys IC Compiler
Challenges
 Proper understanding of basic concepts and terms related to STA was necessary
for accurate analysis of timing reports.
 A know-how of cell delays (input slews and loads), min & max derate factors, setup
time and hold values, MCMM Scenarios which are essential for analysing reports.
 Identification of paths in which timing exceptions like false path & multi cycle path
were to be given. GUI representation of the paths made this clear.
 Calculation of skew value to be loaded to make use of useful skew for fixing setup
and hold violations.
B.Tech Academic Project
Magnetic Spherical Balancing Robot
Description: The robot is a ground based holonomic robot that can instantaneously
move in any direction on the horizontal plane that makes them incredibly responsive.
Tools: Hardware used: ATmega328P, MPU6050. Software used: Arduino IDE
Challenges: We had to replace initial heavy shell with a fibre case which incredibly
reduced the overall weight and could be driven by the motor used. On the programming
side, gyroscope output interpretation was completely new to us and had to spend some
time.
PERSONAL DETAILS
Date of Birth : 06th June, 1995
Languages Known : English, Malayalam and Hindi
Hobbies : Reading, Getting aware of Technological Changes
LinkedIn Profile : linkedin.com/in/sebin-puthiyath-0a6738b0
DECLARATION
I hereby solemnly affirm that all details furnished above are true to the best of my
knowledge.
Date: 16/06/2019
Place: Bangalore SEBIN PUTHIYATH