VLSI+EMBEDDED

1. Name: Veerapandi M
No.146,balamurugan street,
Avadi,Chennai-54,
Phone: 9944721758
Email Id: veeera.mnm@gmail.com
__________________________________________________________________________________
Career Objective:
To pursue a career in an organization which can provide a challenging environment, scope for
creativity and innovative thinking, promotes learning and acquiring new skills and which will help me
to explore myself fully and realize my potential.
Work Experience: 2.0 Years
May 2014 – PRESENT
Digital Design Technician,
YaganamayayA Techsuite,Chennai
Technical Skills:
 C
 Vhdl &
 Verilog
 USB
 i2c bus
 VGA
 UART
 Testbench Verification.
 Embedded C(8051,ARM,arudino board)
 Water tank controller(ultrasonicsensor,Transistor,8051)
 Remote(R5) interfacing with 8051
 GSM(send/receive SMS,voice call) interface with arudino board
 GPS inetrfacing with arudino
 Bluetooth interface with arudino board
Tools Exposed:
 ModelSim
 Quartus-II
 Xilinx
 Arudino
 keil
 Network Simulator Ns2(Tcl).

2. Academic Qualifications:
 M.E(VLSI DESIGN),(77.8%) from VelTech Multi-Tech Engineering College,
Chennai, in 2013
 B.E (ECE), (67%) SVCET, Thiruvallur, Chennai, in 2011
 HSC with an aggregate of 89% in 2007
 SSLC with an aggregate of 90% in 2005
Academic Projects:
1)FPGA Based LCD Monitor.
-Real time video capture and image processing system will be designed on the FPGA
board using SW/HW design methods.
-It will capture an analog video signal from a camera process it and then display the
video in a real time mode. Video and text merging on FPGA.
2)Decision tree based multi pipeline architecture on for packet classification.
-Parallel pipeline architecture on FPGAs for multi-field packet classification. Packet
classification that support higher throughput, larger rule sets and more packet header
fields.
-Develop a framework to partition the rule set into multiple subsets each of which is
built into an optimized decision tree.
-Tree-to-pipeline mapping scheme is carefully designed to maximize the memory
utilization while sustaining high throughput. SRAM-based parallel pipeline architectures
(FPGA).
Projects handled:
1)Network Design for Power Minimization by Adaptive Gating.
-Develop a model of the clock gating network that allows us to reducing switching
power consumption.
-Approach to maximize clock disabling at the gate level, where the clock signal driving
a FF is disabled (gated) when the FF state is not subject to a change in the next clock
cycle.
-Extra logic and interconnects are required to generate the clock enabling signals and the
resulting area and power overheads must be considered.
-Clock gating To Reduce the Unwanted Clock Cycles.

3. 2)Energy Efficient Decoder Architecture Wireless Sensor Network.
-Achieves low area and low energy consumption by decomposing the LUT log bjcr
architecture into its acs operation- index-Parallel prefix adder used.
3)Multipliers Design for 4 – Point FFT Architecture.
-Designed high speed multipliers that can be used to design the Radix 4 point FFT
architectures. Serial adder deisnged for addition by using adaptive clock gating
techniques.
4)2D FIR filter –distributed arithmetic algorithm.
-Memory Reduction for Power-Efficient Realization of 2-D Finite Impulse Response
Filters.
-Here Repeated samples are removed so the requirement of memory also reduced.
-Shift registers blocks and distributed arithmetic algorithms are used .shift register – To
store input samples.
5)Design a UART interface with USB(PS2) and Lcd Display using Vhdl/Verilog and test it in
an altera DE1 board.
-UART protocol used in serial communication specifically for the data exchange
between the external devices and UART for short distance.
-Input device is keyboard.
-Transmit the input characters over the UART to PC.
-Received the characters over the UART from the external devices will be shown by Lcd
display.
6)Design Pong Game on VGA monitor using Vhdl/Verilog and Altera DE1 board
- Design a pong game and display it on a monitor.
-Carry on the FPGA and will send the video to the monitor via VGA interface.
-Synchronization module
-Image generation module
-Synchronization module produce the control signals for the objects shown on the
monitor.

4. Personal Details:
Name : Veerapandi M
Father’s Name : Muthu Veeraperumal K
Date of Birth : 02-04-1990
Nationality : Indian
Gender : Male
Marital Status : Single
Declaration:
I hereby declare that all the information provided above is correct to my knowledge.
(VEERAPANDI.M)