SlideShare a Scribd company logo
Powered by Nanochip Solutions
Powered by Nanochip Solutions
Ankita Gloria Kerketta
ankitagloria@gmail.com, 8867558956
Bangalore-560032, Karnataka
Career Objective
Professional Full Custom Engineer looking for opportunities to learn ,contribute and grow in
the field of VLSI.
Core Competancy
Exposure to blocks like OP-AMP, SRAM and its working.
Knowledge of ASIC and Full Custom Flow.
Understand device operation and characterization.
Ability to identify and solve DRC, LVS and Compatibility rules.
Understanding of layout dependent effects like Antenna Effect, Latchup, EM, ESD and DFM
considerations, Dummy Poly.
Familiar with submicron effects like Optical Proximity Correction, LOD, Proximity Effect and
Shallow Trench Isolation.
Exposure to working in different technology and with different types of blocks.
Education Details
PG Diploma in Advanced Diploma in ASIC Design - Full Custom 2016
RV-VLSI Design Center
Bachelor Degree in Electrical and Electronics 2015
RSR Rungta College Of Engg. & Tech.., with 73.3 %
PUC / 12th 2011
De Paul Hr. Sec. School, Singrauli(M.P.), with 74 %
SSLC 2009
De Paul Hr. Sec. School,Singrauli(M.P.), with 75.6 %
Powered by Nanochip Solutions
Powered by Nanochip Solutions
Domain Specific Project
RV VLSI Design Center
RV-VLSI Design Center Feb-2016 to Apr-2016
32*32 SRAM Memory Cell
Description
32*32 SRAM Memory Cell made up of different blocks such us Sense amplifier, Control Block,
Dout,Din etc. For each block depending upon area constraint and its functionality we have
done floorplanning . And for analog block we have done matching.
Tools
IC Studio, Pyxis Circuit and Layout Editor(Mentor Graphics) Calibre DRC and LVS
Challenges
Source-source sharing, drain-drain sharing. Optimisation of Layout by diffusion sharing.
Floorplanning the layout including matching techniques in order to obtain compact size.
Abutting each block in grid .Avoid Soft check error. Avoid routing over active area
.Understanding and fixing the discrepencies like Shorts, Opens, missing Instances
Designing of Analog Device i.e Sense Amplifier.
RV VLSI Design Center
RV-VLSI Design Center Nov-2015 to Nov-2015
Two stage OP-AMP in 180nm technology
Description
As Two stage OPAMP is a analog block we have to do matching and floorpanninhg. For making
block in optimise way and symmetric we have add dummy transistors and also for S-S and D-D
sharing.
Tools
IC Studio, Pyxis Circuit and Layout Editor (Mentor Graphics) Calibre DRC and LVS
Challenges
Avoid routing over active Poly. Understanding and fixing the discrepencies like Shorts, Opens,
missing Instances
Floorplanning layout including matching techniques in order to obtain compact size.
Source- Source and Drain-Drain sharing.
Powered by Nanochip Solutions
Powered by Nanochip Solutions
RV VLSI Design Center
RV-VLSI Design Center Nov-2015 to Nov-2015
Layout of 28nm Standard Cell Library Design
Description
In this we have to design a standard cell such us AND, NAND,NOR,OR,NOT,MUX etc. There is
a fixed height constraint for the standard cell. we have to do proper floorplanning for each
cell.
Tools
IC Studio, Pyxis Circuit and Layout Editor (Mentor Graphics) Calibre DRC and LVS,
Challenges
Reducing parasitics and S-S or D-D sharing. Understanding and fixing the discrepencies like
Shorts, Opens, missing Instances
Fitting the layout in the given PR Boundary (for the fixed height 9 tracks).
Optimisation of Layout by diffusion sharing and placing metal pins on grids
RV VLSI Design Center
RV-VLSI Design Center Dec-2015 to Dec-2015
Layout of 90nm Standard Cell Library Design
Description
In this we have to design a standard cell such us AND, NAND,NOR,OR,NOT,MUX etc. There is
a fixed height constraint for the standard cell. we have to do proper floorplanning for each.
Tools
IC Studio, Pyxis Circuit and Layout Editor (Mentor Graphics) Calibre DRC and LVS.
Challenges
Reducing parasitics.S-S or D-D sharing.
Fitting the layout in the given PR Boundary.
Optimization of Layout by diffusion sharing and placing metal pins on grids.
Understanding and fixing the discrepencies like Shorts, Opens, missing Instances
Powered by Nanochip Solutions
Powered by Nanochip Solutions
B.E / B.Tech Academic Project
RSR Rungta College Of Engg. & Tech..
To design Rolling Speed Breaker to generate Electricity
Description
Project involves converting kinetic energy to mechanical energy then to electrical energy
which includes rolling breakers connected with Dynamo and this is connected with step-up
transformer then converted electric energy is stored in Battery and last connected to inverter.
Tools
PCB board
Challenges
To reduce leakage current Avoid over heat to device connected and Battery should not leak.

More Related Content

Similar to Ankita Gloria Kerketta (3)

My profile
My profileMy profile
My profiledhruv_63
 
NEEL SHAH RESUME1RF
NEEL SHAH RESUME1RF  NEEL SHAH RESUME1RF
NEEL SHAH RESUME1RF Neel Shah
 
Ramesh resume
Ramesh resumeRamesh resume
Ramesh resume
Ramesh Bankapalli
 
Actively seeking for an opportunity in VLSI domain
Actively seeking for an opportunity in VLSI domainActively seeking for an opportunity in VLSI domain
Actively seeking for an opportunity in VLSI domain
msnadaf
 
Neeraj Resume
Neeraj ResumeNeeraj Resume
Neeraj Resume
Neeraj Vishnu
 
JD Role Type Slides - 12.2022.pdf
JD Role Type Slides - 12.2022.pdfJD Role Type Slides - 12.2022.pdf
JD Role Type Slides - 12.2022.pdf
PallavBishi1
 
William Check Resume
William Check ResumeWilliam Check Resume
William Check ResumeBill Check
 
Ronen Sarig Resume
Ronen Sarig ResumeRonen Sarig Resume
Ronen Sarig ResumeRonen Sarig
 
Ananthprofilepln
AnanthprofileplnAnanthprofilepln
Ananthprofileplnananthch
 
resume_aditya_gujja_03
resume_aditya_gujja_03resume_aditya_gujja_03
resume_aditya_gujja_03Aditya Gujja
 

Similar to Ankita Gloria Kerketta (3) (20)

Pavanteja_CV
Pavanteja_CVPavanteja_CV
Pavanteja_CV
 
MELDIYA THOMAS (2)
MELDIYA THOMAS (2)MELDIYA THOMAS (2)
MELDIYA THOMAS (2)
 
My profile
My profileMy profile
My profile
 
NEEL SHAH RESUME1RF
NEEL SHAH RESUME1RF  NEEL SHAH RESUME1RF
NEEL SHAH RESUME1RF
 
Resume150721
Resume150721Resume150721
Resume150721
 
VIJAYALAKSHMI V
VIJAYALAKSHMI VVIJAYALAKSHMI V
VIJAYALAKSHMI V
 
Chintan Varia-MSEE
Chintan Varia-MSEEChintan Varia-MSEE
Chintan Varia-MSEE
 
Ramesh resume
Ramesh resumeRamesh resume
Ramesh resume
 
Darrell_Hubbard_rs
Darrell_Hubbard_rsDarrell_Hubbard_rs
Darrell_Hubbard_rs
 
Actively seeking for an opportunity in VLSI domain
Actively seeking for an opportunity in VLSI domainActively seeking for an opportunity in VLSI domain
Actively seeking for an opportunity in VLSI domain
 
Neeraj Resume
Neeraj ResumeNeeraj Resume
Neeraj Resume
 
JD Role Type Slides - 12.2022.pdf
JD Role Type Slides - 12.2022.pdfJD Role Type Slides - 12.2022.pdf
JD Role Type Slides - 12.2022.pdf
 
William Check Resume
William Check ResumeWilliam Check Resume
William Check Resume
 
Ronen Sarig Resume
Ronen Sarig ResumeRonen Sarig Resume
Ronen Sarig Resume
 
Ananthprofilepln
AnanthprofileplnAnanthprofilepln
Ananthprofilepln
 
Resume srishail upadhye
Resume srishail upadhyeResume srishail upadhye
Resume srishail upadhye
 
NISHANT_PATHAK_RESUME
NISHANT_PATHAK_RESUMENISHANT_PATHAK_RESUME
NISHANT_PATHAK_RESUME
 
resume_aditya_gujja_03
resume_aditya_gujja_03resume_aditya_gujja_03
resume_aditya_gujja_03
 
Himanshu Resume
Himanshu ResumeHimanshu Resume
Himanshu Resume
 
Wojciech Stanislawski Resume v2016
Wojciech Stanislawski Resume v2016Wojciech Stanislawski Resume v2016
Wojciech Stanislawski Resume v2016
 

Ankita Gloria Kerketta (3)

  • 1. Powered by Nanochip Solutions Powered by Nanochip Solutions Ankita Gloria Kerketta ankitagloria@gmail.com, 8867558956 Bangalore-560032, Karnataka Career Objective Professional Full Custom Engineer looking for opportunities to learn ,contribute and grow in the field of VLSI. Core Competancy Exposure to blocks like OP-AMP, SRAM and its working. Knowledge of ASIC and Full Custom Flow. Understand device operation and characterization. Ability to identify and solve DRC, LVS and Compatibility rules. Understanding of layout dependent effects like Antenna Effect, Latchup, EM, ESD and DFM considerations, Dummy Poly. Familiar with submicron effects like Optical Proximity Correction, LOD, Proximity Effect and Shallow Trench Isolation. Exposure to working in different technology and with different types of blocks. Education Details PG Diploma in Advanced Diploma in ASIC Design - Full Custom 2016 RV-VLSI Design Center Bachelor Degree in Electrical and Electronics 2015 RSR Rungta College Of Engg. & Tech.., with 73.3 % PUC / 12th 2011 De Paul Hr. Sec. School, Singrauli(M.P.), with 74 % SSLC 2009 De Paul Hr. Sec. School,Singrauli(M.P.), with 75.6 %
  • 2. Powered by Nanochip Solutions Powered by Nanochip Solutions Domain Specific Project RV VLSI Design Center RV-VLSI Design Center Feb-2016 to Apr-2016 32*32 SRAM Memory Cell Description 32*32 SRAM Memory Cell made up of different blocks such us Sense amplifier, Control Block, Dout,Din etc. For each block depending upon area constraint and its functionality we have done floorplanning . And for analog block we have done matching. Tools IC Studio, Pyxis Circuit and Layout Editor(Mentor Graphics) Calibre DRC and LVS Challenges Source-source sharing, drain-drain sharing. Optimisation of Layout by diffusion sharing. Floorplanning the layout including matching techniques in order to obtain compact size. Abutting each block in grid .Avoid Soft check error. Avoid routing over active area .Understanding and fixing the discrepencies like Shorts, Opens, missing Instances Designing of Analog Device i.e Sense Amplifier. RV VLSI Design Center RV-VLSI Design Center Nov-2015 to Nov-2015 Two stage OP-AMP in 180nm technology Description As Two stage OPAMP is a analog block we have to do matching and floorpanninhg. For making block in optimise way and symmetric we have add dummy transistors and also for S-S and D-D sharing. Tools IC Studio, Pyxis Circuit and Layout Editor (Mentor Graphics) Calibre DRC and LVS Challenges Avoid routing over active Poly. Understanding and fixing the discrepencies like Shorts, Opens, missing Instances Floorplanning layout including matching techniques in order to obtain compact size. Source- Source and Drain-Drain sharing.
  • 3. Powered by Nanochip Solutions Powered by Nanochip Solutions RV VLSI Design Center RV-VLSI Design Center Nov-2015 to Nov-2015 Layout of 28nm Standard Cell Library Design Description In this we have to design a standard cell such us AND, NAND,NOR,OR,NOT,MUX etc. There is a fixed height constraint for the standard cell. we have to do proper floorplanning for each cell. Tools IC Studio, Pyxis Circuit and Layout Editor (Mentor Graphics) Calibre DRC and LVS, Challenges Reducing parasitics and S-S or D-D sharing. Understanding and fixing the discrepencies like Shorts, Opens, missing Instances Fitting the layout in the given PR Boundary (for the fixed height 9 tracks). Optimisation of Layout by diffusion sharing and placing metal pins on grids RV VLSI Design Center RV-VLSI Design Center Dec-2015 to Dec-2015 Layout of 90nm Standard Cell Library Design Description In this we have to design a standard cell such us AND, NAND,NOR,OR,NOT,MUX etc. There is a fixed height constraint for the standard cell. we have to do proper floorplanning for each. Tools IC Studio, Pyxis Circuit and Layout Editor (Mentor Graphics) Calibre DRC and LVS. Challenges Reducing parasitics.S-S or D-D sharing. Fitting the layout in the given PR Boundary. Optimization of Layout by diffusion sharing and placing metal pins on grids. Understanding and fixing the discrepencies like Shorts, Opens, missing Instances
  • 4. Powered by Nanochip Solutions Powered by Nanochip Solutions B.E / B.Tech Academic Project RSR Rungta College Of Engg. & Tech.. To design Rolling Speed Breaker to generate Electricity Description Project involves converting kinetic energy to mechanical energy then to electrical energy which includes rolling breakers connected with Dynamo and this is connected with step-up transformer then converted electric energy is stored in Battery and last connected to inverter. Tools PCB board Challenges To reduce leakage current Avoid over heat to device connected and Battery should not leak.