This document contains the source code and test bench for a RAM module. The source code defines an entity for a RAM with an 8-bit address and 8-bit data ports, as well as write enable, chip select, and output enable ports. The architecture defines an 8-bit signal to store the 256 memory locations. The test bench instantiates the RAM entity and applies a stimulus of writing 8 bytes of data to addresses and then reading back the values.

1. RAM SOURCE CODE & TEST BENCH
--SOURCE CODE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity ram is
port (address: in std_logic_vector(7 downto 0);
data: inout std_logic_vector(7 downto 0);
WE, CS, OE: in std_logic);
end entity ram;
architecture simple_ram of ram is
type ram_type is array (0 to 255) of std_logic_vector(7 downto 0);
signal ram1: ram_type:= (others => (others => '0'));
begin
ram1(conv_integer(address)) <= data when ((CS='0' and WE='0') and OE='1');
data <= ram1(conv_integer(address)) when ((CS='0' and WE='1') and OE='0') else
(others=>'Z');
end simple_ram;
--TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Ram_TB IS
END Ram_TB;
ARCHITECTURE behavior OF Ram_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ram
PORT(
address : IN std_logic_vector(7 downto 0);
data : INOUT std_logic_vector(7 downto 0);
WE : IN std_logic;
CS : IN std_logic;
OE : IN std_logic
);
END COMPONENT;
--Inputs
signal address : std_logic_vector(7 downto 0) := (others => '0');
signal WE : std_logic := '0';
signal CS : std_logic := '0';
signal OE : std_logic := '0';
--Outputs
signal data : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below
----with
-- appropriate port name

2. BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ram PORT MAP (
address => address,
data => data,
WE => WE,
CS => CS,
OE => OE
);
-- Clock process definitions
stim_proc: process
begin
-- hold reset state for 100 ns.
WE<= '0';
OE<= '1';
Address<="00000001";
Data<= "00000001";wait for 10 ns;
Address<="00000010";
Data<= "00000010";wait for 10 ns;
Address<="00000100";
Data<= "00000100";wait for 10 ns;
Address<="00001000";
Data<= "00001000";wait for 10 ns;
Address<="00010000";
Data<= "00010000";wait for 10 ns;
Address<="00100000";
Data<= "00100000";wait for 10 ns;
Address<="01000000";
Data<= "01000000";wait for 10 ns;
Address<="10000000";
Data<= "10000000";wait for 10 ns;
WE<= '1';
OE<= '0';
Data<= "ZZZZZZZZ";
Address<="00000001";wait for 10 ns;
Address<="00000010";wait for 10 ns;
Address<="00000100";wait for 10 ns;
Address<="00001000";wait for 10 ns;
Address<="00010000";wait for 10 ns;
Address<="00100000";wait for 10 ns;
Address<="01000000";wait for 10 ns;
Address<="10000000";wait for 10 ns;
Address<="00000000";wait for 10 ns;
end process;
END;