Watching And Manipulating Your Network TrafficJosiah Ritchie
This is an intro presentation to using the powerful tools for provided for linux in the area of networking. These are command line only tools because in a good network firewall, you won't have the option of graphical tools.
Slides from my presentation on ARM Shellcode at #44CON 2018, London.
In this talk, we explore ARM egghunting and "Quantum Leap" code - polyglot ARM shellcode. A bonus side effect of this talk will be creating headaches for those who like to defend agaisnt attacks using age old signature based techniques.
HackLU 2018 Make ARM Shellcode Great AgainSaumil Shah
Compared to x86, ARM shellcode has made little progress. The x86 hardware is largely homogenous. ARM, however, has several versions and variants across devices today. There are several constraints and subtleties involved in writing production quality ARM shellcode which works on modern ARM hardware, not just on QEMU emulators.
In this talk, we shall explore issues such as overcoming cache coherency, reliable polymorphic shellcode, ARM egghunting and last but not the least, polyglot ARM shellcode. A bonus side effect of this talk will be creating headaches for those who like to defend agaisnt attacks using age old signature based techniques.
Depuis FreeBSD 8.0, le SSP est activé automatique pour la compilation de l'OS. Cette option de GCC développée au départ par IBM, permet d'ajouter des mécanismes de protection face aux buffer overflows. La présentation sera accompagnée de sources C et d'étude de la mémoire via GDB. La présentation commencera par le fonctionnement du SSP (via 3 aspects), suivi de l'implémentation sous FreeBSD et son Linux pour finir par l'exploitation dans certains cas de figure.
Watching And Manipulating Your Network TrafficJosiah Ritchie
This is an intro presentation to using the powerful tools for provided for linux in the area of networking. These are command line only tools because in a good network firewall, you won't have the option of graphical tools.
Slides from my presentation on ARM Shellcode at #44CON 2018, London.
In this talk, we explore ARM egghunting and "Quantum Leap" code - polyglot ARM shellcode. A bonus side effect of this talk will be creating headaches for those who like to defend agaisnt attacks using age old signature based techniques.
HackLU 2018 Make ARM Shellcode Great AgainSaumil Shah
Compared to x86, ARM shellcode has made little progress. The x86 hardware is largely homogenous. ARM, however, has several versions and variants across devices today. There are several constraints and subtleties involved in writing production quality ARM shellcode which works on modern ARM hardware, not just on QEMU emulators.
In this talk, we shall explore issues such as overcoming cache coherency, reliable polymorphic shellcode, ARM egghunting and last but not the least, polyglot ARM shellcode. A bonus side effect of this talk will be creating headaches for those who like to defend agaisnt attacks using age old signature based techniques.
Depuis FreeBSD 8.0, le SSP est activé automatique pour la compilation de l'OS. Cette option de GCC développée au départ par IBM, permet d'ajouter des mécanismes de protection face aux buffer overflows. La présentation sera accompagnée de sources C et d'étude de la mémoire via GDB. La présentation commencera par le fonctionnement du SSP (via 3 aspects), suivi de l'implémentation sous FreeBSD et son Linux pour finir par l'exploitation dans certains cas de figure.
Key recovery attacks against commercial white-box cryptography implementation...CODE BLUE
White-box cryptography aims to protect cryptographic primitives and keys in software implementations even when the adversary has a full control to the execution environment and an access to the implementation of the cryptographic algorithm. It combines mathematical transformation with obfuscation techniques so it’s not just obfuscation on a data and a code level but actually algorithmic obfuscation.
In the white-box implementation, cryptographic keys are mathematically transformed so that never revealed in a plain form, even during execution of cryptographic algorithms. With such security in the place, it becomes extremely difficult for attackers to locate, modify, and extract the cryptographic keys. Although all current academic white-box implementations have been practically broken by various attacks including table-decomposition, power analysis attack, and fault injection attacks, There are no published reports of successful attacks against commercial white-box implementations to date. When I have assessed Commercial white box implementations to check if they were vulnerable to previous attacks, I found out that previous attacks failed to retrieve a secret key protected with the commercial white-box implementation. Consequently, I modified side channel attacks to be available in academic literature and succeeded in retrieving a secret key protected with the commercial white-box cryptography implementation. This is the first report that succeeded to recover secret key protected with commercial white-box implementation to the best of my knowledge in this industry. In this talk, I would like to share how to recover the key protected with commercial white-box implementation and present security guides on applying white-box cryptography to services more securely.
Make ARM Shellcode Great Again - HITB2018PEKSaumil Shah
Compared to x86, ARM shellcode has made little progress. The x86 hardware is largely homogenous. ARM, however, has several versions and variants across devices today. There are several constraints and subtleties involved in writing production quality ARM shellcode which works on modern ARM hardware, not just on QEMU emulators.
In this talk, we shall explore issues such as overcoming cache coherency, reliable polymorphic shellcode, ARM egghunting and last but not the least, polyglot ARM shellcode. A bonus side effect of this talk will be creating headaches for those who like to defend agaisnt attacks using age old signature based techniques
Kernel Recipes 2016 - Why you need a test strategy for your kernel developmentAnne Nicolas
Testing is important. That’s a well known fact that very few developers will dispute. Why is then so little kernel code covered by a clear testing strategy ? Through real stories about test plans (or the lack thereof), this talk will convince you that none of your excuses for not having a test strategy are valid. You will learn how various parts of the Linux kernel have approached testing and how you can benefit from their experience. The talk will use the V4L2 subsystem to demonstrate the use of test tools, but will be applicable to kernel development in general.
Laurent Pinchart
Key recovery attacks against commercial white-box cryptography implementation...CODE BLUE
White-box cryptography aims to protect cryptographic primitives and keys in software implementations even when the adversary has a full control to the execution environment and an access to the implementation of the cryptographic algorithm. It combines mathematical transformation with obfuscation techniques so it’s not just obfuscation on a data and a code level but actually algorithmic obfuscation.
In the white-box implementation, cryptographic keys are mathematically transformed so that never revealed in a plain form, even during execution of cryptographic algorithms. With such security in the place, it becomes extremely difficult for attackers to locate, modify, and extract the cryptographic keys. Although all current academic white-box implementations have been practically broken by various attacks including table-decomposition, power analysis attack, and fault injection attacks, There are no published reports of successful attacks against commercial white-box implementations to date. When I have assessed Commercial white box implementations to check if they were vulnerable to previous attacks, I found out that previous attacks failed to retrieve a secret key protected with the commercial white-box implementation. Consequently, I modified side channel attacks to be available in academic literature and succeeded in retrieving a secret key protected with the commercial white-box cryptography implementation. This is the first report that succeeded to recover secret key protected with commercial white-box implementation to the best of my knowledge in this industry. In this talk, I would like to share how to recover the key protected with commercial white-box implementation and present security guides on applying white-box cryptography to services more securely.
Make ARM Shellcode Great Again - HITB2018PEKSaumil Shah
Compared to x86, ARM shellcode has made little progress. The x86 hardware is largely homogenous. ARM, however, has several versions and variants across devices today. There are several constraints and subtleties involved in writing production quality ARM shellcode which works on modern ARM hardware, not just on QEMU emulators.
In this talk, we shall explore issues such as overcoming cache coherency, reliable polymorphic shellcode, ARM egghunting and last but not the least, polyglot ARM shellcode. A bonus side effect of this talk will be creating headaches for those who like to defend agaisnt attacks using age old signature based techniques
Kernel Recipes 2016 - Why you need a test strategy for your kernel developmentAnne Nicolas
Testing is important. That’s a well known fact that very few developers will dispute. Why is then so little kernel code covered by a clear testing strategy ? Through real stories about test plans (or the lack thereof), this talk will convince you that none of your excuses for not having a test strategy are valid. You will learn how various parts of the Linux kernel have approached testing and how you can benefit from their experience. The talk will use the V4L2 subsystem to demonstrate the use of test tools, but will be applicable to kernel development in general.
Laurent Pinchart
When your whole system is unresponsive, how to investigate on this failure ?
We'll see how to get a memory dump for offline analysis with kdump system.
Then how to analyze it with crash utility.
And finally, how to use crash on a running system to modify the kernel memory (at your own risks !)
JS Fest 2018. Володимир Шиманський. Запуск двіжка JS на мікроконтролеріJSFestUA
JavaScript - усюди! Тільки нещодавно запускав один і той самий JS код в Browser, Node.js, та React Native, як уже новий виклик - Embedded системи… Спокійно, JS справиться! На цій доповіді ви дізнаєтесь, які двіжки JS працюють в дуже обмежених середовищах, хто і як це використовує в продакшні та наскільки весело розробляти софт під всякі залізяки на JS.
[Спойлер] Якщо все вийде, спробуємо відтворити мелодію Mario на звичайному Bluetooth-брелку для ключів :)
Hadoop World 2011: Leveraging Hadoop for Legacy Systems - Mathias Herberts, C...Cloudera, Inc.
Since many companies in the financial sector still rely on legacy systems for its daily operations, Hadoop can only be truly useful in those environments if it can fit nicely among COBOL, VSAM, MVS and other legacy technologies. In this session, we will detail how Crédit Mutuel Arkéa solved this challenge and successfully mixed the mainframe and Hadoop.
How do I draw the Labview code for pneumatic cylinder(air pistion). .pdffootstatus
How do I draw the Labview code for pneumatic cylinder(air pistion). (Start with banana-plug>>
Pneumatic cylinder(air pistion) moves back and forward certain times or certain seconds>> end)
Solution
#include
#include
#include
#include
#include \"RTClib.h\"
#define LOG_INTERVAL 1 // milsec betweens entries
#define SYNC_INTERVAL 100
uint32_t syncTime =0;
RTC_DS1307 RTC; // Real Time Clock
// On the Ethernet Shield, CS is pin 4. Note that even if it\'s not
// used as the CS pin, the hardware CS pin (10 on most Arduino boards,
// 53 on the Mega) must be left as an output or the SD library
// functions will not work.
const int chipSelect = 10;
//switch inputs and variables
const int kPinReedSwitch1 = 22;
const int kPinReedSwitch2 = 24;
const int relayPin = 26;
int strokedown = 0;
int inc = 0;
int precountA =0;
int precountB = 0;
int count = 0;
int runcycles = 20;
int reset = 0;
int initial = 1;
int start =1;
int LinearPot1Pin = A0; // select the input pin for the potentiometer
float sensorValue = 0.0; // variable to store the value coming from the sensor
int MC_travel = 0;
int on =0;
//logging file
File logfile;
LiquidCrystal lcd(7, 8, 9, 10, 11, 12);
void error(char *str)
{
Serial.print(\"error: \");
Serial.println(str);
while(1);
}
void setup()
{
// Open serial communications and wait for port to open:
Serial.begin(9600);
while (!Serial) {
; // wait for serial port to connect. Needed for Leonardo only
}
// Input pins for Arduino
pinMode(kPinReedSwitch1, INPUT_PULLUP);
pinMode(kPinReedSwitch2, INPUT_PULLUP);
pinMode(relayPin, OUTPUT);
Serial.print(\"Initializing SD card...\");
// make sure that the default chip select pin is set to
// output, even if you don\'t use it:
pinMode(53, OUTPUT);
// see if the card is present and can be initialized:
if (!SD.begin(10,11,12,13)) {
Serial.println(\"Card failed, or not present\");
// don\'t do anything more:
return;
}
Serial.println(\"card initialized.\");
// creating a new file for data logger
char filename[] = \"LOGGER00.CSV\";
for (uint8_t i = 0; i < 100; i++){
filename[6] = i/10 + \'0\';
filename[7] = i%10 + \'0\';
if(! SD.exists(filename)){
logfile = SD.open(filename, FILE_WRITE);
break;
}
}
if (!logfile) {
error(\"couldnt create file\");
}
Serial.print(\"Logging to:\");
Serial.println(filename);
logfile.println(\"MC Travel\");
// LCD initialization
lcd.begin(20,4);
lcd.clear();
lcd.setCursor(0,0);
lcd.print(\"Count: \");
lcd.setCursor(0,1);
lcd.print(\"MC Travel: in\");
}
void loop()
{
for(int i = 1; i < 2; i++ )
//an initialization routine just to get cylinder to \"home\"
//although should never really be away from home
{
digitalWrite(relayPin, HIGH);
delay(200);
digitalWrite(relayPin, LOW);
delay (2000);
}
while( count <= runcycles){
if( start ==1 && digitalRead(kPinReedSwitch1)==HIGH){
digitalWrite(relayPin, HIGH);
}
else if (digitalRead(kPinReedSwitch1) == LOW)
// turns on relay when reed switch A is triggered
// Logic reversed because of pullup resistors
{
strokedown = 1;
precountA =1;
start=0;// .
seccomp is a computer security facility in the Linux kernel, pledge is a similar security facility in the OpenBSD kernel. In this presentation Giovanni Bechis will review the development story and progress of both kernel interfaces and will analyze the main differences. There will be some examples of implementations of security patches made for some important open source projects.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Le nuove frontiere dell'AI nell'RPA con UiPath Autopilot™UiPathCommunity
In questo evento online gratuito, organizzato dalla Community Italiana di UiPath, potrai esplorare le nuove funzionalità di Autopilot, il tool che integra l'Intelligenza Artificiale nei processi di sviluppo e utilizzo delle Automazioni.
📕 Vedremo insieme alcuni esempi dell'utilizzo di Autopilot in diversi tool della Suite UiPath:
Autopilot per Studio Web
Autopilot per Studio
Autopilot per Apps
Clipboard AI
GenAI applicata alla Document Understanding
👨🏫👨💻 Speakers:
Stefano Negro, UiPath MVPx3, RPA Tech Lead @ BSP Consultant
Flavio Martinelli, UiPath MVP 2023, Technical Account Manager @UiPath
Andrei Tasca, RPA Solutions Team Lead @NTT Data
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Pushing the limits of ePRTC: 100ns holdover for 100 daysAdtran
At WSTS 2024, Alon Stern explored the topic of parametric holdover and explained how recent research findings can be implemented in real-world PNT networks to achieve 100 nanoseconds of accuracy for up to 100 days.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Climate Impact of Software Testing at Nordic Testing DaysKari Kakkonen
My slides at Nordic Testing Days 6.6.2024
Climate impact / sustainability of software testing discussed on the talk. ICT and testing must carry their part of global responsibility to help with the climat warming. We can minimize the carbon footprint but we can also have a carbon handprint, a positive impact on the climate. Quality characteristics can be added with sustainability, and then measured continuously. Test environments can be used less, and in smaller scale and on demand. Test techniques can be used in optimizing or minimizing number of tests. Test automation can be used to speed up testing.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
9. C:FPGAdv52LibrariesSsrc@mult_8@r@t@l.vhd 12/30/11 13:55:20
-- hds header_start
--
-- VHDL Architecture S.Mult_8.RTL
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 14:09:52 11/16/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Mult_8 IS
-- Declarations
PORT ( x,y : IN STD_Logic_Vector (7 Downto 0);
z : OUT STD_Logic_Vector (15 Downto 0));
END Mult_8 ;
-- hds interface_end
ARCHITECTURE RTL OF Mult_8 IS
Signal p1: unsigned (7 Downto 0);
Signal p2: unsigned (8 Downto 0);
Signal p3: unsigned (9 Downto 0);
Signal p4: unsigned (10 Downto 0);
Signal p5: unsigned (11 Downto 0);
Signal p6: unsigned (12 Downto 0);
Signal p7: unsigned (13 Downto 0);
Signal p8: unsigned (14 Downto 0);
Signal pp1: unsigned (9 Downto 0);
Signal pp2: unsigned (11 Downto 0);
Signal pp3: unsigned (13 Downto 0);
Signal pp4: unsigned (15 Downto 0);
Signal ppp1: unsigned (11 Downto 0);
Signal ppp2: unsigned (15 Downto 0);
Signal pppp1: unsigned (15 Downto 0);
BEGIN
p1 <= unsigned (x) when y(0) = '1' else (others => '0');
p2 <= unsigned ( x & '0') when y(1) = '1' else (others => '0');
p3 <= unsigned ( x & "00") when y(2) = '1' else (others => '0');
p4 <= unsigned ( x & "000") when y(3) = '1' else (others => '0');
p5 <= unsigned ( x & "0000") when y(4) = '1' else (others => '0');
p6 <= unsigned ( x & "00000") when y(5) = '1' else (others => '0');
p7 <= unsigned ( x & "000000") when y(6) = '1' else (others => '0');
p8 <= unsigned ( x & "0000000") when y(7) = '1' else (others => '0');
pp1 <= ("00" & p1) + ('0' & p2);
pp2 <= ("00" & p3) + ('0' & p4);
pp3 <= ("00" & p5) + ('0' & p6);
pp4 <= ("00" & p7) + ('0' & p8);
ppp1 <= ("00" & pp1) + pp2;
ppp2 <= ("00" & pp3) + pp4;
pppp1 <= ("0000" & ppp1) + ppp2;
z <= STD_Logic_Vector(pppp1);
END RTL;
Page: 1
10. Mult 8.8 Simulation Code
force -freeze sim:/mult_8/x 01100100 0
force -freeze sim:/mult_8/y 00001100 0
add wave sim:/mult_8/*
run
run
run
run
run
run
Page 1
13. C:FPGAdv52LibrariesSsrc@r@a@m_128_8rtl.vhd 12/30/11 12:10:54
-- hds header_start
--
-- VHDL Architecture S.RAM_128_8.rtl
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 11:42:32 12/30/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY RAM_128_8 IS
-- Declarations
PORT (din: IN STD_Logic_Vector (7 downto 0);
dout: OUT STD_Logic_Vector (7 downto 0);
addr: IN STD_Logic_Vector ( 6 downto 0);
wr,clk: IN STD_Logic);
END RAM_128_8 ;
-- hds interface_end
ARCHITECTURE rtl OF RAM_128_8 IS
type mem_type is array (0 to 127) of STD_Logic_vector (7 downto 0);
signal mem: mem_type;
BEGIN
Process (clk)
begin
if(rising_edge(clk)) then
if(wr='1') then
mem(conv_integer(unsigned(addr))) <= din;
end if;
end if;
End Process;
dout <= mem(conv_integer(unsigned(addr)));
END rtl;
Page: 1
14. RAM 128.8 Simulation Code
force -freeze sim:/ram_128_8/clk 1 0, 0 {50 ns} -r
100
force -freeze sim:/ram_128_8/wr 1 0
force -freeze sim:/ram_128_8/addr 0000000 0
force -freeze sim:/ram_128_8/din 00000000 0
force -freeze sim:/ram_128_8/addr 0000000 100
force -freeze sim:/ram_128_8/addr 0000001 200
force -freeze sim:/ram_128_8/addr 0000010 300
force -freeze sim:/ram_128_8/addr 0000011 400
force -freeze sim:/ram_128_8/addr 0000100 500
force -freeze sim:/ram_128_8/addr 0000101 600
force -freeze sim:/ram_128_8/addr 0000110 700
force -freeze sim:/ram_128_8/addr 0000111 800
force -freeze sim:/ram_128_8/addr 0001000 900
force -freeze sim:/ram_128_8/addr 0001001 1000
force -freeze sim:/ram_128_8/din 01100100 100
force -freeze sim:/ram_128_8/din 01100101 200
force -freeze sim:/ram_128_8/din 01100110 300
force -freeze sim:/ram_128_8/din 01100111 400
force -freeze sim:/ram_128_8/din 01101000 500
force -freeze sim:/ram_128_8/din 01101001 600
force -freeze sim:/ram_128_8/din 01101010 700
force -freeze sim:/ram_128_8/din 01101011 800
force -freeze sim:/ram_128_8/din 01101100 900
force -freeze sim:/ram_128_8/din 01101101 1000
force -freeze sim:/ram_128_8/wr 0 1100
force -freeze sim:/ram_128_8/addr 0000000 1200
force -freeze sim:/ram_128_8/addr 0000001 1300
force -freeze sim:/ram_128_8/addr 0000010 1400
force -freeze sim:/ram_128_8/addr 0000011 1500
force -freeze sim:/ram_128_8/addr 0000100 1600
force -freeze sim:/ram_128_8/addr 0000101 1700
force -freeze sim:/ram_128_8/addr 0000110 1800
Page 1
15. RAM 128.8 Simulation Code
force -freeze sim:/ram_128_8/addr 0000111 1900
force -freeze sim:/ram_128_8/addr 0001000 2000
force -freeze sim:/ram_128_8/addr 0001001 2100
add wave sim:/ram_128_8/*
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
Page 2
18. C:FPGAdv52LibrariesSsrc@r@a@m_16_4@r@t@l.vhd 12/30/11 12:19:28
-- hds header_start
--
-- VHDL Architecture S.RAM_16_4.RTL
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 17:25:54 11/16/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY RAM_16_4 IS
-- Declarations
PORT (addr,din: IN STD_Logic_Vector (3 downto 0);
dout: OUT STD_Logic_Vector (3 downto 0);
wr,clk: IN STD_Logic);
END RAM_16_4 ;
-- hds interface_end
ARCHITECTURE RTL OF RAM_16_4 IS
type mem_type is array (0 to 15) of STD_Logic_vector (3 downto 0);
signal mem: mem_type;
BEGIN
Process (clk)
begin
if(rising_edge(clk)) then
if(wr='1') then
mem(conv_integer(unsigned(addr))) <= din;
end if;
end if;
End Process;
dout <= mem(conv_integer(unsigned(addr)));
END RTL;
Page: 1
19. RAM 16.4 Simulation Code
force -freeze sim:/ram_16_4/clk 1 0, 0 {50 ns} -r
100
force -freeze sim:/ram_16_4/wr 1 0
force -freeze sim:/ram_16_4/addr 0000 0
force -freeze sim:/ram_16_4/din 0000 0
force -freeze sim:/ram_16_4/addr 0000 100
force -freeze sim:/ram_16_4/addr 0001 200
force -freeze sim:/ram_16_4/addr 0010 300
force -freeze sim:/ram_16_4/addr 0011 400
force -freeze sim:/ram_16_4/addr 0100 500
force -freeze sim:/ram_16_4/addr 0101 600
force -freeze sim:/ram_16_4/addr 0110 700
force -freeze sim:/ram_16_4/addr 0111 800
force -freeze sim:/ram_16_4/addr 1000 900
force -freeze sim:/ram_16_4/addr 1001 1000
force -freeze sim:/ram_16_4/addr 1010 1100
force -freeze sim:/ram_16_4/addr 1011 1200
force -freeze sim:/ram_16_4/addr 1100 1300
force -freeze sim:/ram_16_4/addr 1101 1400
force -freeze sim:/ram_16_4/addr 1110 1500
force -freeze sim:/ram_16_4/addr 1111 1600
force -freeze sim:/ram_16_4/din 1111 100
force -freeze sim:/ram_16_4/din 1110 200
force -freeze sim:/ram_16_4/din 1101 300
force -freeze sim:/ram_16_4/din 1100 400
force -freeze sim:/ram_16_4/din 1011 500
force -freeze sim:/ram_16_4/din 1010 600
force -freeze sim:/ram_16_4/din 1001 700
force -freeze sim:/ram_16_4/din 1000 800
force -freeze sim:/ram_16_4/din 0111 900
force -freeze sim:/ram_16_4/din 0110 1000
force -freeze sim:/ram_16_4/din 0101 1100
force -freeze sim:/ram_16_4/din 0100 1200
force -freeze sim:/ram_16_4/din 0011 1300
Page 1
20. RAM 16.4 Simulation Code
force -freeze sim:/ram_16_4/din 0010 1400
force -freeze sim:/ram_16_4/din 0001 1500
force -freeze sim:/ram_16_4/din 0000 1600
force -freeze sim:/ram_16_4/wr 0 1700
force -freeze sim:/ram_16_4/addr 0000 1800
force -freeze sim:/ram_16_4/addr 0001 1900
force -freeze sim:/ram_16_4/addr 0010 2000
force -freeze sim:/ram_16_4/addr 0011 2100
force -freeze sim:/ram_16_4/addr 0100 2200
force -freeze sim:/ram_16_4/addr 0101 2300
force -freeze sim:/ram_16_4/addr 0110 2400
force -freeze sim:/ram_16_4/addr 0111 2500
force -freeze sim:/ram_16_4/addr 1000 2600
force -freeze sim:/ram_16_4/addr 1001 2700
force -freeze sim:/ram_16_4/addr 1010 2800
force -freeze sim:/ram_16_4/addr 1011 2900
force -freeze sim:/ram_16_4/addr 1100 3000
force -freeze sim:/ram_16_4/addr 1101 3100
force -freeze sim:/ram_16_4/addr 1110 3200
force -freeze sim:/ram_16_4/addr 1111 3300
add wave sim:/ram_16_4/*
run
run
run
run
run
run
run
run
run
run
run
Page 2
21. RAM 16.4 Simulation Code
run
run
run
run
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Page 3
24. C:FPGAdv52LibrariesSsrc@r@o@m_128_8@r@t@l.vhd 12/30/11 12:19:53
-- hds header_start
--
-- VHDL Architecture S.ROM_128_8.RTL
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 16:39:55 11/16/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY ROM_128_8 IS
-- Declarations
PORT (addr: IN STD_Logic_Vector (6 downto 0);
dout: OUT STD_Logic_Vector (7 downto 0);
clk: IN STD_Logic);
END ROM_128_8 ;
-- hds interface_end
ARCHITECTURE RTL OF ROM_128_8 IS
type rom_type is array (0 to 127) of STD_Logic_Vector(7 downto 0);
constant rom: rom_type:= ("00000001","00000010","00000011","00000100",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010",
"00000001","00000010","00000011","00000100");
BEGIN
Process (clk)
Begin
if (rising_edge(clk)) then
dout <= rom(conv_integer(unsigned(addr)));
end if;
End Process;
END RTL;
Page: 1
25. ROM 128.8 Simulation Code
force -freeze sim:/rom_128_8/clk 1 0, 0 {50 ns} -r
100
force -freeze sim:/rom_128_8/addr 0000000 0
force -freeze sim:/rom_128_8/addr 0000001 200
force -freeze sim:/rom_128_8/addr 0000010 400
force -freeze sim:/rom_128_8/addr 0000011 600
force -freeze sim:/rom_128_8/addr 0000100 800
force -freeze sim:/rom_128_8/addr 1111011 1000
force -freeze sim:/rom_128_8/addr 1111100 1200
force -freeze sim:/rom_128_8/addr 1111101 1400
force -freeze sim:/rom_128_8/addr 1111110 1600
force -freeze sim:/rom_128_8/addr 1111111 1800
add wave sim:/rom_128_8/*
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
Page 1
28. C:FPGAdv52LibrariesSsrc@r@o@m_8_2rtl.vhd 12/30/11 13:38:58
-- hds header_start
--
-- VHDL Architecture s.ROM_8_2.rtl
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 13:38:41 12/30/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY ROM_8_2 IS
-- Declarations
PORT (addr: IN STD_Logic_Vector (2 downto 0);
dout: OUT STD_Logic_Vector (1 downto 0);
clk: IN STD_Logic);
END ROM_8_2 ;
-- hds interface_end
ARCHITECTURE rtl OF ROM_8_2 IS
type rom_type is array (0 to 7) of STD_Logic_Vector(1 downto 0);
constant rom: rom_type:= ("00","01","10","11","00","01","10","11");
BEGIN
Process (clk)
Begin
if (rising_edge(clk)) then
dout <= rom(conv_integer(unsigned(addr)));
End if;
End Process;
END rtl;
Page: 1
29. ROM 8.2 Simulatin Code
force -freeze sim:/rom_8_2/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/rom_8_2/addr 000 0
force -freeze sim:/rom_8_2/addr 001 200
force -freeze sim:/rom_8_2/addr 010 300
force -freeze sim:/rom_8_2/addr 011 400
force -freeze sim:/rom_8_2/addr 100 500
force -freeze sim:/rom_8_2/addr 101 600
force -freeze sim:/rom_8_2/addr 110 700
force -freeze sim:/rom_8_2/addr 111 800
add wave sim:/rom_8_2/*
run
run
run
run
run
run
run
run
run
run
run
Page 1
34. S_TLCTLCstruct
Package List Declarations
LIBRARY ieee; Ports:
USE ieee.std_logic_1164.all; Start : std_logic
USE ieee.std_logic_arith.all; clk : std_logic
rst : std_logic
Green : std_logic
Red : std_logic
Yellow : std_logic
Diagram Signals:
SIGNAL finish_r : std_logic
SIGNAL finish_y : std_logic
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: S_TLC/TLC/struct
Edited: by Pharaoh on 16 Dec 2011
rst Green
rst Green
S_TLC
clk TLC_FSM
clk
I2
Yellow
Yellow
Start
Start
finish_y
Red
Red
finish_r
clk finish_y clk finish_r
clk S_TLC q clk S_TLC q
Yellow Red
en Counter_2bit en Counter_4bit
rst
rst I0 rst
rst I1
Printed by Pharaoh on 12/29/2011 at 05:12:47 PM Page 1 of 1
35. S_TLCTLC_FSMfsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements Process Declarations
SIGNAL SCOPE DEFAULT RESET STATUS
Green OUT '0' COMB
Package List
Red OUT '0' COMB
LIBRARY ieee; Yellow OUT '0' COMB
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: S_TLC/TLC_FSM/fsm
Edited: by Pharaoh on 16 Dec 2011
Green <= '1';
s0 Yellow <= '0';
Red <= '0';
finish_r = '1' Start = '1'
Green <= '0'; Green <= '0';
Yellow <= '0'; finish_y = '1' s1 Yellow <= '1';
s2
Red <= '1'; Red <= '0';
Printed by Pharaoh on 12/29/2011 at 05:13:23 PM Page 1 of 1
36. Simulation
view signals
# .signals
force -freeze sim:/tlc/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/tlc/rst 1 0
force -freeze sim:/tlc/rst 0 200
force -freeze sim:/tlc/start 0 0
force -freeze sim:/tlc/start 1 300
force -freeze sim:/tlc/start 0 400
add wave sim:/tlc/*
run
run
run
run
run
run
run
run
run
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Page 1
39. /tlc/start
/tlc/clk
/tlc/rst
/tlc/green
/tlc/red
/tlc/yellow
/tlc/finish_r
/tlc/finish_y
/tlc/yellow_internal
/tlc/red_internal
0 1 us 2 us 3 us 4 us 5 us 6 us 7 us 8 us 9 us
Entity:tlc Architecture:struct Date: Fri Dec 16 20:17:15 HDS 2011 Row: 1 Page: 1
40.
41. C:FPGAdv52LibrariesS_TLCsrc@counter_2bitrtl.vhd 12/16/11 18:20:57
-- hds header_start
--
-- VHDL Architecture S_TLC.Counter_2bit.rtl
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 18:12:46 12/16/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Counter_2bit IS
-- Declarations
PORT (rst, en, clk: IN Std_Logic;
q : OUT Std_Logic);
END Counter_2bit ;
-- hds interface_end
ARCHITECTURE rtl OF Counter_2bit IS
Signal count_sig: unsigned (1 downto 0);
BEGIN
Process(rst,clk)
Begin
if (rst ='1') then
count_sig <= (Others => '0');
elsif (rising_edge(clk)) then
if (en = '1') then
count_sig <= count_sig +1;
end if;
end if;
end process;
q <= count_sig(0) and count_sig(1);
END rtl;
Page: 1
42. Simulation 2bit
view signals
# .signals
force -freeze sim:/counter_2bit/rst 1 0
force -freeze sim:/counter_2bit/rst 0 200
force -freeze sim:/counter_2bit/en 0 0
force -freeze sim:/counter_2bit/en 1 400
force -freeze sim:/counter_2bit/clk 1 0, 0 {50 ns}
-r 100
add wave sim:/counter_2bit/*
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
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run
run
Page 1
44. C:FPGAdv52LibrariesS_TLCsrc@counter_4bitrtl.vhd 12/16/11 18:28:19
-- hds header_start
--
-- VHDL Architecture S_TLC.Counter_4bit.rtl
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 18:27:22 12/16/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Counter_4bit IS
-- Declarations
port(clk,en,rst:IN Std_Logic;
q:OUT Std_Logic);
END Counter_4bit ;
-- hds interface_end
ARCHITECTURE rtl OF Counter_4bit IS
signal count_sig:unsigned(3 downto 0);
BEGIN
process(rst,clk)
begin
if(rst='1') then
count_sig<=(others=>'0');
elsif(rising_edge(clk)) then
if (en='1') then
count_sig<=count_sig+1;
end if;
end if;
end process;
q<=count_sig(0) and count_sig(1) and count_sig(2) and count_sig(3);
END rtl;
Page: 1
45. Simulation 4bit
view signals
# .signals
# .signals
force -freeze sim:/counter_4bit/rst 1 0
force -freeze sim:/counter_4bit/rst 0 200
force -freeze sim:/counter_4bit/en 0 0
force -freeze sim:/counter_4bit/en 1 400
force -freeze sim:/counter_4bit/clk 1 0, 0 {50 ns}
-r 100
add wave sim:/counter_4bit/*
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
Page 1
48. S_Sequence_DetectorSeq_Det_10010struct
Package List Declarations
LIBRARY ieee; Ports:
USE ieee.std_logic_1164.all; Clk : std_logic
USE ieee.std_logic_arith.all; Rst : std_logic
din : std_logic
Seq_Ok : std_logic
Diagram Signals:
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: <<-- more -->>
Edited: by Pharaoh on 17 Dec 2011
Clk
Clk
S_Sequence_Detector
Rst Seq_Ok
Rst Seq_Det_FSM_10010 Seq_Ok
I2
din
din
Printed by Pharaoh on 12/19/2011 at 12:35:28 PM Page 1 of 1
49. S_Sequence_DetectorSeq_Det_FSM_10010fsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements Process Declarations
SIGNAL SCOPE DEFAULT RESET STATUS
Package List Seq_Ok OUT '0' COMB
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: <<-- more -->>
Edited: by Pharaoh on 17 Dec 2011
s0
din = '0'
din = '1'
1
Seq_Ok <= '1'; s5 s1
2 din = '1'
din = '0' din = '0' din = '0' din = '1'
2 din = '1'
1
1
s4 s2
2
1
din = '0'
din = '1'
2
s3
Printed by Pharaoh on 12/19/2011 at 12:35:56 PM Page 1 of 1
52. S_Sequence_DetectorSeq_Det_10010_Ostruct
Package List Declarations
LIBRARY ieee; Ports:
USE ieee.std_logic_1164.all; Clk : std_logic
USE ieee.std_logic_arith.all; Rst : std_logic
din : std_logic
Seq_Ok : std_logic
Diagram Signals:
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: <<-- more -->>
Edited: by Pharaoh on 17 Dec 2011
Clk
Clk
S_Sequence_Detector
Rst Seq_Ok
Rst Seq_Det_FSM_10010_O Seq_Ok
I3
din
din
Printed by Pharaoh on 12/19/2011 at 12:36:22 PM Page 1 of 1
53. S_Sequence_DetectorSeq_Det_FSM_10010_Ofsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements Process Declarations
SIGNAL SCOPE DEFAULT RESET STATUS
Package List Seq_Ok OUT '0' COMB
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: <<-- more -->>
Edited: by Pharaoh on 17 Dec 2011
s0
din = '1'
Seq_Ok <= '1'; s5 s1
2 din = '1'
din = '1'
1
din = '0' din = '0' din = '0' din = '1'
2 1
1 din = '0'
s4 s2
2
1
din = '0'
din = '1'
2
s3
Printed by Pharaoh on 12/19/2011 at 12:36:39 PM Page 1 of 1
56. S_VMVMstruct
Package List Declarations
LIBRARY ieee; Ports:
USE ieee.std_logic_1164.all; Diagram Signals:
SIGNAL Clk : std_logic
USE ieee.std_logic_arith.all;
SIGNAL Dollar : std_logic
SIGNAL Quarter_Dollar : std_logic
SIGNAL Return_Request : std_logic
SIGNAL Rst : std_logic
<company name> SIGNAL Project:
Soda <enter : std_logic
project name here>
SIGNAL Soda_Request : std_logic
Title: <enter diagram title here> <enter comments here>
SIGNAL The_Return : std_logic
Path: S_VM/VM/struct
Edited: by Pharaoh on 21 Dec 2011
Clk
Rst S_VM
VM_FSM
Dollar I0
Quarter_Dollar The_Return
Soda_Request Soda
Return_Request
Printed by Pharaoh on 12/21/2011 at 11:36:14 AM Page 1 of 1
57. S_VMVM_FSMfsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements Process Declarations
SIGNAL SCOPE DEFAULT RESET STATUS
Package List Soda OUT '0' COMB
The_Return OUT '0' COMB
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: S_VM/VM_FSM/fsm
Edited: by Pharaoh on 21 Dec 2011
Quarter_Dollar = '1' Quarter_Dollar = '1' s3
s1 s2
2
1
Quarter_Dollar = '1'
Soda_Request = '1'
1
Quarter_Dollar = '1'
s0 s5
Soda <= '1';
2
Dollar = '1'
s4
s8
The_Return <= '1';
Return_Request = '1' Soda_Request = '1'
s7 s6
Soda <= '0';
Soda <= '1';
Printed by Pharaoh on 12/21/2011 at 11:41:17 AM Page 1 of 1
58. VM Simulation Code - 3 Quarters
force -freeze sim:/vm_fsm/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/vm_fsm/rst 1 0
force -freeze sim:/vm_fsm/rst 0 50
force -freeze sim:/vm_fsm/dollar 0 0
force -freeze sim:/vm_fsm/quarter_dollar 0 0
force -freeze sim:/vm_fsm/soda_request 0 0
force -freeze sim:/vm_fsm/return_request 0 0
force -freeze sim:/vm_fsm/quarter_dollar 1 200
force -freeze sim:/vm_fsm/quarter_dollar 0 500
force -freeze sim:/vm_fsm/soda_request 1 1200
add wave sim:/vm_fsm/*
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
Page 1
61. VM Simulation Code - 4 Quarters
force -freeze sim:/vm_fsm/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/vm_fsm/rst 1 0
force -freeze sim:/vm_fsm/rst 0 50
force -freeze sim:/vm_fsm/dollar 0 0
force -freeze sim:/vm_fsm/quarter_dollar 0 0
force -freeze sim:/vm_fsm/soda_request 0 0
force -freeze sim:/vm_fsm/return_request 0 0
force -freeze sim:/vm_fsm/quarter_dollar 1 200
force -freeze sim:/vm_fsm/quarter_dollar 0 600
force -freeze sim:/vm_fsm/soda_request 1 1200
force -freeze sim:/vm_fsm/return_request 1 2000
add wave sim:/vm_fsm/*
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
Page 1
64. VM Simulation Code - Dollar
force -freeze sim:/vm_fsm/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/vm_fsm/rst 1 0
force -freeze sim:/vm_fsm/rst 0 50
force -freeze sim:/vm_fsm/dollar 0 0
force -freeze sim:/vm_fsm/quarter_dollar 0 0
force -freeze sim:/vm_fsm/soda_request 0 0
force -freeze sim:/vm_fsm/return_request 0 0
force -freeze sim:/vm_fsm/dollar 1 200
force -freeze sim:/vm_fsm/dollar 0 300
force -freeze sim:/vm_fsm/soda_request 1 800
force -freeze sim:/vm_fsm/return_request 1 1600
add wave sim:/vm_fsm/*
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
Page 1
68. ExpEDLstruct
Package List Declarations
LIBRARY ieee; Ports:
USE ieee.std_logic_1164.all; Diagram Signals:
SIGNAL Click : std_logic
USE ieee.std_logic_arith.all;
SIGNAL Clk : std_logic
SIGNAL Key : std_logic_vector(3 DOWNTO 0)
SIGNAL Open_Door : std_logic
SIGNAL Rst : std_logic
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: Exp/EDL/struct
Edited: by Pharaoh on 24 Dec 2011
Clk Open_Door
Exp
Rst Click
EDL_FSM
I0
Key : (3:0)
Printed by Pharaoh on 12/31/2011 at 04:06:55 PM Page 1 of 1
69. ExpEDL_FSMfsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements Process Declarations
SIGNAL SCOPE DEFAULT RESET STATUS
Package List Click OUT '0' COMB
Open_Door OUT '0' COMB
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: Exp/EDL_FSM/fsm
Edited: by Pharaoh on 29 Dec 2011
s0
2
1
Key = "0011"
s1 s5
Click <= '1'; 2 Click <= '1';
1
Key = "1010"
s6
s2
Click <= '1';
Click <= '1'; 2
1
Key = "0101"
s7
s3
Click <= '1';
Click <= '1';
Key = "1011"
s4
Open_Door <= '1';
Click <= '1';
Printed by Pharaoh on 12/29/2011 at 05:35:08 PM Page 1 of 1
71. Simulation Code
force -freeze sim:/edl_fsm/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/edl_fsm/rst 1 0
force -freeze sim:/edl_fsm/rst 0 50
force -freeze sim:/edl_fsm/key 0011 0
force -freeze sim:/edl_fsm/key 1010 100
force -freeze sim:/edl_fsm/key 0101 200
force -freeze sim:/edl_fsm/key 1011 300
add wave sim:/edl_fsm/*
run
run
run
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Page 1
76. Simulation Code
force -freeze sim:/edl_fsm/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/edl_fsm/rst 1 0
force -freeze sim:/edl_fsm/rst 0 50
force -freeze sim:/edl_fsm/key 0000 0
force -freeze sim:/edl_fsm/intr 0 0
force -freeze sim:/edl_fsm/intr 1 200
force -freeze sim:/edl_fsm/intr 1 500
force -freeze sim:/edl_fsm/intr 1 800
force -freeze sim:/edl_fsm/intr 1 1100
force -freeze sim:/edl_fsm/intr 0 300
force -freeze sim:/edl_fsm/intr 0 600
force -freeze sim:/edl_fsm/intr 0 900
force -freeze sim:/edl_fsm/intr 0 1200
force -freeze sim:/edl_fsm/key 1101 200
force -freeze sim:/edl_fsm/key 0011 500
force -freeze sim:/edl_fsm/key 0111 800
force -freeze sim:/edl_fsm/key 1001 1100
add wave sim:/edl_fsm/*
run
run
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Page 1
79. S_SDSDstruct
Package List Declarations
LIBRARY ieee; Ports:
USE ieee.std_logic_1164.all; Diagram Signals:
USE ieee.std_logic_arith.all; SIGNAL Clk : std_logic
SIGNAL Open_Door : std_logic
SIGNAL Rst : std_logic
SIGNAL Sensor_1 : std_logic
SIGNAL Sensor_2 : std_logic
<company name> SIGNAL Project:
close <enter project name here>
: std_logic
SIGNAL <enter comments here>
en : std_logic
Title: <enter diagram title here>
Path: S_SD/SD/struct
Edited: by Pharaoh on 21 Dec 2011
Clk
Rst
Open_Door
Sensor_1
Sensor_2 S_SD
SD_FSM
I0 en
Clk close
clk S_SD close
Rst
rst Counter_20sec
en I1
Printed by Pharaoh on 12/21/2011 at 02:59:21 PM Page 1 of 1
80. S_SDSD_FSMfsm ['machine0']
Architecture Declarations
Global Actions Concurrent Statements
Process Declarations
Package List Signals Status State Register Statements
LIBRARY ieee; SIGNAL SCOPE DEFAULT RESET STATUS
USE ieee.std_logic_1164.all; Open_Door OUT '0' COMB
USE ieee.std_logic_arith.all; en OUT '0' COMB
<company name> Project: <enter project name here>
Title: Smart Door <enter comments here>
Path: S_SD/SD_FSM/fsm
Edited: by Pharaoh on 21 Dec 2011
s0
Sensor_1 = '1' OR Sensor_2 = '1'
2
s1 close = '1' s2
Open_Door <= '1'; en <= '0';
en <= '1'; Sensor_1 = '1' OR Sensor_2 = '1' 1
Printed by Pharaoh on 12/21/2011 at 03:05:29 PM Page 1 of 1
81. Smart Door - Simulation Code
add wave sim:/sd/*
force -freeze sim:/sd/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/sd/rst 1 0
force -freeze sim:/sd/rst 0 50
force -freeze sim:/sd/sensor_2 0 0
force -freeze sim:/sd/sensor_1 0 0
force -freeze sim:/sd/sensor_1 1 900
force -freeze sim:/sd/sensor_1 0 1000
force -freeze sim:/sd/sensor_2 1 3900
force -freeze sim:/sd/sensor_2 0 4000
force -freeze sim:/sd/sensor_2 1 6900
force -freeze sim:/sd/sensor_2 0 7000
run
run
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Page 1
82. Smart Door - Simulation Code
run
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Page 2
83. Smart Door - Simulation Code
run
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Page 3
84.
85.
86. C:FPGAdv52LibrariesS_SDsrc@counter_20secrtl.vhd 12/21/11 14:58:23
-- hds header_start
--
-- VHDL Architecture S_SD.Counter_20sec.rtl
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 12:40:51 12/21/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Counter_20sec IS
-- Declarations
port(rst,clk,en: in std_logic;
close: out std_logic);
END Counter_20sec ;
-- hds interface_end
ARCHITECTURE rtl OF Counter_20sec IS
signal count: unsigned(4 downto 0);
BEGIN
process(rst,clk)
begin
if(rst = '1')then
count <= "00010";
close <= '0';
elsif (rising_edge(clk)) then
if(en = '1') then
if( count < 20 ) then
count <= count + 1;
close <= '0';
else
count <= "00001";
close <= '1';
end if;
end if;
end if;
end process;
END rtl;
Page: 1
88. BasmaSuezstruct
Package List Declarations
LIBRARY ieee; Ports:
USE ieee.std_logic_1164.all; Diagram Signals:
SIGNAL Clk : Std_Logic
USE ieee.std_logic_arith.all;
SIGNAL Rst : Std_Logic
SIGNAL Start_4 : Std_Logic
SIGNAL Start_8 : Std_Logic
SIGNAL alarm : Std_Logic
SIGNAL finish_4 : Std_Logic
SIGNAL finish_8 : Std_Logic
SIGNAL gate_closed : Std_Logic
SIGNAL green : Std_Logic
SIGNAL red : Std_Logic
SIGNAL sensor_A : std_logic
SIGNAL sensor_B : std_logic
SIGNAL sensor_C : std_logic
SIGNAL yellow : Std_Logic
<company name> Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: Basma/Suez/struct
Edited: by Pharaoh on 29 Dec 2011
Rst
Clk
sensor_A alarm
gate_closed
sensor_B
sensor_C green
yellow
red
Basma
suez_fsm
I0
finish_4
Start_4
finish_8
Start_8
Clk Clk finish_8
clk finish_4
clk Basma q
Start_4
q Start_8
en Basma en counter_3bits
Rst
rst counter_2bits Rst
rst I2
I1
Printed by Pharaoh on 12/29/2011 at 04:42:42 PM Page 1 of 1
89. Basmasuez_fsmfsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements Process Declarations
SIGNAL SCOPE DEFAULT RESET STATUS
Package List Start_4 OUT '0' COMB
Start_8 OUT '0' COMB
LIBRARY ieee;
alarm OUT '0' COMB
USE ieee.std_logic_1164.all;
gate_closed OUT '0' COMB
USE ieee.std_logic_arith.all; green OUT '0' COMB
red OUT '0' COMB
yellow OUT '0' <company name>
COMB Project: <enter project name here>
Title: <enter diagram title here> <enter comments here>
Path: Basma/suez_fsm/fsm
Edited: by Pharaoh on 29 Dec 2011
sensor_A = '0' AND sensor_B = '0' AND sensor_C = '0'
green <= '0';
yellow <= '1';
s5 s0 sensor_A = '1' s1
green <= '1'; red <= '0';
green <= '0';
yellow <= '0'; Start_4 <= '1';
yellow <= '0';
red <= '1'; red <= '0';
sensor_C = '1' finish_4 = '1'
green <= '0';
alarm <= '1';
yellow <= '0';
gate_closed <= '1'; s4 sensor_B = '1' s3 finish_8 = '1' s2
red <= '1';
green <= '0';
Start_8 <= '1';
yellow <= '0';
red <= '1';
gate_closed <= '1';
green <= '0';
yellow <= '0';
red <= '1';
Printed by Pharaoh on 12/29/2011 at 04:43:10 PM Page 1 of 1
90. Simulation Forces
force -freeze sim:/suez/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/suez/rst 1 0
force -freeze sim:/suez/rst 0 50
force -freeze sim:/suez/sensor_a 0 0
force -freeze sim:/suez/sensor_b 0 0
force -freeze sim:/suez/sensor_c 0 0
force -freeze sim:/suez/sensor_a 1 200
force -freeze sim:/suez/sensor_a 0 300
force -freeze sim:/suez/sensor_b 1 1600
force -freeze sim:/suez/sensor_b 0 1700
force -freeze sim:/suez/sensor_c 1 4000
force -freeze sim:/suez/sensor_c 0 4100
add wave sim:/suez/*
run
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Page 1
92. /suez/clk
/suez/rst
/suez/green
/suez/yellow
/suez/red
/suez/sensor_a
/suez/sensor_b
/suez/sensor_c
/suez/start_4
/suez/finish_4
/suez/start_8
/suez/finish_8
/suez/gate_closed
/suez/alarm
0 500 1 us 1500 2 us 2500 3 us 3500 4 us 4500
Entity:suez Architecture:struct Date: Thu Dec 29 16:44:34 HDS 2011 Row: 1 Page: 1
93.
94. C:FPGAdv52LibrariesBasmasrccounter_2bitsuntitled.vhd 12/29/11 14:06:48
-- hds header_start
--
-- VHDL Architecture Basma.counter_2bits.untitled
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 13:55:37 12/29/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY counter_2bits IS
-- Declarations
PORT (rst, en, clk: IN Std_Logic;
q : OUT Std_Logic);
END counter_2bits ;
-- hds interface_end
ARCHITECTURE untitled OF counter_2bits IS
Signal count_sig: unsigned (1 downto 0);
BEGIN
Process(rst,clk)
Begin
if (rst ='1') then
count_sig <= (Others => '0');
elsif (rising_edge(clk)) then
if (en = '1') then
count_sig <= count_sig +1;
end if;
end if;
end process;
q <= count_sig(0) and count_sig(1);
END untitled;
Page: 1
95. C:FPGAdv52LibrariesBasmasrccounter_3bitsuntitled.vhd 12/29/11 14:08:12
-- hds header_start
--
-- VHDL Architecture Basma.counter_3bits.untitled
--
-- Created:
-- by - Pharaoh.UNKNOWN (S)
-- at - 14:06:22 12/29/2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY counter_3bits IS
-- Declarations
PORT (rst, en, clk: IN Std_Logic;
q : OUT Std_Logic);
END counter_3bits ;
-- hds interface_end
ARCHITECTURE untitled OF counter_3bits IS
Signal count_sig: unsigned (2 downto 0);
BEGIN
Process(rst,clk)
Begin
if (rst ='1') then
count_sig <= (Others => '0');
elsif (rising_edge(clk)) then
if (en = '1') then
count_sig <= count_sig +1;
end if;
end if;
end process;
q <= count_sig(0) and count_sig(1) and count_sig(2);
END untitled;
Page: 1