Downloaded 133 times
Uploaded byVLSI SYSTEM Design
Static Noise margin
The document discusses the impact of passive components in CMOS circuits, focusing on noise margin and switching activity. It explains noise margin as the tolerance to noise without altering logic levels, characterizing ideal versus practical input/output behavior of an inverter. Key parameters include input/output high and low voltages, and the importance of defined noise margin ranges for accurate signal recognition.
More Related Content
Static Noise margin
- 1. In Out Circuit Ideal Scenario Out In Circuit Practical Scenario
- 2. Out In Circuit Practical Scenario Due to the behavioral aspects of the passive components (R,L,C), the ideal characteristics of the circuits are affected. To understand this behavior, let’s focus on below mentioned terms 1. Noise Margin 2. Switching Activity of CMOS
- 3. Noise Margin 1. Noisemargin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit. 2. Noise margin does makes sure that any signal which is logic '1' with finite noise added to it, is still recognized as logic '1' and not logic '0'. 3. It is basically the difference between signal value and the noise value 3/2/2013 3
- 4. 0 1 Let’s Begin with a example, Consider a Inverter
- 5. 0/1 1/0 Input and Output of an Inverter
- 6. 0/1 1/0 Vout 0 Vin I/O Characteristic of a Inverter
- 7. 0/1 1/0 Vout Vdd 0 Vdd/2 Vdd Vin Ideal I/O Characteristic of a Inverter
- 8. 0/1 1/0 Vout Infinite Slope Vdd 0 Vdd/2 Vdd Vin Ideal I/O Characteristic of a Inverter with Infinite Slope
- 9. 0/1 1/0 Vout Vout Infinite Slope Vdd Vdd 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin Actual I/O Characteristic of a Inverter with Finite Slope
- 10. 0/1 1/0 Vout Vout Infinite Slope Finite Slope Vdd Vdd 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin Actual I/O Characteristic of a Inverter with Finite Slope
- 11. 0/1 1/0 Vout Vout Infinite Slope Finite Slope Vdd Vdd VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH VIL is Input Low Voltage => Any input voltage level between 0 and VIL will be treated as logic ‘0’
- 12. 0/1 1/0 Vout Vout Infinite Slope Finite Slope Vdd Vdd VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH VOL is Output Low Voltage => Any output voltage level between 0 and VOL will be treated as logic ‘0’
- 13. 0/1 1/0 Vout Vout Infinite Slope Finite Slope Vdd Vdd VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH VIH is Input High Voltage =>Any input voltage level between VIH and VDD will be treated as logic ‘1’
- 14. 0/1 1/0 Vout Vout Infinite Slope Finite Slope Vdd Vdd VOH VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH VOH is Output High Voltage =>Any output voltage level between VOH and VDD will be treated as logic ‘1’
- 15. 0/1 1/0 Vout Vout Finite Slope Vdd Vdd VOH VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
- 16. 0/1 1/0 Vout Vout Finite Slope Vdd Vdd VOH VOL 0 Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
- 17. 0/1 1/0 Vout Vout Finite Slope Vdd Vdd VOH VOL 0 Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
- 18. 0/1 1/0 Vout Vout Finite Slope Vdd Vdd VOH VOL 0 VIL Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
- 19. 0/1 1/0 Vout Vout Finite Slope Vdd Vdd VOH VOL 0 VIL VIH Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
- 20. 0/1 1/0 Vout Vout Finite Slope Vdd Vdd VOH VOL VOL 0 VIL VIH Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
- 21. 0/1 1/0 Vout Vout Finite Slope Vdd Vdd VOH VOH VOL VOL 0 VIL VIH Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
- 22. 0/1 1/0 Vout Vout Finite Slope Vdd Slope = -1 Vdd VOH VOH Slope = -1 VOL VOL 0 VIL VIH Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
- 23. 0/1 1/0 Vout Vdd Slope = -1 VOH Slope = -1 VOL 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
- 24. 0/1 1/0 Vout Vdd Slope = -1 VOH Slope = -1 VOL 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
- 25. 0/1 1/0 Vout Vdd Vdd Slope = -1 VOH Slope = -1 VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
- 26. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 VOH Slope = -1 VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
- 27. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 VIH VOH Slope = -1 VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
- 28. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 VIH VOH Slope = -1 VIL VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
- 29. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 VIH VOH Slope = -1 VIL VOL VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
- 30. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 VIH VOH Slope = -1 VIL VOL VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
- 31. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 NMH VIH Noise Margin High VOH Slope = -1 VIL VOL VOL 0 0 VIL VIH Vdd Vin NMH is the Noise Margin High => Any voltage level in “NMH” range will be detected as logic ‘1’
- 32. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 NMH VIH Noise Margin High VOH Slope = -1 VIL NML Noise Margin Low VOL VOL 0 0 VIL VIH Vdd Vin NML is the Noise Margin Low => Any voltage level in “NML” range will be detected as logic ‘0’
- 33. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 NMH VIH Noise Margin High VOH Slope = -1 VIL NML Noise Margin Low VOL VOL 0 0 VIL VIH Vdd Vin NMH = VOH - VIH NML = VIL - VOL
- 34. 0/1 1/0 Vout Vdd VOH Vdd Slope = -1 NMH VIH Noise Margin High VOH Undefined Region Slope = -1 VIL NML Noise Margin Low VOL VOL 0 0 VIL VIH Vdd Vin Any Signal in ‘Undefined Region’ will be indefinite logic level
- 35. Noise Margin Summary Forany signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NML and NMH ranges, respectively 3/2/2013 35