The document describes the design of a concurrent triple-band low noise amplifier (LNA) that operates at 1.8 GHz, 2.4 GHz, and 5.2 GHz. A cascode structure with a source degeneration inductor is used. The input matching network employs a multi-element LC filter to match the input to 50 ohms across all three bands. Separate output resonance circuits are used for each band. Simulation results show the LNA achieves good input matching and noise figure across bands while providing sufficient gain and linearity.

1. Concurrent Triple-Band Low Noise
Amplifier Design
Presenter: Halil İbrahim Kayıhan
Supervisor: Assoc. Prof. Nil Tarım
Department: Electronic and Communication Engineering
JUNE 2015
1www.hikayihan.com

2. Overview
2
Low noise amplifier
Circuit topologies and biasing
Matching networks and load circuits
Single band design
Triple band design
Simulation results (0.18μm TSMC)
S-parameter results
Noise figure
1dB compression point
Third order intercept point
www.hikayihan.com

3. Low Noise Amplifier
3
Low noise figure
Sensitivity of the total receiver chain
Friis’ formula
Enough gain
S21 parameter
Good input matching
S11 parameter
Linearity
P1dB and IP3
www.hikayihan.com

4. LNA Structures
4
Common gate
Common source with resistive feedback
Cascode with current mirror
Cascode with source degeneration
Zi Zi
Zi
(a) (b) (c)
www.hikayihan.com

5. Single Band Cascode LNA
5
Source degeneration inductor provides the
real part of the input impedance.
Zi
M1
M2
Ls
𝑍𝑖 =
1
𝑠𝐶𝑔𝑠
+
𝑔 𝑚 𝐿 𝑠
𝐶𝑔𝑠
+ 𝑠𝐿 𝑠
𝑍𝑖 =
1
𝑠(𝐶𝑔𝑠 + 2𝐶𝑔𝑑
+
𝑔 𝑚 𝐿 𝑠
𝐶𝑔𝑠 + 2𝐶𝑔𝑑
+ 𝑠𝐿 𝑠
www.hikayihan.com

6. Biasing and Sizing the MOSFETs
6
M1
M2
Ls
Matching
Network
DC
RFC
Cc
AC
50ohm
+VDD
VDD = 1.8V
Gate of M1 is VDD/2
Equal overdrive voltages (Vgs-Vt)
and transconductance (gm)
Coupling capacitor
RFC
www.hikayihan.com

7. Biasing and Sizing the MOSFETs
7
W/L ratio is selected considering:
Transconductance
Parasitic capacitances
Source inductance
Gate inductance
W/L = (20 X 5μm)/(0.18μm) with 20 fingers
𝑔 𝑚 = 46.34 𝑚𝑆
𝐶𝑔𝑠 = 121 𝑓𝐹
𝐶𝑔𝑠 = 38.2 𝑓𝐹
www.hikayihan.com

8. Input Matching Network
8
Zi
M1
Ls
Lg
Cgs
Cgd
www.hikayihan.com

9. Input Matching Network
9
Inductors are modeled with series resistance
Modified input impedance expression
𝑍𝑖 =
1
𝑠(𝐶𝑔𝑠 + 2𝐶𝑔𝑑)
+
𝑔 𝑚 𝐿 𝑠
𝐶𝑔𝑠 + 2𝐶𝑔𝑑
+ 𝑠𝐿 𝑠 + 𝑠𝐿 𝑔 + 𝑟𝐿𝑠 + 𝑟𝐿𝑔 = 50Ω
𝑟𝐿𝑠 =
𝜔𝐿 𝑠
𝑄
, 𝑟𝐿𝑔 =
𝜔𝐿 𝑔
𝑄
, 𝜔 = 2.4 𝐺𝐻𝑧, 𝑄 = 10
L
=>
L
rL
www.hikayihan.com

10. Load Resonance Circuit
10
Load resonance circuit is a simple parallel LC
circuit.
𝜔 𝑜=
1
𝐿 𝑜 𝐶 𝑜
LoCo
www.hikayihan.com

11. Element Values
11
CC RFC Lg Ls Lo Co M1 M2
107.5pF 100nH 23.416nH 64pH 808.6pH 4.397pF
W=100µm
L=0.18µm
W=100µm
L=0.18µm
LoCo
M1
M2
Ls
+VDD
Lg
Zi
www.hikayihan.com

12. Simulation Results
12
S11 and S21 parameters
www.hikayihan.com

13. Simulation Results
13
S12 parameter
www.hikayihan.com

14. Simulation Results
14
Noise figure
www.hikayihan.com

15. Simulation Results
15
1dB compression point
www.hikayihan.com

16. Simulation Results
16
Third order intercept point
www.hikayihan.com

17. Simulation Results
17
Total results
Output port impedance is 50ohm.
ZO = 53.67+j*38.3.
The proper LC network for output matching
can be used for a specific impedance.
fO S11 S21 S12 S22 NF P1dB IIP3
2.4GHz -42.22dB 19.44dB -44.91dB -5.48dB 2.61dB -18.23dBm -15.91dBm
www.hikayihan.com

18. Concurrent LNA Design
18
Simultaneous multiband operation without
switching structures
Lower power consumption
Reduced chip area
Three frequencies: 1.8GHz, 2.4GHz and 5.2GHz
Input matching to 50Ω
Design for ideal and nonideal inductors and
capacitors
www.hikayihan.com

19. Cascode Structure and Biasing
19
Transistor circuit and biasing are the same for
concurrent LNA
Concurrent LNA is designed with ideal
elements and nonideal elements separately
For ideal case W/L ratio is (50μm/0.18μm)
For nonideal case W/L ratio is (100μm/0.18μm)
Some values for ideal case:
𝐶𝑔𝑠= 60.53 𝑓𝐹
𝐶𝑔𝑑 = 19.097 𝑓𝐹
𝑔 𝑚= 23.104 𝑚𝑆
www.hikayihan.com

20. Input Matching Network
20
Zi
M1
Ls
Lg
Cgs
Cgd
C2
L2
C1
L1
www.hikayihan.com

21. Input Matching Network
21
Equivalents for 1.8GHz, 2.4GHz and 5.2GHz
Lga2*L2a1*L1
Lga3*L2
Lg
(a)
(b)
(c)
b1/L1
b3/L2b2/L1
www.hikayihan.com

22. Input Matching Network
22
Coefficients and frequency values
a1 a2 a3 b1 b2 b3
𝜔4
2
𝜔4
2
− 𝜔1
2
𝜔5
2
𝜔5
2
− 𝜔1
2
𝜔5
2
𝜔5
2
− 𝜔2
2
𝜔2
2
− 𝜔4
2
𝜔2
2
. 𝜔4
2
𝜔3
2
− 𝜔4
2
𝜔3
2
. 𝜔4
2
𝜔3
2
− 𝜔5
2
𝜔3
2
. 𝜔5
2
𝝎 𝟏 𝝎 𝟐 𝝎 𝟑 𝝎 𝟒 𝝎 𝟓
1.8GHz 2.4GHz 5.2GHz 2.079GHz 3.533GHz
www.hikayihan.com

23. Input Matching Network
23
Input impedance expressions
• 𝑍𝑖 = 𝑎1. 𝑠𝐿1 + 𝑎2. 𝑠𝐿2 + 𝑠𝐿 𝑔 + 𝑠𝐿 𝑠 +
1
𝑠. 𝐶 𝑔𝑠+2𝐶 𝑔𝑑
+
𝑔 𝑚.𝐿 𝑠
𝐶 𝑔𝑠
• 𝑍𝑖 =
1
𝑠.
𝑏1
𝐿1
+ 𝑎3. 𝑠𝐿2 + 𝑠𝐿 𝑔 + 𝑠𝐿 𝑠 +
1
𝑠. 𝐶 𝑔𝑠+2𝐶 𝑔𝑑
+
𝑔 𝑚.𝐿 𝑠
𝐶 𝑔𝑠
• 𝑍𝑖 =
1
𝑠.
𝑏2
𝐿1
+
1
𝑠.
𝑏3
𝐿2
+ 𝑠𝐿 𝑔 + 𝑠𝐿 𝑠 +
1
𝑠. 𝐶 𝑔𝑠+2𝐶 𝑔𝑑
+
𝑔 𝑚.𝐿 𝑠
𝐶 𝑔𝑠
• 𝜔4
2
=
1
𝐿1.𝐶1
• 𝜔5
2
=
1
𝐿2.𝐶2
www.hikayihan.com

24. Load Resonance Circuits
24
Conventional:
www.hikayihan.com

25. Load Resonance Circuits
25
Proposed:
L18 C18
L24 C24
L52 C52
www.hikayihan.com

26. Element Values
26
L1 L2 Lg Ls C1 C2
6.5664nH 19.647nH 27.766nH 213.64pH 922fF 104fF
L18 L24 L52 C18 C24 C52
100pH 100pH 100pH 78pF 43.975pF 9.35pF
www.hikayihan.com

27. Simulation Results
27
All circuit diagram:
Zi
M1
Ls
Lg
Cgs
Cgd
C2
L2
C1
L1
L18 C18
L24 C24
L52 C52
M2
Vout
Vin
www.hikayihan.com

28. Simulation Results
28
S11 and S21 parameters
www.hikayihan.com

29. Simulation Results
29
S12 parameter
www.hikayihan.com

30. Simulation Results
30
S22 parameter
www.hikayihan.com

31. Simulation Results
31
Noise figure
www.hikayihan.com

32. Simulation Results
32
Total results
Total results with nonideal capacitors
Frequency S11 S21 S12 NF P1dB IIP3
1.8 GHz -23.59dB 25.76dB -41.17dB 422mdB -15.80dBm -13.98dBm
2.4 GHz -27.87dB 23.27dB -41.16dB 426mdB -14.65dBm -16.40dBm
5.2 GHz -40.31dB 16.58dB -41.09dB 538mdB -11.34dBm -22.08dBm
Frequency S11 S21 S12 NF P1dB IIP3
1.8 GHz -24.17dB 25.75dB -41.18dB 421mdB -15.73dBm -13.92dBm
2.4 GHz -28.77dB 23.26dB -41.17dB 425mdB -14.60dBm -16.55dBm
5.2 GHz -40.21dB 16.57dB -41.09dB 537mdB -11.32dBm -21.95dBm
www.hikayihan.com

33. Nonideal Case Input Matching
33
Zi
M1
Ls
Lg
Cgs
Cgd
C2
L2
C1
L1
rLg
rLp2rLp1
rLs
www.hikayihan.com

34. Nonideal Case Input Matching
34
Parallel effective resistances
• 𝑟𝐿𝑝1
= 𝑟𝐿1
. 1 + 𝑄 𝐿
2
≅
𝐿1
𝑟 𝐿1 𝐶1
• 𝑟𝐿𝑝2
= 𝑟𝐿2
. 1 + 𝑄 𝐿
2
≅
𝐿2
𝑟 𝐿2 𝐶2
Lga2*L2a1*L1
Lga3*L2
Lg
(a)
(b)
(c)
b1/L1
b3/L2b2/L1
rLp1 rLp2
rLp1 rLp2
rLp1 rLp2
www.hikayihan.com

35. Nonideal Case Input Matching
35
Parallel RC and RL circuit expressions
• 𝑍 𝑅𝐿 =
𝜔2 𝐿2 𝑅
𝜔2 𝐿2+𝑅2 + 𝑗.
𝜔𝐿𝑅2
𝜔2 𝐿2+𝑅2
• 𝑍 𝑅𝐶 =
𝑅
𝜔2 𝑅2 𝐶2+1
− 𝑗.
𝜔𝐶𝑅2
𝜔2 𝑅2 𝐶2+1
www.hikayihan.com

36. Nonideal Case Input Matching
36
𝑅𝑒 𝑍1.8𝐺 =
𝜔1
2
. 𝑎1
2
. 𝐿1
2
. 𝑟𝐿𝑝1
𝜔1
2
. 𝑎1
2
. 𝐿1
2
+ 𝑟𝐿𝑝1
2 +
𝜔1
2
. 𝑎2
2
. 𝐿2
2
. 𝑟𝐿𝑝2
𝜔1
2
. 𝑎2
2
. 𝐿2
2
+ 𝑟𝐿𝑝2
2 +
𝜔2. 𝐿 𝑔
𝑄
+ 𝐿 𝑠.
𝑔 𝑚
𝐶𝑖𝑛
+
𝜔2
𝑄
𝐼𝑚 𝑍1.8𝐺 =
𝑎1. 𝐿1. 𝑟𝐿𝑝1
2
𝜔1
2
. 𝑎1
2
. 𝐿1
2
+ 𝑟𝐿𝑝1
2 +
𝑎2. 𝐿2. 𝑟𝐿𝑝2
2
𝜔1
2
. 𝑎2
2
. 𝐿2
2
+ 𝑟𝐿𝑝2
2 −
1
𝜔1
2
. 𝐶𝑖𝑛
+ 𝐿 𝑠 + 𝐿 𝑔
𝑅𝑒 𝑍2.4𝐺 =
𝑟𝐿𝑝1
𝜔2
2
. 𝑟𝐿𝑝1
2
.
𝑏1
𝐿1
2
+ 1
+
𝜔2
2
. 𝑎3
2
. 𝐿2
2
. 𝑟𝐿𝑝2
𝜔2
2
. 𝑎3
2
. 𝐿2
2
+ 𝑟𝐿𝑝2
2 +
𝜔2. 𝐿 𝑔
𝑄
+ 𝐿 𝑠.
𝑔 𝑚
𝐶𝑖𝑛
+
𝜔2
𝑄
𝐼𝑚 𝑍2.4𝐺 = −
𝑏1
𝐿1
. 𝑟𝐿𝑝1
2
𝜔2
2
.
𝑏1
𝐿1
2
. 𝑟𝐿𝑝1
2
+ 1
+
𝑎3. 𝐿2. 𝑟𝐿𝑝2
2
𝜔2
2
. 𝑎3
2
. 𝐿2
2
+ 𝑟𝐿𝑝2
2 −
1
𝜔2
2
. 𝐶𝑖𝑛
+ 𝐿 𝑠 + 𝐿 𝑔
𝑅𝑒 𝑍5.2𝐺 =
𝑟𝐿𝑝1
𝜔3
2
. 𝑟𝐿𝑝1
2
.
𝑏2
𝐿1
2
+ 1
+
𝑟𝐿𝑝2
𝜔3
2
. 𝑟𝐿𝑝2
2
.
𝑏3
𝐿2
2
+ 1
+
𝜔2. 𝐿 𝑔
𝑄
+ 𝐿 𝑠.
𝑔 𝑚
𝐶𝑖𝑛
+
𝜔2
𝑄
𝐼𝑚 𝑍5.2𝐺 = −
𝑏2
𝐿1
. 𝑟𝐿𝑝1
2
𝜔3
2
.
𝑏2
𝐿1
2
. 𝑟𝐿𝑝1
2
+ 1
−
𝑏3
𝐿2
. 𝑟𝐿𝑝2
2
𝜔3
2
.
𝑏3
𝐿2
2
. 𝑟𝐿𝑝2
2
+ 1
−
1
𝜔3
2
. 𝐶𝑖𝑛
+ 𝐿 𝑠 + 𝐿 𝑔
www.hikayihan.com

37. Load Resonance Circuit Values
37
L18 L24 L52 C18 C24 C52
1.4nH 852.9pH 870pH 4.75pF 5.51pF 1.171pF
www.hikayihan.com

38. Simulation Results for Q=10
38
L1 L2 Lg Ls C1 C2
3.413nH 9.966nH 13.939nH 64.038pH 1.648pF 206.88fF
Frequency S11 S21 S12 NF P1dB IIP3
1.8 GHz -6.475dB 18.61dB -48.03dB 5.27dB -13.02dBm -20.00dBm
2.4 GHz -5.959dB 14.80dB -49.34dB 5.91dB -11.22dBm -17.36dBm
5.2 GHz -43.91dB 15.63dB -41.81dB 2.70dB -9.08dBm -17.48dBm
www.hikayihan.com

39. Simulation Results for Q=30
39
L1 L2 Lg Ls C1 C2
3.309nH 9.932nH 14.08nH 114pH 1.648pF 206.88fF
Frequency S11 S21 S12 NF P1dB IIP3
1.8 GHz -15.38dB 23.21dB -43.62dB 3.04dB -13.36dBm -20.07dBm
2.4 GHz -17.48dB 20.87dB -43.46dB 2.69dB -12.61dBm -20.28dBm
5.2 GHz -17.59dB 17.12dB -40.43dB 1.34dB -9.37dBm -17.25dBm
www.hikayihan.com

40. Simulation Results for Q=40
40
L1 L2 Lg Ls C1 C2
3.295nH 9.853nH 14.128nH 120pH 1.8056pF 204.72fF
Frequency S11 S21 S12 NF P1dB IIP3
1.8 GHz -20.14dB 24.16dB -42.71dB 2.45dB -14.20dBm -18.30dBm
2.4 GHz -21.95dB 21.67dB -42.68dB 2.20dB -13.13dBm -20.32dBm
5.2 GHz -16.56dB 17.31dB -40.25dB 1.14dB -9.35dBm -17.25dBm
www.hikayihan.com

41. Total Simulation Results
41
Q Frequency S11 S21 S12 NF P1dB IIP3
10
1.8 GHz
-6.475dB 18.61dB -48.03dB 5.27dB -13.02dBm -20.00dBm
30 -15.38dB 23.21dB -43.62dB 3.04dB -13.36dBm -20.07dBm
40 -20.14dB 24.16dB -42.71dB 2.45dB -14.20dBm -18.30dBm
Ideal -23.59dB 25.76dB -41.17dB 422mdB -15.80dBm -13.98dBm
10
2.4 GHz
-5.959dB 14.80dB -49.34dB 5.91dB -11.22dBm -17.36dBm
30 -17.48dB 20.87dB -43.46dB 2.69dB -12.61dBm -20.28dBm
40 -21.95dB 21.67dB -42.68dB 2.20dB -13.13dBm -20.32dBm
Ideal -27.87dB 23.27dB -41.16dB 426mdB -14.65dBm -16.40dBm
10
5.2 GHz
-43.91dB 15.63dB -41.81dB 2.70dB -9.08dBm -17.48dBm
30 -17.59dB 17.12dB -40.43dB 1.34dB -9.37dBm -17.25dBm
40 -16.56dB 17.31dB -40.25dB 1.14dB -9.35dBm -17.25dBm
Ideal -40.31dB 16.58dB -41.09dB 538mdB -11.34dBm -22.08dBm
www.hikayihan.com

42. Comparison with Other Works
42
Reference Frequency S11 S21 NF P1dB IIP3 Power
[1]
945 MHz -7.0dB 18.0dB 4.6dB - -12.8dBm
32.4mW2.4 GHz -15.0dB 24.0dB 4.4dB - -15.3dBm
5.25 GHz -10.0dB 23.0dB 4.4dB - -14.7dBm
[2]
2.4 GHz -10.3dB 11.8dB 3.8dB - -3.0dBm
13.5mW3.5 GHz -10.4dB 11.7dB 4.0dB - -2.1dBm
5.2 GHz -13.5dB 10.0dB 3.7dB - -0.4dBm
[3]
1.8 GHz -10.6dB 10.1dB 3.69dB -7.8dBm 1.7dBm
39.14mW2.45 GHz -10.4dB 10.8dB 4.75dB -9.8dBm 0dBm
5.25 GHz -19.9db 11.8dB 6.36dB -6.9dBm 4.5dBm
This Work
(Q=30)
1.8 GHz -15.38dB 23.21dB 3.04dB -13.36dBm -20.07dBm
21.35mW2.4 GHz -17.48dB 20.87dB 2.69dB -12.61dBm -20.28dBm
5.2 GHz -17.59dB 17.12dB 1.34dB -9.37dBm -17.25dBm
www.hikayihan.com

43. References
43
[1] C.W. Ang, Y. Zheng, and C. H.Heng, “A multi-band CMOS low noise
amplifier for multi-standard wireless receivers,” in IEEE Int. Circuits
Syst. Symp. Dig., 2007, pp. 2802–2805.
[2] C. Y. Kao, Y. T. Chiang, and J. R. Yang, “A concurrent multi-band
low-noise amplifier for WLAN/WiMAX applications,” in IEEE Int.
Electron./Inform. Technol. Conf. Dig., 2008, pp. 514–517.
[3] Christina F. Jou , Kuo-Hua Cheng , Eing-Tsang Lu and Yang Wang,
"Design Of A Fully Integrated Concurrent Triple-Band CMOS Low Noise
Amplifier", IEEE, 2004
www.hikayihan.com