The document discusses the development of 7nm processors using FinFET transistors and EUV lithography. It begins with an introduction to processors and Moore's Law. It then discusses the problems with continuing Moore's Law using current 14nm technology. It introduces FinFET transistors as a way to make faster transistors without decreasing node size. It also introduces EUV lithography as the solution needed to continue shrinking node sizes. It describes the advantages of FinFETs and challenges with EUV lithography. Finally, it highlights that IBM created the world's first functional 7nm chip in 2015 using FinFETs and EUV lithography, showing the viability of this approach.
Analysis of FinFET based Low Power SRAM Cellijsrd.com
As CMOS electronic devices are continuously shrinking to nanometer regime, leads to increasing the consequences of short channel effects and variability due to the process parameters which lead to cause the reliability of the circuit as well as performance. To solve these issues of CMOS, FINFET is one of the promising and better technologies without sacrificing reliability and performance for its applications and the circuit design. Among the various embedded memory technologies, SRAM provides the highest performance along with low standby power consumption. In CMOS circuits, high leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation due to reduction in threshold voltage, channel length, and gate oxide thickness. FinFET based SRAM design can be used as an alternative solution to the bulk devices. FinFET is suitable for Nano scale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current. As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. The paper focuses on study of various design aspects of FinFET based SRAM.
Analysis of FinFET based Low Power SRAM Cellijsrd.com
As CMOS electronic devices are continuously shrinking to nanometer regime, leads to increasing the consequences of short channel effects and variability due to the process parameters which lead to cause the reliability of the circuit as well as performance. To solve these issues of CMOS, FINFET is one of the promising and better technologies without sacrificing reliability and performance for its applications and the circuit design. Among the various embedded memory technologies, SRAM provides the highest performance along with low standby power consumption. In CMOS circuits, high leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation due to reduction in threshold voltage, channel length, and gate oxide thickness. FinFET based SRAM design can be used as an alternative solution to the bulk devices. FinFET is suitable for Nano scale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current. As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. The paper focuses on study of various design aspects of FinFET based SRAM.
one of the famous Silicon Valley golden rules which state “Higher the clock frequency, Greater the power consumption”. Digging deep into deep submicron CMOS technology, there are design and power management challenges present for Analog and Mixed Signal devices such as PLL and it is very much important to optimize PLL to create a successful and power optimized system. Here, ALF CP PLL is designed in a way that it can operate on low supply voltage but with a 20% reduction in the overall power consumption. The PLL output frequency can be tuned from 80 MHz to 330 MHz and at 350 MHz PLL consumes 190μW at 1V of supply.
Superior Tray Systems Inc.: Introduction to the Technical and Safety Aspects ...Beatrice Wong, MBA
Tired of repairing failed bus ducts? Learn about the technical and safety aspects of our no-maintenance cable bus as an alternative to bus ducts, wire in conduit and cable trays. Visit us at http://www.superiortray.com/ for more information.
Report on PCB designing and fabrication by Prince RohanRohan Das
This is a report on our printed circuit board training on Central Mechanical Engineering Research Institute, Durgapur.
I hope this will help some student. Thank you
DC testing has been accepted for many years as the standard field method for performing high-voltage tests on cable insulation systems. Whenever DC testing is performed, full consideration should be given to the fact that steady-state direct voltage creates within the insulation systems an electrical field determined by the geometry and conductance of the insulation, whereas under service conditions, alternating voltage creates an electric field determined chiefly by the geometry and dielectric constant (or capacitance) of the insulation.
Under ideal, homogeneously uniform insulation conditions, the mathematical formulas governing the steady-state stress distribution within the cable insulation are of the same form for DC and for AC, resulting incomparable relative values; however, should the cable insulation contain defects in which either the conductivity or the dielectric constant assume values significantly different from those in the bulk of the insulation,the electric stress distribution obtained with direct voltage will no longer correspond to that obtained with alternating voltage.
Investigation and design of ion-implanted MOSFET based on (18 nm) channel lengthTELKOMNIKA JOURNAL
The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET’s designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general.
Review of Fin FET Technology and Circuit Design ChallengesIJERA Editor
Considering the difficulties in planar CMOS transistor scaling to secure an acceptable gate to channel control
FinFET based multi-gate (MuGFET) devices have been proposed as a technology option for replacing the
existing technology. The desirability of FinFET that it’s operation principle is same as CMOS process. This
permits to lengthening the gate scaling beyond the planar transistor limits, sustaining a steep subthreshold slope,
better performance with bias voltage scaling and good matching due to low doping concentration in the channel.
There are, still, several challenges and limitations that FinFET technology has to face to be competitive with
other technology options: Fin shape, pitch, isolation, doping, crystallographic orientation and stressing as well as
device parasitic, performance and patterning approaches will be discussed.
Read other blog posts by the author, Zahid Ghadialy, here: https://communities.cisco.com/people/ZahidGhadialy/content
For more discussions and topics around SP Mobility, please visit our Mobility Community: http://cisco.com/go/mobilitycommunity
one of the famous Silicon Valley golden rules which state “Higher the clock frequency, Greater the power consumption”. Digging deep into deep submicron CMOS technology, there are design and power management challenges present for Analog and Mixed Signal devices such as PLL and it is very much important to optimize PLL to create a successful and power optimized system. Here, ALF CP PLL is designed in a way that it can operate on low supply voltage but with a 20% reduction in the overall power consumption. The PLL output frequency can be tuned from 80 MHz to 330 MHz and at 350 MHz PLL consumes 190μW at 1V of supply.
Superior Tray Systems Inc.: Introduction to the Technical and Safety Aspects ...Beatrice Wong, MBA
Tired of repairing failed bus ducts? Learn about the technical and safety aspects of our no-maintenance cable bus as an alternative to bus ducts, wire in conduit and cable trays. Visit us at http://www.superiortray.com/ for more information.
Report on PCB designing and fabrication by Prince RohanRohan Das
This is a report on our printed circuit board training on Central Mechanical Engineering Research Institute, Durgapur.
I hope this will help some student. Thank you
DC testing has been accepted for many years as the standard field method for performing high-voltage tests on cable insulation systems. Whenever DC testing is performed, full consideration should be given to the fact that steady-state direct voltage creates within the insulation systems an electrical field determined by the geometry and conductance of the insulation, whereas under service conditions, alternating voltage creates an electric field determined chiefly by the geometry and dielectric constant (or capacitance) of the insulation.
Under ideal, homogeneously uniform insulation conditions, the mathematical formulas governing the steady-state stress distribution within the cable insulation are of the same form for DC and for AC, resulting incomparable relative values; however, should the cable insulation contain defects in which either the conductivity or the dielectric constant assume values significantly different from those in the bulk of the insulation,the electric stress distribution obtained with direct voltage will no longer correspond to that obtained with alternating voltage.
Investigation and design of ion-implanted MOSFET based on (18 nm) channel lengthTELKOMNIKA JOURNAL
The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET’s designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general.
Review of Fin FET Technology and Circuit Design ChallengesIJERA Editor
Considering the difficulties in planar CMOS transistor scaling to secure an acceptable gate to channel control
FinFET based multi-gate (MuGFET) devices have been proposed as a technology option for replacing the
existing technology. The desirability of FinFET that it’s operation principle is same as CMOS process. This
permits to lengthening the gate scaling beyond the planar transistor limits, sustaining a steep subthreshold slope,
better performance with bias voltage scaling and good matching due to low doping concentration in the channel.
There are, still, several challenges and limitations that FinFET technology has to face to be competitive with
other technology options: Fin shape, pitch, isolation, doping, crystallographic orientation and stressing as well as
device parasitic, performance and patterning approaches will be discussed.
Read other blog posts by the author, Zahid Ghadialy, here: https://communities.cisco.com/people/ZahidGhadialy/content
For more discussions and topics around SP Mobility, please visit our Mobility Community: http://cisco.com/go/mobilitycommunity
Conférence débat du 10 juin 2015, organisée par le groupe Réseaux et Services de Telecom ParisTech Amumni "Quels réseaux pour l'Internet des Objets ?"
présentation de Christophe Fourtet (Sigfox)
Moore’s Law is slowing, but more importantly the world is changing from PCs to smart phones and cloud computing where improvements continue to occur. Improvements are still occurring in other types of ICs such as wireless, GPUs, and 3D camera chips because they lag microprocessors and parallel processing is easier on them than on microprocessors. Data centers are also experiencing rapid improvements as changes in architecture are made, particularly for analyzing unstructured data, i.e., Big Data. These slides discuss the implications for new services in areas such as smart phones, software, and Big Data. The last one-third of the slides summarize alternatives to silicon and von Neumann.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Flex printed circuit boards are at the heart of most modern day electronics, it is the circuit board that provides the density to the electronic. The high density electronics have eyes for a much thinner FPC than the conventional ones. The conventional FPCs comprises of three layers formed by copper, polyimide and bonding adhesives. The three layered circuits are being replaced by two-layer circuits that equate to the copper being directly placed on the polyimide without the help of any adhesives.
The process of manufacturing a flexible printed circuit is a very complex one within itself. The manufacturing of the circuit can be affected by a shift, as tiny as 0.01mils. The FPCs themselves aren’t very huge in their size, so a small shift could have a major impact on the manufacturing of the circuit board. The manufacturing of a flexible printed circuit is a much more complex than that of a rigid PCB. With regards to this, there have been multiple innovations in the manufacturing process of the flexible printed circuits. Here are some of the inventions in the manufacturing world of FPCs:
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Gen AI Study Jams _ For the GDSC Leads in India.pdf
PPT for sessional paper titled 'Seminar' for subject code EC-681
1. 7nm Processors using
FinFET and EUV
By ANIKET BHAGAT(16900314011)
ARJUN SANTRA (16900314018)
Electronics & Communications Engg. Dept.
Under the guidance of Prof. Subham Pramanik
2. Contents
1. INTRODUCTION – Who and what is this all about?
2. Is there a problem with today’s technology?
3. Welcoming Moore’s Law
4. Its limitations today
5. Meeting the solution to these problems
6. FinFET
7. Advantages
8. EUV
9. Current Solutions
10. How EUV enhances current options
11. Its disadvantages
12. The applications
13. World’s 1st 7nm chip
3. INTRODUCTION – What this
is all about? Processors are taken for granted so much by us that
we forget the fact that even the digital watch that
we are wearing on our wrists has a miniature
embedded processor in it which works by using the
same basic concepts as those of advanced
processors – Transistors.
The kind of processors that we will be covering in
today’s discussion are general computing
processors used in Personal Computers and other
devices such as smartphones and various storage
devices.
What do we think of when we
hear the word “PROCESSOR”?
This is what most people think.
4. A very quick look into what processors are.
Processors are nothing but a complex circuit comprised of various components, the most
important of which is Transistors.
They are fabricated on wafers of silicon called die.
They are created using a technique called photolithography.
They are made on different nodes, where a node is the minimum channel length of the
transistors used in making the processor.
5. Current scenario of processors in the market
Currently we have 4-5 major players in
general computing market such as Intel,
AMD, Qualcomm and Samsung along with
various other smaller companies.
Al these companies offer high performance
devices for our daily uses which are
immensely powerful.
The rate at which development has been
taking place and speed has increased over
the years is breath-taking.
6. So, what is the problem then?
Things are looking quite good, right? Processors are very powerful, they can handle almost all of our workload
and development is going on at a steady pace. Actually, NO.
Technological developments continue to stagger us as time goes by. The amount of data analysed and
processed today has tripled over the last few years.
Latest trends such as Virtual Reality, Ultra HD content creation & streaming, automated smart technologies,
Deep Learning, Big Data, Artificial Intelligence are pushing the current processors to their limits.
This has created a demand in the industry for not only faster but more energy efficient solutions compared to
those we have today.
7. Welcome
Moore’s Law
This famous law goes like this – “Moore's law refers to
an observation made by Intel co-founder Gordon Moore
in 1965. He noticed that the number of transistors per
square inch on integrated circuits had doubled every
year since their invention. Moore's law predicts that
this trend will continue into the foreseeable future.
Although the pace has slowed, the number of transistors
per square inch has since doubled approximately every
18 months. This is used as the current definition of
Moore's law.”
This kind of growth is an exponential growth as seen
from the graph.
What it basically means is packing double the amount of
transistors in the same area every 2 years or so.
What this also implies is that the transistors have to be
smaller for this to be physically possible.
This is only possible by decreasing process nodes
Thus, Moore’s Law ushers in faster and more efficient
devices every 2 years.
8. A light hearted look at Moore’s Law’s physical
limitations before we get technical.
9. So what is the problem with Moore’s Law?
Its very simple. Moore’s law was very easy to apply
when the no. of transistors per processor was in
100s or 1000s. Today, they number in billions.
It is becoming physically impossible to create
smaller transistors with current lithographic
techniques.
The most mainstream process node used today is
14nm which has been in use for more than 3 years,
defying Moore’s law.
To make a simple comparison, human hair is about
10000 times thicker than a transistor at 14nm. And
Moore’s Law along with current technology
demands even smaller transistors.
10. So how do we solve these problems?
There are two ways to solving these problems:
First, make transistors which are faster and more efficient than previously used ones.
Second, make transistors smaller ,i.e., decrease process node.
Now, the problem with the second solution is that it is not yet ready for commercial
use while also being very expensive than current solutions.
So, logically we can only make transistors as fast as possible until we are ready to
make the jump to a new node.
The solutions – FinFET transistors for faster computing and Extreme Ultraviolet (EUV)
Lithography for the node jump.
11. The world’s first 3-D transistors - FinFET
Dr. Chenming Hu has been called the Father of 3D Transistor for
developing the FinFET. Intel was the first company to use FinFET in
2011 production calling it the most radical shift in semiconductor
technology in over 50 years.
FinFET technology takes its name from the fact that the FET
structure used looks like a set of fins when viewed.
The main characteristic of the FinFET is that it has a conducting
channel wrapped by a thin silicon "fin" from which it gains its name.
The thickness of the fin determines the effective channel length of
the device.
12. Modern Designs
Typically has a vertical fin on a substrate which runs
between a larger drain and source area. This
protrudes vertically above the substrate as a fin. The
gate orientation is at right angles to the vertical fin.
And to traverse from one side of the fin to the other
it wraps over the fin.
The gate is wrapped around the channel providing
excellent control from three sides of the channel. This
structure is called the FinFET because its Si body
resembles the back fin of a fish.
Width of Channel = 2 X Fin Height + Fin Width
13. Advantages of such a 3-D design.
The main principle behind the structure is a thin body, so the gate capacitance is closer to whole
channel. The body is very thin, around 10nm or less. So, there is no leakage path which is far
from the gate. The gate can effectively control the leakage.
This form of gate structure provides improved electrical control over the channel conduction and
it helps reduce leakage current levels and overcomes some other short-channel effects.
The drive current of the FinFET can be increased by increasing the width of the channel i.e. by
increasing the height of the Fin.
FinFET suffers less from dopant-induced variations. Low channel doping also ensures better
mobility of the carriers inside the channel.
FinFET technology provides numerous advantages over bulk CMOS, such as higher drive current
for a given transistor footprint, hence higher speed, lower leakage, hence lower power
consumption, no random dopant fluctuation, hence better mobility and scaling of the transistor
beyond 28nm.
14. Few more numbers on advantages
Much lower power consumption allows high
integration levels. Early adopters reported 150%
improvements.
FinFETs operate at a lower voltage as a result of
their lower threshold voltage.
Possible to pass through the 20nm barrier
previously thought as an end point.
Static leakage current typically reduced by up to
90%
Operating speed often in excess of 30% faster
than the non-FinFET versions.
15. EUV – Not now but certain in the future.
Extreme Ultraviolet Lithography is the future.
There is no doubt about it.
It uses extremely small 13.5nm wavelength
light for designing.
Currently in development, it is expected to
be introduced into commercial use by 2020.
Microprocessors made by EUV are up to 100
times faster than today’s most powerful chips
16. Current lithographic solutions
Feature sizes of today’s circuits within modern chips can be as small as 42 nm, whereas modern
semiconductor production tools use deep ultraviolet (DUV) argon fluoride (ArF) excimer lasers with 193 nm
wavelength. To compensate for this difference, Intel and other makers of advanced chips use multiple
techniques to enhance resolution of photolithographic equipment.
Immersion lithography replaces the air gap between the lens and wafer with liquid, whose refraction index is
higher than one. For example, purified deionized water has refraction index of 1.44 and this allows to
enhance resolution of production tools by up to 40% depending on materials.
Multiple patterning is a semiconductor production technique that allows to increase feature density by
resolving multiple lines on the same photoresist layer using multiple photomasks. Usage of multi-patterning
essentially means that certain layers within one chip are exposed multiple times, which greatly increases
complexity of manufacturing operations and stretches production cycles, essentially increasing costs of chips.
18. How EUV enhances current solutions
Using EUV can greatly enhance the feature density of chips without heavy reliance
on multi-patterning and additional layers.
For example, TSMC can produce 46 nm metal pitches with a single exposure, an
operation that requires usage of four masks for an ArF scanner.
EUV is expected to shrink cycle times and promises to increase yields of chips at
advanced nodes.
GlobalFoundries and IBM are not the only ones that have poured money into EUV.
In 2012, Intel, Samsung, and TSMC committed a total of €1.38 billion in R&D
funding to ASML for next-generation lithography research.
The reason for all this investment is not only that EUV is hard but that chipmakers
are coming around to the idea that, soon, they may not be able to move forward
without it.
The words of a scientist at TSMC on importance of EUV in Moore’s Law’s survival,
“Totally critical. 100 percent critical. Very, very critical. TSMC expects to
adopt EUV in 2020, when the company aims to begin producing chips on
its 5-nm manufacturing line.”
Curves and Corners: EUV promises
to create sharper shapes [right] than
those that can be created through
multiple patterning with today’s 193-
nanometer light [left]. The lines in
these micrographs have a minimum
width of 24 nm.
19. A new tech always has its disadvantages
In order to generate 13.5 nm EUV light in a special plasma chamber, we need a very powerful
laser.
EUV light with 13.5 nm wavelength can be absorbed by almost any matter thus it has to be done
in vacuum.
Traditional lenses cannot be used with EUV because they absorb 13.5 nm light; instead,
specialized multilayer mirrors are used.
The 13.5 nm EUV light generator needs to have a powerful light source that can expose
economically viable amount of wafers per hour (or day). Moreover, lifetime and continuous
exposure is a yet another point of concern.
The implementation cost is humongous.
20. The applications
All this complicated technology is geared
towards one direction – making faster devices
for our uses.
Even though today’s devices made on 14nm
technology are fast, they are not fast enough.
The world has been eyeing sub-10nm and 7nm
for a long time now and EUV coupled with
FinFETs may just be the exact solution.
40% speed gain or >65% power reduction
over 16nm technology.
21. A ray of light in this darkness.
A report published on 9th July, 2015 – “IBM, working with GlobalFoundries,
Samsung, SUNY, and various equipment suppliers, has produced the world's first 7nm
chip with functional transistors. While it should be stressed that commercial 7nm chips
remain at least two years away, this test chip from IBM and its partners is extremely
significant for three reasons: it's a working sub-10nm chip (this is pretty significant in
itself); it's the first commercially viable sub-10nm FinFET logic chip that uses silicon-
germanium as the channel material; and it appears to be the first commercially viable
design produced with extreme ultraviolet (EUV) lithography.”
This report which is almost 2 years old, gives us a very positive picture of
where we stand today in regards to the stability of EUV technology and its
commercial viability. Needless to say, it is clear that this technology is not
very far away with expected arrival within a couple of year.
One of the 7nm test chips,
created by IBM/SUNY