This document summarizes a presentation given by Jacov Brener and Liav Ben-Artsi of Marvell Israel Ltd on rules of thumb for 100Gb/s board design. The presentation covered COM testing methodology and optimizing the physical design to improve COM margins. Some key guidelines included minimizing reflections by matching discontinuities to the effective channel impedance, shielding signal vias to reduce crosstalk, adding termination vias at the edge of planes, and deskewing signals where skew occurs to reduce ISI. Following these guidelines such as adjusting via structures and adding shield vias increased COM by up to 1dB in examples shown, providing important margin for reliable high-speed signal transmission.

1. TITLE
Image
Are There Any Rules of Thumb When It Comes
to 100Gb/S Board Design? A Walkthrough from
Physical Domain to Channel Operating Margin
(COM) Testing.
Jacov Brener (Marvell Israel Ltd)
Liav Ben-Artsi (Marvell Israel Ltd)

2. Jacov Brener
Senior Signal Integrity Engineer, Marvell Israel Ltd
jacovb@marvell.com |
Jacov is a Senior Signal Integrity Engineer at Marvell Israel Ltd,
starting this year. For the previous 10 years Jacov has worked in Intel's
Communication and Storage Infrastructure Group, most of the time as
package designer and signal/power integrity focal point in a high-speed
PHY team.
Liav Ben-Artsi
Senior Signal Integrity Manager, Marvell Israel Ltd
liav@marvell.com |
Liav is a Senior Signal Integrity Manager at Marvell Israel Ltd. Liav has
worked at Marvell for the last 15 years, most of the time as a signal
integrity engineer, focusing on signal integrity methodologies,
guidelines, test plan definitions and training. He holds several patents
in the field as well as several others pending. Liav took an active part in
IEEE802.3bj standard committee.
SPEAKERS

3. MOTIVATION
COMS-parametersPhysical design Result

4. MOTIVATION
Contd.
COMS-parametersPhysical design Result

5. AGENDA
 Background
 COM basics & test procedure
 DUT host board & reference channel
 Reflections minimization
 Si termination
 Host board discontinuities
 XTALK degradation
 Shield vias
 Termination vias
 De-skewing techniques
 Summary
COM
TX
agg
TX
agg
TX
vic
RX
FEXT
NEXT

6. BACKGROUND
COM basics & test procedure
1. TX & RX equalization:
 TX FFE
 RX CTLE
 RX DFE
2. XTALK addition:
 FEXT
 NEXT
3. Result analysis
 Frequency domain plots
 Pulse responses
 Bathtubs
 COM
Referenced from: R. Mellitz, A. Ran, M. P. Li and V. Ragavassamy, "Channel Operating Margin
(COM): Evolution of Channel Specifications for 25 Gbps and Beyond," in DesignCon, 2013

7. BACKGROUND
DUT host board & reference channel
 Panasonic Megtron6 with HVLP copper
 5in traces on inner layers
 1.6mm thick
 TX & RX channels s-parameters are plotted
DUT host board
RXTX

8. BACKGROUND
DUT host board & reference channel contd.
 5m 24AWG cable
 zQSFP+ mated pair connector
 Cable assembly s-parameters are plotted
for 12mm & 30mm package trace
Reference channel
zQSFP+
connector5m cable
zQSFP+
connector
30mm package12mm package

9. REFLECTION MINIMIZATION
Si termination
Reflection & loss mechanisms equilibrium:
 Reflection mechanism drives the
impedances towards common value
 Loss mechanism pushes the TX down
and RX up – voltage division
 Optimum values for this channel are
35Ω for TX and 55Ω for RX
50Ω Si termination isn’t :
 Optimized value for any channel
 Rule of thumb for any given Si
 Reference impedance for any channel

10. Via structure #1 Via structure #2
VS.
 2 cases of via structures were examined
 Structure #1 is common rule of thumb
 Structure #2 expected to have lower impedance than Structure #1
REFLECTION MINIMIZATION
Host board discontinuities
40mil
30mil40mil
10mil
20mil
40mil
25mil30mil
20mil
10mil

11. Via structure RL Via structure TDR
Via structure #1
Via structure #2
REFLECTION MINIMIZATION
Host board discontinuities contd.
 RL shows structure #1 is better for 100Ω reference impedance
 “Effective impedance” seen by the structures , placed near the BGA:
- Side1: board+system(cable)+board+BGA ~90Ω / Side 2: BGA ~80Ω
 TDR hints structure #2 is better for this case

12. System RL System IL
Via structures #1
Via structures #2
REFLECTION MINIMIZATION
Host board discontinuities contd.
 System RL with structure #2 is better by ~5dB up to 10GHz
 System IL is similar for both structures, but:
- Structure #2 IL is smoother
- Structure #2 loss is a little bit lower

13. System SBR System Voltage BT
Via structures #1
Via structures #2
REFLECTION MINIMIZATION
Host board discontinuities contd.
 System SBR has higher main tap for structure #2 since the channel is less reflective
 System Voltage BT is opened by ~20% using structure #2 instead of structure #1

14. Systems with COM [dB]
Structures #1 2.9 (FAIL)
Structures #2 3.65 (PASS)
REFLECTION MINIMIZATION
Host board discontinuities contd.
COM increased by 0.75dB meeting the pass criteria!
General design guidelines :
Usually the “effective impedance” of the system is lower than 100Ω
Match discontinuities impedance to the “effective impedance”
of the system by making them as transparent as possible
For this test case almost minimum distances of S-S and S-G give the best results

15. Via-to-via Xtalk becomes more significant:
 Trace-to-trace Xtalk is suppressed
while routing as striplines
 Thicker boards have more via Xtalk
High lane count increases via-to-via FEXT:
 Vias are placed in rows to create
corridors for traces
 Same lane TX & RX vias are in the
same row and shielded with
reference vias to mitigate NEXT
 Although distance between different
rows looks enough FEXT may occur
XTALK DEGRADATION
Shield vias

16. E-field w/o shielding
vias
E-field with shielding
vias
VS.
XTALK DEGRADATION
Shielding vias contd.
 E-field w/o shielding vias penetrates much easier to the adjacent than to the same row
 Stitching shielding vias between the rows decreases the E-field by ~40dB

17. Via FEXT
FEXT degradation using shielding vias is substantial:
 ~10dB at Fbaud/2
 ~-60dB max instead of ~2dB/GHz slope
w/o shielding vias
with shielding vias
XTALK DEGRADATION
Shield vias contd.

18. System FEXT System XTALK SBR
w/o shielding vias
with shielding vias
 System FEXT decreased by 4-8dB through the spectrum of significance
 System XTALK SBR decreased by ~40%!
XTALK DEGRADATION
Shielding vias contd.

19. System Voltage XTALK BT System Voltage ISI+XTALK BT
w/o shielding vias
with shielding vias
 Eye opening on voltage scale due to XTALK only → improved by ~15%
 Eye opening on voltage scale due to XTALK and ISI → improved by ~23%
XTALK DEGRADATION
Shield vias contd.

20. Systems with via structures COM [dB]
w/o shielding vias 3.1
with shielding vias 3.35
COM increased by 0.25dB!
General design guidelines :
Don’t base XTALK expectations purely on the distance and symmetry of the vias
Shield signal vias from all sides, yet bit farther than S-G distance
XTALK DEGRADATION
Shield vias contd.

21. XTALK at PCB plane edge becomes more
significant:
 Resonance occurs as return path signal
reaches end of plane and bounces of it
inducing XTALK to nearby victim
 Bitrate increase excites higher frequency
resonances
High lane count increases via-to-via NEXT at PCB
plane edge:
 More vias are pushed to PCB
 NEXT is most sensitive due to tighter
margins to maintain low SNR
XTALK DEGRADATION
Termination vias
E-field on PCB edge

22. E-field w/o termination vias E-field with termination vias
VS.
XTALK DEGRADATION
Termination vias contd.
 Cavity has the same nature of E-field as PCB plane edge just in smaller magnitude
 E-field w/o termination vias bounces off the edge and induces XTALK on the near signal
 Stitching termination vias at the edge of the cavity decrease the E-field by ~15dB

23. XTALK DEGRADATION
Termination vias contd.
Via NEXT
 ~8dB impact on NEXT at spectrum of interest
 Higher frequency improvement can be made with finer stitching
w/o terminating vias
with terminating vias

24. Systems type COM [dB]
w/o terminating vias 3.15
with terminating vias 3.25
COM increased by 0.1dB w/o any real effort!
Stitch the edge of the reference plain with terminating vias
 Via-to-via distance ≤120mil for 25Gbps
 For other rates use: 𝑑 𝑚𝑎𝑥 =
𝑣
2𝐹 𝑏𝑎𝑢𝑑
XTALK DEGRADATION
Termination vias contd.

25. De-skew where skew happens:
 Where exactly skew happens and
how much?
 Both techniques look alike from 1st
glance
Examine local and global skew:
 Technique #1 de-skews all the global
skew in the beginning of signal path
 Technique #2 de-skews only the local
skew at each location.
DE-SKEWING TECHNIQUES
De-skewing technique #1
De-skewing technique #2

26. Trace MC System MC
 De-skewing technique #2 decreases trace MC by 2-3dB
 System MC is decreased by 6-8dB using technique #2
DE-SKEWING TECHNIQUES
Contd.
De-skew technique #1
De-skew technique #2

27. System design phase COM [dB]
Initial 2.35 (FAIL)
Optimized 3.35 (PASS)
COM increased by 1dB , in this case equivalent to ~1in
margin in PCB trace length!
Proper via treatment can increase system’s COM by:
 0.75dB – via matching to the “effective impedance”
 0.25dB – reference via shielding
SUMMARY

28. SUMMARY
Contd.
Distortion type Mitigation Rule-of-Thumb
RL Decrease distances of signal-signal and signal-ground vias almost to minimum
XTALK
Shield signal vias from all sides, yet bit farther than signal-ground distance
Stich termination vias at the end of reference planes at distance ≤120mil
MC De-skew where skew happens by the same amount it happens at the location

29. MORE INFORMATION
 J. Brener and L. Ben-Artsi, "Are There Any Rules of Thumb When It Comes to
100Gb/S Board Design? A Walkthrough from Physical Domain to Channel
Operating Margin (COM) Testing.," DesignCon, 2016.
 jacovb@marvell.com
liav@marvell.com

30. ---
QUESTIONS?
Thank you!