3. • A Phase-Locked Loop (PLL) is a negative feedback system consists of a phase
detector, a low pass filter and a voltage controlled oscillator (VCO) within its loop.
Its purpose is to synchronize an output signal with a reference or input signal in
frequency as well as in phase.
• In the synchronized or “locked” state, the phase error between the oscillator’s
output signal and the reference signal is zero, or it remains constant.
• If a phase error builds up, a control mechanism acts on the oscillator to reduce
the phase error to a minimum so that the phase of the output signal is actually
locked to the phase of the reference signal. This is why it is called a PLL.
• The majority of PLL applications fall into four main categories:
• Frequency synthesis (Most widely used so PLL is also referred as frequency
synthesizer).
• Frequency (FM) and phase (PM) modulation and demodulation.
• Data and carrier recovery.
• Tracking filters.
• Classification of PLLs: Analog or Linear PLL (LPLL), Digital PLL (DPLL) is Analog
PLL with digital phase detector, All-Digital PLL (ADPLL) is a digital loop in two
senses: all digital components and all digital (discrete-time) signals.
Introduction to Phase-locked Loop (PLL)
3
5. 1932: Invention of “coherent communication” using vacuum tube, (deBellescize)
1943: Horizontal and vertical sweep synchronization in television (Wendt and
Faraday)
1954: Color television (Richman)
1965: PLL on integrated circuit
1970: Classical digital PLL
1972: All-digital PLL
PLLs today: in every cell phone, TV, radio, pager, computer, …
Clock and Data Recovery
Frequency Synthesis
Clock Generation
Clock-skew minimization
Duty-cycle enhancement
Brief Phase-Locked Loop (PLL) History
1.people.ee.duke.edu/~mbrooke/defense/Borte.ppt 5
6. Basic PLL System
The basic PLL block diagram consists of three components connected in a feedback loop :
• A Phase Detector (PD) or Phase Frequency Detector (PFD)
• produces a signal V𝝓 proportional to the phase difference between the fin and fosc signal.
• A Loop Filter (LF)
• filters output voltage Vout that controls the frequency of the VCO.
• A Voltage-Controlled Oscillator (VCO)
• Vout at the input of the VCO determines the frequency fosc of the periodic signal Vosc at the output of the VCO
A basic property of the PLL atemps to maintain the frequency lock fosc= fin between Vosc and Vin even if the frequency
fin of the incoming signal varies in time.
Assume the PLL is in the locked condition, and the frequency fin of the incoming signal increases slightly. The phase
difference between the VCO signal and the incoming signal will begin to increase in time. As a result, the filtered
output voltage Vout increases the VCO output frequency fosc increases until it matches fin, thus keeping the PLL in
the locked condition. 6
7. Lock Range and Capture Range of PLL:
Lock Range of the PLL: The range of frequencies where the locked PLL remains in the locked: fmin ≤ fin ≤ fmax
The lock range is wider than the capture range.
• If the PLL is initially locked, and if fmax < fin < fmin the PLL becomes unlocked (fin ≠ fosc).
• When the PLL is unlocked, the fosc= fo where fo is called the center frequency, or the free-running frequency of the VCO.
Capture Range of the PLL: The lock can be established again if the incoming signal frequency fin gets close enough to fo.
The range of frequencies such that the initially unlocked PLL becomes locked: fo- fc ≤ fin ≤ fo+ fc
Sometimes a frequency detector is added to the phase detector to assist in initial acquisition of lock.
There are three stages of PLL operations:
• Free Running Stage: When no input is applied at the
phase detector, PLL out put frequency is fosc = fo
where fo free running frequency of the VCO.
• Capture Stage: When an input is applied at the phase
detector and due to feedback mechanism PLL tries to
track the output with respect to the input.
• Phase Locked Stage: Due to feedback mechanism,
the frequency comparison stops when fosc = fin.
Stages of PLL Operations
7
8. Linear (Analog) Phase Detector
An analog multiplier mixer can be used as a phase detector which compares
the phase at each input and generates an error signal, Vφ(t), proportional to
the phase difference between the two inputs.
Recall that the mixer takes the product of two inputs.
Vφ(t) = cos(ωosct + φosc) cos(ωint + φin)
= (1/2) {cos[(ωosct – ωint )+ (φosc – φin)] + cos[(ωosct + ωint )+ (φosc + φin)]}
When loop is locked (ωosc = ωin) we have an output proportional to the
cosine of the phase difference and one output at twice the input frequency .
Vφ(t) = (1/2) {cos(φosc – φin) + cos[(2ωosct )+ (φosc + φin)]}
The doubled frequency component will be removed by the low-pass loop
filter. Any phase difference then shows up as the control voltage to the VCO,
a DC or slowly varying AC signal after filtering. KD is the gain of the phase
detector (V/rad).
Vφ(t) = KD (φosc – φin) where KD π/2 = VDD/2 KD = VDD/π
The averaged transfer characteristic of such a phase detector is shown below.
Note that in many implementations, the characteristic may be shifted up in
voltage (single supply/single ended).
cos(ωint + φin)
cos(ωosct + φosc)
Vφ(t) = ½{cos(φ0sc – φin)
+ cos[(2ωosct)+ (φosc+φin)]}
High frequency
component to be removed
by low-pass filter
+VDD/2
–VDD/2
8
11. Voltage Controlled Oscillator (VCO)
11
The VCO oscillates at an angular frequency, ωout. Its
frequency is set to a nominal ω0 when the control voltage
is zero. Frequency is assumed to be linearly proportional to
the control voltage with a gain coefficient KO (rad/s/v)
ωout = ω0 + KO Vout
12. PLL 4046 Design Example
The filter output Vo controls the VCO, i.e., determines the frequency fosc of the VCO output Vosc . From PLL 4046 circuit
below, the voltage Vo controls the charging and discharging currents through capacitor C1. As a result the frequency fosc
of the VCO is determined by the Vo. The VCO output Vosc is a square wave with 50% duty ratio and frequency fosc.
For proper operation of the VCO, components C1, R1 and R2
should satisfy: 100pF ≤ C1 ≤ 100nF and 10kΩ ≤ R1, R2 ≤ 1MΩ 12
13. Given PLL 4046 circuit on previous page.
1) Select C1, R1 and R2 so that the VCO operates from fmin = 8 kHz to fmax = 12 kHz.
2) Find the frequency sensitivity (gain) KO if the VCO characteristic fosc (Vo) is linear for 0 ≤ Vo ≤ VDD where VDD = 15V.
3) Select Cf and Rf so that the cut off frequency of the low-pass filter fp = 1KHz
4) Assume Vin(t) is square-wave signal at frequency fin. Determine voltage Vo for:
a) fin = 9 kHz
b) fin = 10 kHz
c) fin = 11 kHz
Solution:
1) Select C1 = 1 nF
R2 = 1 / (1, 032 nF x 8000) ≈ 121 kΩ
R1 = 1 / (1, 032 nF x 4000) ≈ 242 kΩ
2) KO = (12 – 8)kHz / (15 – 0)V = 267 Hz/V or 1676 rad/V
3) Select Cf = 10 nF Rf = 1 / (1kHz x 2π x 10nF) ≈ 16 kΩ
4) For:
a) fin = 9 kHz ΔVo = Δfosc / KO = (12 – 9) / 267 = 11.2 V VO ≈ 3.8 V
b) fin = 10 kHz ΔVo = Δfosc / KO = (12 – 10) / 267 = 7.5 V VO = 7.5 V
c) fin = 9 kHz ΔVo = Δfosc / KO = (12 – 11) / 267 3.7 V VO ≈ 11.3 V
PLL Design Example
13
14. Problem 1.
Determine the change in frequency for a voltage controlled oscillator (VCO) with a transfer function of KO = 2.5KHz/V
and a DC input voltage change of ΔVO = 0.8V.
Solution: Δf = ΔVO KO Δf = (0.8 V)(2.5 kHz/V) = 2 kHz
Problem 2.
Calculate the voltage at the output of a phase comparator with a PD gain of KD = 0.5V/rad and a phase error of
Φϴ = 0.75 rads.
Solution: VD = KD Φϴ = (0.5 V/rad)(0.75 rad) = 0.375 V
Problem 3.
Determine the hold in range, (i.e. the maximum change in frequency) for a phase lock loop with an open loop gain of
KV = 20kHz/rad.
Solution: Δfmax = KV π/2 = (20 krad) π/2 rad = 31.4 kHz
Problem 4.
Find the phase error necessary to produce a VCO frequency shift of Δf = 10KHz for an open loop gain of
KV = 40KHz/rad.
Solution: Vϴ = Δf / KV = 10 kHz / 40 kHz/rad) = 0.25 rad
Problem 5:
Given fosc = 1.2 MHz at VCOin = 4.5 V and fosc = 380 kHz at VCOin = 1.6 V. Find Ko
Solution: Ko = 2π x (1.2 MHz – 380KHz) / (4.5V – 1.6V) rad/V = 1,777 krad/s/v
Examples
14
18. Designing an Integer-N PLL Frequency Synthesizer
Output Frequency: 2.0MHz to 3.0MHz
Frequency Steps: 100KHz
Lock-Up Time Between Channels: 1ms
Overshoot < 25%
19. The programmable counter Kn can be found as:
The PLL must be optimized (ζ =0.7) for divider ratio:
Nmean = (Nmin Nmax)1/2 = (20x30)1/2 = 25
ζmean = (ζmin ζmax)1/2
Determine of damping factor:
ζmean = 0.7 at Nmean = 25
ζmax / ζmin = (Nmax / Nmin)1/2 = (30/20)1/2 = 1.22
(ζmin x 1.22ζmin)1/2 = (1.22ζ2
min)1/2 = 0.7
ζmin = 0.7/(1.22)1/2 = 0.63 at N = 30
ζmax = 1.22x0.63 = 0.77 at N = 20
This range is acceptable.
The overshoot and stability as a function of the damping ratio ξ is
illustrated by the various plots. Each response is plotted as a function
of the normalized time ωnt.
For a given ξ and a lock-up time t, the ωn required to achieve the
desired results can be determined. it is seen that a damping ratio ζ =
0.7 will produce a peak overshoot less than 25% and will settle within
5% at ωnt = 4.5. The required lock-up time is 1ms.
21. Common PLL Applications
• Clock multiplier/Clock Generator
• Input: Fixed frequency clock
• Output: Multiple of input clock frequency/Multiple of clock outputs
• Frequency synthesizer (Fractional-N, Integer-N)
• Input: Fixed frequency clock
• Output: Clock signal with arbitrary frequency
• Clock and data recovery
• Input: Data signal (from a serial link)
• Output: Digital data as well as clock signal with phase detector is different than other
applications
• FM demodulation
• Input: Radio signal
• Output: Demodulated signal
24. • The resolution of the output frequency is determined by the reference frequency applied to the phase detector. Step
size or frequency resolution - the smallest frequency increment possible.
• To obtain a stable low frequency source is not easy, because a quartz crystal oscillating in kHz region is quite bulky
and not practical. A sensible approach is to take a good stable crystal-based high frequency source and an integer-N
synthesizer to divide it down.
Example: Given an oscillator EXTAL = 10 MHz, a step size/frequency resolution of 200 KHz is required. Determine counter
values of R and N to produce outputs fOUT = 900.2, 900.4, … MHz.
Solution: Step size/frequency resolution: fREF = 200 KHz = 10 MHz / R R = 10 MHz / 200 kHz = 50
FOUT = 900.2 MHz = 200 kHz x N N = 900.2 MHz / 200 kHz = 4501 N = 4501, 4502, …
Integer-N Synthesizer
25. Fractional-N allows the resolution at the PLL output to be reduced to small fractions of the PFD frequency as shown
below, where the PFD input frequency is 1 MHz. It is possible to generate output frequencies with resolutions
of 100s of Hz, while maintaining a high PFD frequency. As a result the N-value is significantly less than for integer-N.
Fractional-N Synthesizer
26. Programmable Phase-Locked Loop Clock Generator
The FS7140/FS7145 is a monolithic CMOS clock generator/regenerator IC. Via the I2C−bus interface, the FS7140/45 can
be adapted to many clock generation requirements. The length of the reference and feedback dividers, their fine
granularity and the flexibility of the post divider make the FS7140/45 the most flexible stand alone PLL clock generator
available.
27. Four-modulus prescalers
To extend the upper frequency range of a frequency synthesizer but still allows the synthesis of lower
frequencies. The solution is the four-modulus prescaler. The four-modulus prescaler is a logical extension
of the dual-modulus prescaler. It offers four different scaling factors, and two control signals are required to
select one of the four available scaling factors.
Integer-N Frequency Synthesizers with Prescalers
fosc = 10MHz
28. Integer-N Frequency Synthesizers with Prescalers cont.
There are three programmable /N counters in the system: /N1, /N2, and /N3 dividers.
The overall division ratio is given by: NEFF = 100N1 + 10N2 + N3
where N3 represents the units, N2 the tens, and N1 the hundreds of the division ratio Ntot.
N2 and N3 range: 0 – 9, and N1 ≥ N2 and N3 because when the content of N1 becomes 0, all
/N1, /N2 and /N3 counters are reloaded to their preset values, and the cycle is repeated.
Output /N2 and /N3 counters are HIGH when counter value ≠ 0 and go LOW when counter
value = 0. Note: For a reference frequency f1 = 10 kHz, the lowest frequency to be
synthesized is therefore: 100 x f1 = 1 MHz.
Example: We wish to generate a frequency that is 1023 times the reference frequency. The
division ratio Ntot is thus 1023; hence N1 = 10, N2 = 2, and N3 = 3 are chosen.
Both outputs of the /N2 and /N3 counters are now HIGH, a condition that causes the four-
modulus prescaler to divide initially by 111.
NEFF = 2(111) + 1(101) + 7(100) = 1023
N2:
Add 10
N3:
Add 1
Divide by
0 0 100
0 1 101
1 0 110
1 1 111
The four-modulus prescaler can divide by factors of
100, 101, 110, and 111. The internal logic of the four-
modulus prescaler is designed so that the scaling
factor is determined by control signals “N2: Add 10”
and “N3: Add 1” as shown in next table.
N1 N2 N3 Div
10 2 3 111
9 1 2 111
8 0 1 101
7 0 0 100
6 100
5 100
4 100
3 100
2 100
1 100
0 Reload values for
N1, N2, N3
10 2 3 111
29. Frequency Synthesis and Frequency Dividers
A frequency synthesis technique and frequency dividers are used to generate multiple frequencies
from an accurate reference frequency, usually a crystal oscillator.
In this manner, the non integer frequencies can be developed.
Example: A system requires CPU clock 1.6 GHz, memory clock = 200MHz and I/O bus clock = 400 MHz.
A crystal oscillator of 30 MHz is used for fREF. Determine counters /R, /N, /P and /Q.
Solution: Choose R = 3 fPFD = 30 MHz / 3 = 10 MHz, N = 160 fOSC = 160 x 10 MHz (CPU),
P = 4 fOSC = 1.6 GHz / 4 = 400 MHz (I/O Clock), Q = 8 fOSC = 1.6 GHz / 8 = 200 MHz (Memory).
fOSC
30 MHz
10 MHz
/160
/8
/4
/3
30. Clock Data Recovery
Different Techniques of Data Communication
1. Serial Data Communication:
Data bits are transmitted sequentially
one by one
2. Parallel Data Communication:
Data bits are driven on multiple wires simultaneously.
a) Skew
Travelling path length
for every bit is going to
be different. Due to this
some bits can arrive
early or before than
others which may
corrupt the information.
b) Inter symbol interference (ISI) and Cross talk
Due to several parallel links ISI and Cross talk is introduced in the system
which gets more severe as length of link is increased. So this limits the
length of a connection.
c) Limitation of I/O pin count
Parallel data communication requires a lot more I/O pins than what is
required by serial data communication.
31. A Clock and Data Recovery (CDR) circuit is an essential block in many high-speed wire-linked data transmission
applications such as optical communications systems, backplane data-link routing and chip-to-chip interconnection.
Sometimes the data is sent over the high speed serial interfaces without an accompanying clock, the receiver needs to
recover the clock in order to sample the data on serial lines.
The important role of a Clock and Data Recovery (CDR) is to:
• Detect the transitions in the received data and generates a periodic recovery clock – Clock recovery.
• Retime the received data which samples noisy data and then regenerates it with less jitter and skew driven by the
recovered clock – Data recovery.
Note: A primary difference between CDR and PLL is that the incoming data is not periodic like the incoming reference
clock of a PLL
Clock Data Recovery
32. 32
• Phase Detector: Generates an output signal in relation to the phase difference of both inputs
• Linear – PLL can analyzed in a similar manner as frequency synthesizers
• Nonlinear – PLL operates as a bang-bang control system (hard to rigorously analyze in many cases)
• Charge-Pump: Output pulses of PD are converted to current
• Loop Filter: Integrates the output of the charge pump and produces the control voltage
• Voltage Controlled Oscillator: Generates a periodic output whose frequency depends on the control voltage
Clock Data Recovery
33. 33
Hogge Phase Detector (Linear PD):
Error output, e(t), consists of two pulses with opposite polarity
• Positive polarity pulse has an area that is proportional to the phase error between the data and clock
• Negative polarity pulse has a fixed area corresponding to half of the clk period
• Overall area is zero when data edge is aligned to falling clock edge
Phase Detectors in Clock and Data Recovery Circuits
34. 34
Alexander Phase Detector (Bang-Bang PD):
Data is sampled at 3 equidistant points A, B and C
• XOR gates combine nodes A, B and C: X = A xor B and Y = B xor C
• Performs an early-late detection
Clock is early: Y = Low and X = High
Clock is late: Y = High and X = Low
Phase Detectors in Clock and Data Recovery Circuits
35. 35
Phase Detectors in Clock and Data Recovery Circuits
Alexander Phase Detector (Bang-Bang PD):
36. • Clock Jitter:
Jitter is a shift in the edges of a periodic signal. This
breaks the periodicity of the signal.
– AC - jitter: The uncertainty of the output phase
– DC - phase offset: Undesired difference of the
average output phase relative to the input phase.
A data bit should be sampled at the
centre. It is the optimum position
where maximum shift in the edges
on either side (from left to right or
right to left) can be encountered.
However if the shift in an edge
becomes greater than half of the bit
period then there will be a bit error.
Clock w/o jitter Clock w/ jitter
Clock Data Recovery
• Data Jitter: Jitter tolerance is defined as the amount of jitter that
the CDR circuit must tolerate on the input data without increasing
the bit error rate (BER).
If the jitter on the input data varies slowly, the recovered clock will
track the transition in the data and always sample the data in the
middle of the bit period as shown below. This will guarantee a low
BER.
If the jitter on the input data varies fast, the recovered clock will not
be able to track the transition in the data and will fail to sample the
data in the middle of the bit period as shown in Figure 2.14. This will
result in a greater BER.
38. Differentiation CDR
The steps taken by the algorithm to obtain the recovered data. The first plot is the input data, the
second is the differentiated input data. We can see that the peaks occur at the zero crossings of the
input data. The third plot is the fullwave rectified differentiated data. This data is used to create a
clock, which is then used to create the fourth plot, the regenerated data
