The document summarizes the Phase-Locked Loop (PLL) system. It discusses the basic components of a PLL including the phase detector, loop filter, and voltage-controlled oscillator. It provides examples of PLL applications for frequency synthesis, modulation/demodulation, data recovery, and tracking filters. It also describes integer-N and fractional-N PLL architectures and provides examples of calculating output frequencies for each.

1. Phase-Locked Loop (PLL)
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1
‫ﻣﺣﺎﺿرة‬
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2. OBJECTIVES
‫اﻟﻣﺣﺎﺿرة‬ ‫ھدف‬
• Introduction to Phase-locked loop (PLL)
• Basic PLL System
• Phase Detector (PD)
• Voltage Controlled Oscillator (VCO)
• Loop Filter (LF)
• PLL Applications
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3. • A Phase-Locked Loop (PLL) is a negative feedback system consists of a
phase detector, a low pass filter and a voltage controlled oscillator (VCO)
within its loop. Its purpose is to synchronize an output signal with a reference
or input signal in frequency as well as in phase.
• The majority of PLL applications fall into four main categories:
• Frequency synthesis (Most widely used so PLL is also referred
as frequency synthesizer).
• Frequency (FM) and phase (PM) modulation and demodulation.
• Data and carrier recovery.
• Tracking filters.
• Classification of PLLs: Analog or Linear PLL (LPLL), Digital PLL
(DPLL) is Analog PLL with digital phase detector, All-Digital PLL
(ADPLL) is a digital loop in two senses: all digital components and all
digital (discrete-time) signals.
Introduction to Phase-locked Loop (PLL)
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4. How Are PLLs Used?
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5. Basic PLL System
The basic PLL block diagram consists of three components connected in a feedback
loop :
• A Phase Detector (PD) or Phase Frequency Detector (PFD)
• produces a signal V𝝓𝝓 proportional to the phase difference between the fin and fosc
signal.
• A Loop Filter (LF)
• filters output voltage Vout that controls the frequency of the VCO.
• A Voltage-Controlled Oscillator (VCO)
• Vout at the input of the VCO determines the frequency fosc of the periodic signal
Vosc at the output of the VCO
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6. There are three stages of PLL operations:
• Free Running Stage: When no input is applied at the phase detector, PLL out put
frequency is fosc = fo where fo free running frequency of the VCO.
• Capture Stage: When an input is applied at the phase detector and due to feedback
mechanism PLL tries to track the output with respect to the input.
• Phase Locked Stage: Due to feedback mechanism, the frequency comparison stops
when fosc = fin.
Stages of PLL Operations
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7. PLL 4046 Design Example
The filter output Vo controls the VCO, i.e., determines the frequency fosc of the VCO output Vosc . From PLL 4046 circuit
below, the voltage Vo controls the charging and discharging currents through capacitor C1. As a result the frequency fosc
of the VCO is determined by the Vo. The VCO output Vosc is a square wave with 50% duty ratio and frequency fosc.
The VCO characteristics are adjustable by three
components: R1, R2 and C1.
When Vo = 0, the VCO operates at the minimum frequency
fmin given approximately by:
fmin =
𝟏𝟏
𝑹𝑹𝑹𝑹(𝑪𝑪𝑪𝑪+𝟑𝟑𝟑𝟑 𝒑𝒑𝒑𝒑)
When Vo = VDD, the VCO operates at the maximum
frequency fmax given approximately by:
fmax = fmin+
𝟏𝟏
𝑹𝑹𝟏𝟏(𝑪𝑪𝑪𝑪+𝟑𝟑𝟑𝟑 𝒑𝒑𝒑𝒑)
For fmin ≤ fosc ≤ fmax, the VCO output frequency fosc is ideally a
linear function of the control voltage Vo.
The slope Ko =
𝜟𝜟fosc
𝜟𝜟𝑽𝑽𝒐𝒐
of the fosc(Vo) characteristic is called
the gain or the frequency sensitivity of the VCO, in Hz/V.
For proper operation of the VCO, components C1, R1 and R2
should satisfy: 100pF ≤ C1 ≤ 100nF and 10kΩ ≤ R1, R2 ≤ 1MΩ 7

8. Given PLL 4046 circuit on previous page.
1) Select C1, R1 and R2 so that the VCO operates from fmin = 8 kHz to fmax = 12 kHz.
2) Find the frequency sensitivity (gain) KO if the VCO characteristic fosc (Vo) is linear for 0 ≤ Vo ≤ VDD where VDD = 15V.
3) Select Cf and Rf so that the cut off frequency of the low-pass filter fp = 1KHz
4) Assume Vin(t) is square-wave signal at frequency fin. Determine voltage Vo for:
a) fin = 9 kHz
b) fin = 10 kHz
c) fin = 11 kHz
Solution:
1) Select C1 = 1 nF
 R2 = 1 / (1, 032 nF x 8000) ≈ 121 kΩ
 R1 = 1 / (1, 032 nF x 4000) ≈ 242 kΩ
2) KO = (12 – 8)kHz / (15 – 0)V = 267 Hz/V or 1676 rad/V
3) Select Cf = 10 nF  Rf = 1 / (1kHz x 2π x 10nF) ≈ 16 kΩ
4) For:
a) fin = 9 kHz  ΔVo = Δfosc / KO = (12 – 9) / 267 = 11.2 V  VO ≈ 3.8 V
b) fin = 10 kHz  ΔVo = Δfosc / KO = (12 – 10) / 267 = 7.5 V  VO = 7.5 V
c) fin = 9 kHz  ΔVo = Δfosc / KO = (12 – 11) / 267 3.7 V  VO ≈ 11.3 V
PLL Design Example
fmin =
𝟏𝟏
𝑹𝑹𝑹𝑹(𝑪𝑪𝑪𝑪+𝟑𝟑𝟑𝟑 𝒑𝒑𝒑𝒑)
fmax = fmin+
𝟏𝟏
𝑹𝑹𝑹𝑹(𝑪𝑪𝑪𝑪+𝟑𝟑𝟑𝟑 𝒑𝒑𝒑𝒑)
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9. Common PLL Applications
• Clock multiplier/Clock Generator
• Input: Fixed frequency clock
• Output: Multiple of input clock frequency/Multiple of clock outputs
• Frequency synthesizer (Fractional-N, Integer-N)
• Input: Fixed frequency clock
• Output: Clock signal with arbitrary frequency
• Clock and data recovery
• Input: Data signal (from a serial link)
• Output: Digital data as well as clock signal with phase detector is different than other
applications
• FM demodulation
• Input: Radio signal
• Output: Demodulated signal

10. Basic PLL

11. • The resolution of the output frequency is determined by the reference frequency applied to the phase detector. Step
size or frequency resolution - the smallest frequency increment possible.
• To obtain a stable low frequency source is not easy, because a quartz crystal oscillating in kHz region is quite bulky
and not practical. A sensible approach is to take a good stable crystal-based high frequency source and an integer-N
synthesizer to divide it down.
Example: Given an oscillator EXTAL = 10 MHz, a step size/frequency resolution of 200 KHz is required. Determine counter
values of R and N to produce outputs fOUT = 900.2, 900.4, … MHz.
Solution: Step size/frequency resolution: fREF = 200 KHz = 10 MHz / R  R = 10 MHz / 200 kHz = 50
FOUT = 900.2 MHz = 200 kHz x N  N = 900.2 MHz / 200 kHz = 4501  N = 4501, 4502, …
Integer-N Synthesizer

12. Fractional-N allows the resolution at the PLL output to be reduced to small fractions of the PFD frequency as shown
below, where the PFD input frequency is 1 MHz. It is possible to generate output frequencies with resolutions
of 100s of Hz, while maintaining a high PFD frequency. As a result the N-value is significantly less than for integer-N.
Fractional-N Synthesizer
NEFF =
𝑨𝑨(𝑵𝑵)+𝑩𝑩(𝑵𝑵+𝟏𝟏)
𝑨𝑨+𝑩𝑩
A: Cycle for N counter
B: Cycle for N+1 counter
A + B = 10
Toggling between the two integer
division ratios, a fractional division
ratio can be achieved by time-
averaging the divider output.
NEFF =
𝟖𝟖(𝟗𝟗𝟗𝟗𝟗𝟗)+𝟐𝟐(𝟗𝟗𝟗𝟗𝟏𝟏)
𝟏𝟏𝟏𝟏
= 900.2