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ADF4113 Frequency Synthesizer 驅動程式實作

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原始碼: https://github.com/simenkid/adf4113_driver

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ADF4113 Frequency Synthesizer 驅動程式實作

  1. 1. Chien-Jung Li Nov. 2013 Analog Devices ADF4113 Frequency Synthesizer
  2. 2. 2 Analog Devices ADF4113
  3. 3. 3 ADF4113 Spec. Abstract RF characteristics were not shown, since we are focusing the design of digital interface here. DSN-3019 Spec. (I guess 3.3V DVDD is used in the packaged module)
  4. 4. 4 Timing Diagram 10 ns 10 ns 25 ns 25 ns 10 ns 2 ns It’s quite easy to meet the timing requirement. MSB go first 24-bits
  5. 5. 5 ADF4113 Pin Function Digital Section: 1. 24-bit input shift register / 14-bit R counter / 19-bit N counter (6-bit A counter + 13-bit B counter). 2. Data is clocked into the 24-bit shift register on each rising edge of CLK MSB first. 3. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5.
  6. 6. 6 4 Types of the Latches
  7. 7. 7 R Counter Latch (0, 0) 14-bits div. ratio (0 is not allowed) PFD deadzone cancel (0, 0) normal How LD is set (not important) Not important Byte[2] Byte[1] Byte[0]
  8. 8. 8 N Counter Latch Byte[2] Byte[1] Byte[0]
  9. 9. 9 Function Latch Byte[2] Byte[1] Byte[0] 詳細功能自行閱讀Datasheet
  10. 10. 10 晶片初始化
  11. 11. 11 測試結果 (I) – 初始化 1. Init: 80,00,C3 = 1000, 0000, 0000, 0000, 1100, 0011 2. R = 00,00,28 = 0000, 0000, 0000, 0000, 0010, 1000 3. N = 00,4C,49 = 0000, 0000, 0100, 1100, 0100, 1001 Initial Latch
  12. 12. 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 Div32 Normal ICP0 TCOUNTER0 Fast Lock Disable Normal + RDIV Normal Init Latch 0x8000C3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 R Latch Normal 3 cycleNormal 3 ns 10 Dec 0x000028 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 N LatchGain1 18 Dec76 Dec 0x004C49 P = 32, B = 76, A = 18, R = 10
  13. 13. 13 測試結果 (II) – 設定頻率為2476 MHz Function Latch 1. Func: 80,00,C2 = 1000, 0000, 0000, 0000, 1100, 0010 2. R = 00,00,28 = 0000, 0000, 0000, 0000, 0010, 1000 3. N = 00,4D,31 = 0000, 0000, 0100, 1101, 0011, 0001 A = 12 DecB = 77 Dec R= 10 Dec P= 32 Dec
  14. 14. 14 測試結果 (III) – 更改功能並設新頻率  功能改為LD精度5 Cycles, abp時間1.5ns, 電流量為ICP6, counter控制為43個 PFD cycles, MUX設為除N輸出  頻率改為2423 MHz 1. Func: 9B,50,A2 = 1001, 1011, 0101, 0000, 1010, 0010 2. R = 11,00,28 = 0001, 0001, 0000, 0000, 0010, 1000 3. N = 00,4B,5D = 0000, 0000, 0100, 1011, 0101, 1101 ICP6 (datasheet上的CPI6) 43 PFD Cycles 除N輸出 A = 23 DecB = 75 Dec R= 10 Dec P= 32 Dec
  15. 15. 15 API函數  在main()中可以呼叫以下三種函數來設定Synthesizer  HalSynInit(void):初始化晶片,在main()開頭使用, 只要初始化一次即可(寫在while(1)的super loop外)。  HalSynStart(uint16 rf_Freq):使晶片開始於新設 定的頻率,rf_Freq填入數字即可,單位是MHz。例如要 設定新頻率為2558 MHz,使用HalSynStart(2558)即可。  halSynSetFunc(uint8 funcSet, uint8 mode) : 設 定 晶 片 功 能 , 第 一 欄 填 寫 設 定 之 類 型 ( 見 hal_adf4113.h) , 第 二 欄 填 寫 要 更 改 的 功 能 屬 性 ( 見 hal_adf4113.h)。 extern uint8 HalSynInit(void); extern uint8 HalSynStart(uint16 rf_Freq); extern uint8 halSynSetFunc(uint8 funcSet, uint8 mode);
  16. 16. 16 應用程式main() #include <ioAT89C52.h> #include "hal_adf4113.h" #define BTN1 P3_bit.P3_2 #define BTN2 P3_bit.P3_3 void main() { TriWire_LE = 0; BTN1 = 1; BTN2 = 1; HalSynInit(); while(1) { if (BTN1 == 0) { delayms(50); if (BTN1 == 0){ while(BTN1 == 0); HalSynStart(2476); } } if (BTN2 == 0) { delayms(50); if (BTN2 == 0){ while(BTN2 == 0); halSynSetFunc(ADF4113_SET_LD_PREC, ADF4113_LD_PREC_5CYCLE); halSynSetFunc(ADF4113_SET_ABP, ADF4113_ANTI_WIDTH_1P5NS); halSynSetFunc(ADF4113_SET_CURRENT, ADF4113_ICP6); halSynSetFunc(ADF4113_SET_COUNTER_CONT, ADF4113_TCOUNTER10); halSynSetFunc(ADF4113_SET_MUX, ADF4113_MUX_DIVN_OUT); HalSynStart(2423); } } } } 功能設定可以重複調用,等所有功能都設定完, 最後記得執行HalSynStart()才會送出設定訊號給晶片 3-wire I/O設定在 hal_adf4113.h 裡面

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