This document discusses best practices for PCB design to improve manufacturing reliability. It identifies five common problems: 1) via in pad, 2) QFN center pad issues, 3) incorrect footprints and markings, 4) thermal manufacturing issues, and 5) bill of materials explosions. Each issue is explained in detail with examples of both correct and incorrect design approaches. The document emphasizes that aspects that don't impact larger boards can cause failures at smaller scales, and provides tips for via filling, stencil segmentation, thermal relief, and managing component counts.

1. PCB Design Best Practices for
More Reliable Manufacturing
Duane Benson

2. The Five Most Common Problems
1. Via in pad
2. QFN center pad
3. Footprints and marking
4. Thermal manufacturing issues
5. BOM explosion

3. Why These Issues?
Things that don’t matter at .1” do matter at .01”
15mm / 0.6”
1206
01005

4. Why These Issues?
Things that don’t matter at .1” do matter at .01”
15mm / 0.6”
1206
01005
1mm tip

5. Why These Issues?
Things that don’t matter at .1” do matter at .01”
15mm / 0.6”
1206
01005
0603 package 1mm tip

6. Why These Issues?
Things that don’t matter at
.1” do matter at .01” 2.54mm / 0.1”
0.4mm
1mm tip

7. Why These Issues?
Things that don’t matter at
.1” do matter at .01” 2.54mm / 0.1”
0.4mm
1mm tip

8. Don’t Fear the New Components
New form-factor components come
with a number of challenges, but
they can all be easily overcome

9. FIVE COMMON TRAPS
1. VIA IN PAD

10. Open Via In and Near Pad
BGA

11. Open Via In and Near Pad
Vias in or near BGA pads will cause loss of
solder balls resulting in a failed assembly
First of all: No.
BGA

12. Open Via In and Near Pad
Vias in or near BGA pads will cause loss of
solder balls resulting in a failed assembly
2nd of all: No.
BGA

13. Open Via In and Near Pad
Vias in or near BGA pads will cause loss of
solder balls resulting in a failed assembly
3rd of all: No
BGA

14. Open Via In and Near Pad
Just No
BGA
We salvaged this one, but don’t count on it

15. Open Via In and Near Pad
Filled and plated over at the board house
Copper plugs
Conductive epoxy
Thermal epoxy
The ONLY viable solution for BGA via
in pad is to have the vias filled and
plated over at the PCB fab house

16. Open Via In and Near Pad
QFN, DFN, QFP may require vias in the center
pad for thermal transfer or for grounding.
Open vias are not acceptable.
QFN and DFN

17. Open Via In and Near Pad
QFN, DFN, QFP may require vias in the center
pad for thermal transfer or for grounding.
Open vias are not acceptable.
QFN and DFN

18. Open Via In and Near Pad
More options with QFN/DFN than
with BGAs. Fill, plate or cap
QFN and DFN

19. Open Via In and Near Pad
This may not be acceptable with immersion silver
surface finish due to corrosion. Check with fab house
QFN and DFN

20. Open Via In and Near Pad
QFN and DFN

21. Open Via In and Near Pad
QFN and DFN

22. Open Via In and Near Pad
Passives & others
Insufficient solder on
pad and solder on
back side of PCB

23. Open Via In and Near Pad
Small components are subject to a number of
problems that don’t affect larger parts
Passives & others

24. Open Via In and Near Pad
Basically, just don’t do it.
It can lead to too many
reliability problems.
Passives & others
Insufficient solder on
pad and solder on
back side of PCB
IPC-A-610 Class Zero

25. FIVE COMMON TRAPS
2. QFN CENTER PAD

26. QFN Stencil Layer

27. QFN Stencil Layer
QFN/DFN solder paste stencil opening is
sensitive to a number of factors.
QFN Float

28. QFN Stencil Layer
QFN/DFN solder paste stencil opening is
sensitive to a number of factors.
QFN Float prevented

29. QFN Stencil Layer
QFN/DFN solder paste stencil opening is
sensitive to a number of factors.
QFN Voids

30. QFN Stencil Layer
QFN/DFN solder paste stencil opening is
sensitive to a number of factors.
QFN Voids avoided

31. QFN Stencil Layer
Segment the stencil so solder doesn’t
cover the capped vias.
QFN and DFN
Capped vias will
be in between the
stencil openings
Space for six vias

32. QFN Stencil Layer
Segment the stencil so solder doesn’t
cover the capped vias.
QFN and DFN
How not to do it

33. QFN Stencil Layer

34. QFN Stencil Layer
Stencil layer openings
segmented
Vias between the
openings
QFN and DFN

35. QFN Stencil Layer
Can apply to other components as well

36. FIVE COMMON TRAPS
3. FOOTPRINTS AND MARKINGS

37. Footprint and Marking
While you’re at it, make sure the
footprint matches the copper on the part

38. Footprint and Marking
While you’re at it, make
sure the footprint matches
the copper on the part
It’s important with thru-
hole parts too

39. Footprint and Marking
Diode and capacitor polarity ambiguity can cause
problems in prototype and final assembly

40. Footprint and Marking
Diode and capacitor polarity ambiguity can cause
problems in prototype and final assembly

41. FIVE COMMON TRAPS
4. THERMAL MANUFACTURING ISSUES

42. Thermal Issues
Thermal mass of large
component can cause
uneven paste melt or
component overheating
Thermal inertia

43. Thermal Issues
Thermal inertia

44. Thermal Issues
Thermal inertia

45. Thermal Issues
Thermal inertia

46. Thermal Issues
Thermal mass of large
component can cause
uneven paste melt
Mask too thick
can cause part to
ride up and not
solder well
Tombstoning

47. Thermal Issues
Thermal mass of
larger copper area
(even internal layer)
on one side can cause
uneven paste melt
Tombstoning

48. Thermal Issues
No thermal relief can cause tombstoning
and poor solder joints

49. Thermal Issues
Meets IPC spacing
requirements
But, no mask
between parts. All
open copper (and
no thermal relief)

50. Thermal Issues
Meets IPC spacing
requirements Result

51. Thermal Issues
Meets IPC spacing, has thermal relief but
still has open copper between parts.

52. Thermal Issues
Meets IPC spacing, has thermal relief
and no open copper between parts.

53. Thermal Issues
Meets IPC spacing, has thermal relief
and no open copper between parts.

54. FIVE COMMON TRAPS
5. BOM EXPLOSION

55. BOM Explosion
Feeders may be a
limitation for
projects with large
BOMs.

56. BOM Explosion
R18 can be as low as 1K
If current draw isn’t an
issue, use 27K

57. Summary
• No open vias in pads
• Segment your QFN stencils
• Verify footprints
• Clarify polarities
• Watch for BOM line item creep

58. blog.screamingcircuits.com
For additional layout advice