This document discusses the need for standards in 3D design and manufacturing to facilitate the integration of die from multiple sources and mitigate risks. It proposes leveraging existing standards bodies and industry forums to develop standards in several key areas, including design exchange formats, modeling parameters, bump layout specifications, and metrology and reliability metrics. The document recommends convening expert groups to define a complete list of required design information exchange formats and to propose and champion specific format standards.

1. PAGE 1 QUALCOMM CONFIDENTIAL AND PROPRIETARY
QUALCOMM CONFIDENTIAL AND PROPRIETARYqctconnect.com
3D Design Exchange Formats
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Riko Radojcic DAC 2011
Qualcomm San Diego, CA
E-mail : rikor@qualcomm.com 7 June 2011
Tel : 1 858 651 7235

2. PAGE 2 QUALCOMM CONFIDENTIAL AND PROPRIETARY
3D Standards : Goals & Constraints
3D Technology is, or is Perceived as, a Risk
 Mitigate Risks and Reduce Anxieties through Standards
Focus on Consensus in the Supply Chain
 Do not Infringe on Core Competences of individual entities
 Maximize their ROI
Focus on Near Term Challenges
 Demonstrate Successes (=3D product in production) in Next 3 - 5 years
Focus on Common Denominator Challenges
 e.g. issues faced by Memory on Logic implementation
Facilitate 3D Integration of Die from Multiple Sources
 Action : Standards at the Interfaces between Supply Chain Partners

3. PAGE 3 QUALCOMM CONFIDENTIAL AND PROPRIETARY
General Consensus on Need for Standards
Lot of Talk About Standards
 Design & EDA
 Processes & Metrology
 Footprints & Layouts
 Test & ESD
Many Willing Players
 But no visible Master Plan
Accelerate Standardization Efforts
Divide-and-Conquer the Challenges
Map Efforts to the Best Owners
Status of the 3D Standards : Circa 3 Q 10
GSA
IEEE
SEMATECH
ANSI
Si2
IMEC
JEDEC
SEMI

4. PAGE 4 QUALCOMM CONFIDENTIAL AND PROPRIETARY
3D Standards : Tactical Plan Proposal
 Leverage Existing Standards Bodies
 Established balloting, adoption and management practices
 But formal and hence suitable for a ‘mature proposal’….
 Leverage Existing
Industry 3D Forums
 Existing venues for
involved entities active
in 3D
 But interactive and
hence suitable for a
‘nascent proposal’ …
 Coordinate & Align
Sematech
3D Center
GSA/Si2
3D SiG
SEMI Si2
Design Standards
EDA
SRC
Academia
OSAT
Consortia
i/pi/p
others
Product Drivers
in 2011Process Standards

5. PAGE 5 QUALCOMM CONFIDENTIAL AND PROPRIETARY
Design Domain Standards (1)
Objective: Enable 3D Design Using Commercial (Memory) Die
Standard: Layout of D2D Interconnect for Heterogeneous
Stacks
 e.g. mBump Layout – Standard Size / Pitch Rules for a mBump
 e.g. mBump Array Configuration – Standard Array Shape and Size
 e.g. Pin Assignments – Standard Pin Assignments for Utility Pins
Status : Standard Wide IO DRAM Bump Array – by JEDEC
 mBump Array for WideIO Sponsored by Memory Suppliers
 Expect Adoption in 2011
Technical area Proposer Stds Body
D2D
layout
compatibility
Bump Layout
Die
Suppliers
Single bump size and shape
Bump Array Layout Array size and shape
Bump Assignment e.g. dedicated pins for DFT, Temp Sensors…
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6. PAGE 6 QUALCOMM CONFIDENTIAL AND PROPRIETARY
Design Domain Standards (2)
Technical area Proposer Stds Body
PDK
modeling
compatibility
Electrical model format 3D EC
GSA?
How to manage coupling and stuff
Thermal model format Material properties, char & validation method
Stress model format 3D EC ? Material properties, characterization methods,
Objective: Enable Modeling & Simulation
Standard : Formats for Physical Models
 e.g. Electrical SPICE model of mBump, TSV, BRDL …
 e.g. Thermal & Mechanical Material Property Parameters
Status : Effort underway for Mechanical Stress Modeling
 Sematech/Fraunhofer 3D Stress Workshop Series…
 Peer Review & Acceptance in 2010 & drive into industry in 2011-2011
 No formal activities for others ?
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7. PAGE 7 QUALCOMM CONFIDENTIAL AND PROPRIETARY
Design Domain Standards (3)
Objective: Enable Design/Verification with Existing EDA Tools
Standard: Design Exchange Formats
 For Physical Design & Verification, Timing & Power Simulation, Thermal & Stress
Analyses, DFT, Power Distribution Network design, PathFinding handoff…..
Status : IMEC with DFT / Apache with PDN …
 No activities for others
Technical area Driver Stds Body
Design
designdatabasecompatibility
PF Exchange Formats Atrenta ? Partitioning info, floorplanning info
PV Exchange Format ?? Layer definition, GDS etc for DRC/LVS
Stress Exchange Formats ? ? I/P for stress sim + O/P Stress Map
Temp Exchange Formats ? ? I/P power map + O/P Temp map for timing
PDN Exchange Format ? ? Reduced order compact power model
SI Exchange Format ? ? Equivalent of IBIS-like mod for 3D
DFT Exchange Formats IMEC To enable Scan/JTAG across tiers
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8. PAGE 8 QUALCOMM CONFIDENTIAL AND PROPRIETARY
What is Required – Now
1. A List of Agreed-to Design Exchange Formats
 As required to support Design for Heterogeneous Stacking (e.g. Memory on Logic)
 Propose :
– convene a body of Respected Experts to review and define a complete list of design
information about DieN+1 required for design of DieN for a 3D stack consisting of DieN
and DieN+1
– e.g. what is required information about Wide IO Memory to design the Logic die
underneath it for a 3D Wide IO Memory on Logic stack... With minimum risks …
– Post this List through the usual interested channels (GSA, Si2, 3DEC, Sematech…..) to
solicit input and comments
2. Specific Design Exchange Format Proposals
 As required to eventually get a Convention or a Standard
 Propose :
– Select an Expert to propose and champion a given Exchange Format
– Define a workgroup forum to review and discuss the proposed Exchange Format
– Drive consensus and create a Standard

9. PAGE 9 QUALCOMM CONFIDENTIAL AND PROPRIETARY
Other Standards Activities: in 3D Manufacturing Arena
Standard Driver “Keeper”
Materials
Material
compatibility
Metallurgy pairs
3D EC
Compatible metallurgies
Max dT Safe Operating Area SoA spec for ‘compatible metallurgies
Reliability SoA Rel SoA spec for ‘compatible metallurgies
QA
Incoming
specs
Metrology (e.g. Warpage) 3D EC How to measure warpage– not numbers
Die/wafer QA metrics 3D EC How to measure chips, balls, planarity..
Flow
Handling
specs
Shipping Carrier specs –
Bonded Wafer Pair
3D EC
Shape size, etc required for machines
In-Assembly ESD TBD ?? Requirement & verification
Test
KGD / pre-Bond test IMEC
IEEE
Methodology, Flow, Sacrificial Pads..
Probe Cards IMEC Probe pad formats, etc..
 Other – process related - activities
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