Carl Schattke has over 42 years of experience in PCB design and manufacturing. He started his career soldering in 1967 and began PCB design in 1973. Since then, he has designed over 3,500 PCBs and worked for various companies including Intel, Asic Designs/Tezzaron, and currently Tesla Motors. He is also an instructor for PCB West courses and speaks at IPC conferences. The document discusses the history of PCBs and soldering techniques. It then covers various factors that can contribute to void formation in solder joints, such as surface finish, PCB design, components, solder paste, and reflow process parameters. Different inspection methods for detecting voids

1. Silicon Valley
IPC Designers Council
PCB Design for Soldering
October 15, 2015

3. Who’s you speaker today?
• Carl Schattke, CID, CID+
– Started soldering in 1967
– Started PCB Design in 1973
– Family owned a PCB Manufacturing company
– Family owned PCB Assembly in 1970’s and 1980’s
– Designed over 3,500 PCB’s over 42 years
• Over 130,000 hours of design time
– Owned PCB Design Service Bureau for 10 years
– Asic Designs/Tezzaron – Contract design
– Intel – Network equipment division and Sort Test
– Currently Sr. Lead PCB Designer at Tesla Motors
– PCB West Course Instructor
– IPC/APEX Keynote Speaker
– PCB Design Consultant

4. PCB Design for Solder Joint Reliability
What does a reliable solder joint do?
• Provides a lasting electro-mechanical bond for
the expected lifetime and environment.
What considerations do we need to take into
account?
• Expected lifetime -
• Class of operation -
• Environment – moisture, chemicals, thermal
cycles, extreme temps, vibration, component
stressing

5. PCB Design for Solder Joint Reliability
What does the designer usually control?
Pad Geometry
Processing order
Processing steps
Solder, Solder paste
PCB Surface finishes
PCB Planarity
PCB cleanliness and contamination
PCB storage and procedures for use.
PCB panelazation
PCB Placement
t

6. PCB Design for Solder Joint Reliability
What might the designer NOT usually control?
Component choices
Form factor
Component density
Environment
Assembly expertise
PCB Manufacturer
PCB Quality

7. PCB History
• 1903 Albert Hanson – flat foil laminated to
insulator
• 1904 Thomas Edison Plating conductors onto
linen
• 1913 Arthur Berry patented print and etch
method
• 1927 method of electroplating circuit patterns
• 1936-1947 John Sargrove Electroninc Circuit
making Equipment (ECME) sprayed metal onto
Bakelite

8. PCB History
• 1936 Paul Eisler – First Printed circuit radio set
• ~1940 Harry Rubenstien – Ceramic with
Metallic paint for conductors and carbon
material for resistors
• 1949 -1956 US Army Signal corps Moe
Abramson and Stanislaus Danko component
leads passed through holes to be dip soldered
• 1956 - Wave soldering evolved
• 1980 – SMT started to replace through hole
• 1990-to today smaller fine pitch geometries

9. History of solder joints
• Mechanical Bonds (Not really Solder)
– Wire wrap
– Spring clips
– Nuts and bolts
• Solder joins two metals that do not melt with molten metal
• Solder originally used for jewelry about 5000 years ago in Mesopotamia
Electrical soldering
• Eutectic Solder 63%tin/37% lead melts at 183 Deg C
• and 60%/40%
• Plated Through Holes
• SMT

10. Through-Hole Technology

11. Surface Mount Component Lead Styles
Ball Grid Array Bump Grid Array Land Grid Array Column Grid Array Pillar Grid Array
Flat Side Convex Side Concave Side Corner Concave
Gull Wing J-Lead
Flat Lug
Outward L
Inward L
End Cap Under Body L
Flat Bottom
No-Lead

12. Production Tools
Baking Oven

13. Baking Oven – drives moisture out

14. PCB and Fixture

15. Tooling Fixture

16. Screen Printer

17. Screen Printer

18. Solder paste being applied

19. Large Cassette parts

20. Small Reel parts

21. Tray components

22. Infrared Solder Oven

23. Setup panel for 12 stage oven

24. End of line solder inspection

25. 2D AOI inspection

26. 3D AOI Inspection

27. 3D viewing panel

28. Cold state wave solder machine

30. Wave Solder Liquid Flow State

32. Aqueous wash station

33. Washing machine for PCB’s

34. Solder Pot

35. Solder Pot Crucible

36. Inspection methods of Voids
Wafer printer
Reflow oven
X-ray inspection
Reflow oven
Printer
SMT System Wafer Bumping System
Dage 7600NT
Voiding Inspection Systems in SHENMAO Lab

37. Overview
 Two Main Issues in Assembly
 Factor Analysis for Void Formation
* Surface Finish
* Voids from PCB Design
* Voids from Component
* Voids from Solder Paste
* Voids from Process
 Voids in Bumping Process

38. Types of Voids Description
Macrovoids Voids were formed as volatile ingredients of the fluxes within the
solder paste, usually found everywhere in solder joint.
Planar
Microvoids
Voids generated by anomalies in surface finish application
process, generally located in one plane and found at the solder-to-
land interface.
Shrinkage Voids Caused by the solidification of SAC solders, formed as linear
cracks with rough edges from the surface of the solder joints.
Micro-via Voids Caused by microvias in lands.
Pinhole Voids Voids generated by excursions in the copper plating process at
board supplier.
R. Aspandiar, SMTA Northwest Chapter Meeting (2005)
Something about Voids

39. Something about Voids
Kirkendall Voids
During thermal aging (including temp. cycling), rapid diffusion of one
material into another could cause crystal vacancies to form in the bulk
material, that then leads to risks for reliability failures of solder joints.
SAC
Cu Cu
SAC
Cu3Sn
Cu6Sn5
Cu
SAC
Cu3Sn
Cu6Sn5
 Kirdendall voids were formed in the Cu3Sn because
the Sn and Cu atoms diffused.
 During high temperature storage, two IMCs Cu6Sn5
and Cu3Sn continued to grow and a certain amount
of solder matrix was the different composition
between the voids and neighbor IMCs.
Luhua Xu et al. / Electronics Packaging Technology Conference, IEEE(2005)863–867
Zequn Mei et al. / Electronic Components and Technology Conference, IEEE(2005)415–420

40.  Poor Heat Transfer Rate
 Poor Current Carrying Capability
 Long-term Reliability Concern
 Squeezed Short
 Bump Height Uniformity
Something about Voids
Why don’t we like void?

41. Cross-sectionX-Ray CT Scan
Modern 2D/3D X-Ray
inspection systems are
powerful tools for
finding defects in BGA,
QFN and 3D packages.
Inspection methods of Voids
2D/3D X-ray CT Scan Cross Section
Resolution
Preparation time
Analysis time
Automation
Void Location
Accuracy
Cost
Best
Worst
Moderate

42. Industrial Standards for Voids
Component Criteria Standard
Solder Balls of BGA
components
(Pre-SMT)
< 15% JESD 217
Surface Mount Area Array
(Post-SMT)
< 25% IPC-A-610
QFN, MOSFET, Components
with Bottom Thermal Plane
Terminations
(Post-SMT)
No industrial standard
but often target at < 25%
-

43. Occurrence Rate of Voids
30%
40%
30%
13%
50%
35%
25%
13%
20%
12%
20%
25%
45%
74%
80%
88%
0% 20% 40% 60% 80% 100%
2014
2013
2012
2011
2010
2009
SHENMAO Customer Service Case Studies
MOSFET QFN BGA

44. Factor Analysis of Void
Formation
Contamination
Cleanness
Powder Size
Surface Finish
Printing
Void
PCB
Reflow Profile
Component
Process
Solder paste
Surface
Finish
Design
Activato
r
Pad Design
Reflow Atmosphere
Powder
Oxidation

45. OSP ENIG
2.92% 0.83%
ImSn ImAg
2.72% 1.20%
QFP
Pitch 0.4
mm QFP
Comparison of Different Surface Finish
Surface Finish

46. OSP ENIG
2.92% 0.83%
ImSn ImAg
2.72% 1.20%
QFP
Pitch 0.4
mm QFP
Comparison of Different Surface Finish
Surface Finish

47. 0603 Chip
0603 Chip
OSP ENIG
5.58% 1.54%
ImSn ImAg
5.16% 3.37%
Comparison of Different Surface Finish
Surface Finish

48. BGA
Diameter
0.5 mm
BGA
OSP ENIG
6.38% 0.83%
ImSn ImAg
5.44% 4.17%
Comparison of Different Surface Finish
Surface Finish

49. Mechanism of Voids from ImAg
pad
●: point will be de-wetting
■: Ag film
AgAgAgAg
H2O, CuO, chemical in cave
soldering
cu cu
AgAgAgAg
cave
poor
boundary
ImAg
vacuum
state
pad
●: de-wetting point
→: driving force of solder
→: organic outgasing from flux
voiding
on cave
pad
→: outgasing from H2O, O2 or
chemicals residue
soldering
Large amount of
caves between
ImAg surface and
Cu pad
planar voids near the interface
Surface Finish

50. Key Factors of Voids from ImSn
Discoloration
Low tin thickness Ionic / organic
contaminationNG
*Oxidation on
ImSn surface
*Transform to IMC layer
 Dewetting
*De-wetting
Sn
Cu6Sn5
Cu3Sn
Cu
De-wetting point
Surface Finish
IMC is not good
wetting with solder

51. Surface Finish
Cracks from Planar Voids

52.  Poor filling from stencil printing
 Risk of residue from electroplating
Voids from PCB Design
Via Hole
Typical Microvia Void

53. Traces of flying pin test
A very large void in center of the BGA ball
“Balloon effect“ to form large void
gas expansion
from the pin hole
Voids from Component
Contaminations

54. MOS
Substrate/PCB
Two voiding types can be found in MOS, LGA, or any component with larger
soldering area
1. Gas
2. Non-wetting
MOS
Substrate/PCB
MOS
Substrate/PCB
MOS
Substrate/PCB
MOS
Substrate/PCB
MOS
Substrate/PCB
0. Ideal
MOS
Substrate/PCB
The outer area of the paste will melt first
and then block the inner gas to escape
The minimal soldering with the
component is caused by non-wetting.
Combination of 2 effects
Voids from Component

55. Two types of voids can be found in MOS or LGA, larger soldering area
1. Gas
2. Non-wetting
Irregular Shape
Voids from Component

56. Take QFN for example
Ground Pad:
Four-grid
Ground Pad:
Nine-grid
Ground Pad:
Minus 20% Area
Good: “Window paning” creates vents that results in smaller voids.
Bad: Vent channels resulted in additional “open” areas that reduced solder
joint continuity. However, it can’t eliminate voids completely due to the
surface finish wetting issues.
Voids from Component
Stencil Design
large void size small void size minimized void size

57. Voids from Solder Paste
Solder paste plays an important role in contribution of void.
 High volume of flux  High volume of gas generated
 Large surface area from solder powder
 Rapid chemical reaction in reflow
Water soluble solder pastes tend to cause larger void than no-clean ones.
 Different chemical compound in flux
 Moisture absorption

58. Reflow Simulator
Reflow chamber
Camera 1 (top view)
Camera 2 (side view)
 Customized Reflow Profile
 Customized Atmosphere (Air/N2)
 Monitors what is happening during
reflow.
 Displays two images at the same time
by connecting two sets of CCD cameras.
 Measures the warp caused by thermal
stress
BGA-1 BGA-2
Bumping

59. Flux clean tin oxide
Flux cleans oxide (gas 1)
and activator (gas 2) and
solvent (gas 3) to
generate void
Gas may be trapped
because of the surface tension
of flux and solder
Substrate/PCB
MO
SnO2
Flux
Substrate/PCB
Void
MO + R-COOH→ (R-COO-)M + H2O(g)
Flux cleans oxide (gas 1)
R-COOH + R’OH→ R’-COOR + H2O(g)
Activator (gas 2)
Substrate/PCB
Void
Acid B
Acid C
Halide
Acid A
Mechanism of Void Formation in Reflow
Voids from Solder Paste

60. Substrate
Type 5
(15-25μm)
Substrate
Type 7
(2-12μm)
Smaller Surface Area
Less Flux Reaction
Less Gas Generation
Larger Surface Area
More Flux Reaction
More Gas Generation
Ave. 0.19%
Max. 1.20%
Ave. 9.64%
Max. 13.20%
Powder Size Effect
Voids from Solder Paste

61. According to the reaction, the
more oxidation on the surface,
the more H2O gas formation,
resulting in higher voiding.
Sample Oxygen content
A 334 ppm
B 507 ppm
oxide
↓
A
B
Powder Oxidation Effect
SnOx + RCOOH→ (RCOO)ySn + H2O(g)
oxide
↓
Yellowish
Ave. 0.92%
Max. 2.70%
Ave. 1.86%
Max. 4.90%
Voids from Solder Paste

62. RTS
Profile
RSS
Profile
Long soaking
*Void Growth
RSS < RTS
*Flux outgases on heating.
*Long soaking helps to
reduce voids
 by Increasing outgassing
before solder melts.
RSS profile is more suitable for
larger components because a longer soaking time can achieve thermal uniformity.
It also provides longer time for gas to escape.
Voids from Process
Profile Consideration
Profile Void in
BGA
RTS 6.03%
RSS 2.52%

63. *Void Growth
N2 < Air
N2 prevents powder from
oxidation.
 Reduces gas formation
from flux reaction during
reflow
Ave. 1.41%
Max. 3.00%
Ave. 1.27%
Max. 3.60%
Ave. 2.28%
Max. 5.70%
Ave. 2.26%
Max. 7.10%
In N2 atmosphere, flux
becomes more fluid (lower
surface tension) so that the
gas can escape easily.
Voids from Process
Atmosphere

64. Vacuum Reflow
 Gas evacuates from molten solder easily
 Cycle time is 30-60 sec or longer (in-line reflow oven)
 Costs much more than conventional reflow oven
 Minor risk of splash of flux and solder ball
 Minor risk of small sized component shift
Fluxless Reflow (in Formic Acid Atmosphere)
 No Flux ≈ No Gas Generation
 Cycle time
 Limited cleaning and reduction ability
 Solder balls need to be fixed in (ball attach / bumping / pre-solder) process
Voids from Process

65. Voids in Bumping Process
Dry Film
Opening definition Paste deposition
D
r
y
F
i
l
m
1st reflow &
Dry film removal
Flux spray
Flux dispensing 2nd reflow
Bumping Solder Paste 2nd reflow Flux
Flip Chip
基板
Wafer Bumping
Substrate
PCB
Flux clean solvent
Flip Chip Tacky Flux
BGA Flux
SMT Solder Paste
Substrate Bumping
Bumping Process

66. Voids in Bumping Process
Voids are big challenges for bumping process
Problem from
Production Process
Problem from
Wafer/Substrate
Bad
printing
condition
reflow
condition
Plating
liquid
residue
Poor
wetting
and
oxidation
on pad
Excess (high)
melting
temperature
and meting
time
Excess (high)
speed
heating in
secondary
heating zone
Thick printingMoisture
Shape
design of
dry film

67. Voids in Bumping Process
Solder Paste Design
Flux Conventional New Formula
Rosin 20~50% R1 R1
Activator 0~10% A1+A2 A1+A2+A3
Halide 0~5% H1 H2
Thixotropic 0~10% T1 T2
Solvent 10~25% S1+S2 S2+S3
Conventional
Ave. 3.04%
Max. 7.40%
New Formula
Ave. 1.03%
Max. 3.90%
activity in flux
thixotropic property
viscosity
In-house testing results (piece wafer)

68. Voids in Bumping Process
Wafer Type Dummy Dummy
Paste Conventional New Formula
Dry Film Opening (μm) 150 150
FV bump
void (%)
Sample Size 7500 7500
> 30 1 0
26-30 8 4
21-25 31 10
16-20 56 16
11-15 113 9
Amount Void 209 39
Void Rate (%) 2.78 0.52
Max Void Size 31% 30%
Solder Paste Design
In-Line Testing Results (Full Wafer)

69. 400
450
500
550
600
650
700
750
800
0 1 2 3
ShearStrength(mN)
Reflow
New
Conventional
Voids in Bumping Process
1 2 3 4 5
Shear Strength
Shear strengths dropped after
multiple reflow.
Shear strength of solder bump
increased because of low voiding
from new solder paste formula.
Solder Paste Design
New Formula

70. Solder Paste Conclusions
Design
1. Select a suitable surface finish.
2. Choose right solder powder size.
3. Avoid microvia.
4. Design stencil aperture properly for large ground pad.
Process
1. Control the quality of incoming component and PCB. Low cost is not always
the best!
2. Discuss with solder paste manufacturer for best reflow profile. Or try different
soldering paste.
3. Use Nitrogen reflow or Vacuum reflow if possible.
www.linkedin.com/carlswww.linkedin.com/carls

71. PCB Design Tips
• Land Pattern Construction – IPC 7351B going to
IPC7351C
• Solder mask defined pads – don’t mix and match on
BGAs
• No silkscreen under DFN type components
• Balance copper to pad on both sides
• Allow for gas escape on large pads
• Don’t shadow low profile components
• Heavy parts on top (so they don’t fall off)
• Keep a 3-5mm border along two sides for a working
edge
• Panelize small boards

72. PCB Layout Tips
• Ground Plugs should allow gas to escape
• Allow 3-5 mm gap on bottom side SMT to TH leads.
• If for a prototype do not run in and out of part in
more than one place so it can be cut
• Long SMT connectors need excellent planarity
• Plan wave solder direction plan
• At least 3 Global Fiducials
• 2 local fiducials for fine pitch/BGA/QFPs
• Local fiducials on all small boards in arrays
• Use at least two NPTH Tooling holes

73. Controlling costs
• Reduce setup steps to
save money
• Increase lead pitch
• Plan or Spec PCBA build
process
Cost order:

74. Controlling costs
• Reduce setup steps to
save money
• Increase lead pitch
• Plan or Spec PCBA build
process
Cost order:

75. Future Developments
• New IPC7351C –
– Rounded Rectangle pads – better paste release
– Proportional Padstacks
– Contoured courtyards
– New naming to avoid duplications

76. 3-Tier Pad Stack
Concept
Proportional
Pad Stack
Small Hole
Large
Hole
Same Annular Ring
Proportional
Annular Ring

77. No 3-Tier Library System
IPC-7351C Proportional Pad Stacks

78. IPC-7351C Proportional Pad Stacks

79. IPC-7351B Rectangular Courtyards

80. IPC-7351C Contour Courtyards

81. Rounded Rectangle Pad Shape
• Most Component Manufacturer’s
Recommended Pad Shape is Rectangle
• IPC-SM-782 and IPC-7351B
Recommended Pad Shape is Oblong
• IPC-7351C – Rounded Rectangle Pad
Land Width =
Shortest Side
Maximum Radius =
10 Mil (0.25 mm)
Corner Radius =
25% Land Width
1 Mil (0.01 mm)
Round-off

82. Thank you for participating with
IPC Designers Council today
• Sign up for mailing list
• Silicon Valley Chapter
IPC Designers Council
<ipc-dc-
svc@outlook.com>
• Contact Carl Schattke at
schattke@pacbell.net
Mobil 408-386-7481
www.linkedin.com/in/carls

83. Additional Resources
• https://en.wikipedia.org/wiki/Printed_circuit_board#History
• http://www.empf.org/empfasis/2010/June10/tech_tips_610.html
• http://www.shenmao.com
• www.pcblibraries.com