This document describes implementing the CORDIC algorithm on an FPGA to calculate the sine function. It provides background on FPGAs, the Spartan 3E kit, and the CORDIC algorithm. The CORDIC algorithm uses iterative shifts and additions to calculate trigonometric and other functions. It will implement the CORDIC algorithm on the Spartan 3E FPGA to calculate sine values from input angles provided via keyboard, displaying results on the FPGA's LCD module.
The document describes an ultra-low power asynchronous logic in-situ self-adaptive VDD system for wireless sensor networks. The proposed system uses quasi-delay-insensitive asynchronous logic implemented with pre-charged static logic circuits. It features a self-adaptive VDD scaling system that dynamically adjusts the supply voltage based on processing requirements to minimize power consumption while operating robustly in the sub-threshold voltage region. The system design includes an asynchronous filter bank module powered by the adjustable VDD rail and a power management module that monitors circuit delays to determine the optimal VDD setting.
This document describes the design and implementation of a basic calculator using an LCD display module with an FPGA. It includes objectives to write Verilog code for the calculator logic and driving the LCD display. The design is a simple four-function calculator that takes two single-digit inputs and an operation and displays the result. The document outlines the state machine design and functions for converting values to ASCII format for the LCD. It provides details on interfacing with and controlling the LCD module through its control lines and registers. The implementation in Verilog is described including the top module ports and behavioral simulation steps to test the design functionality.
This document provides details about an EE 329 product design and management project to create a stage light control system. A group of 3 students designed a universal keypad and address selection protocol to control up to 32 remote terminal units for brightness or position. The system allows controlling multiple lights simultaneously or individually in 7 different modes using ergonomic potentiometers and an Arduino-based control panel. Codes for the master control station and remote terminal units are included along with a user guide explaining the operating modes. The project aims to provide an ergonomic, environmentally friendly, and low-cost alternative to existing stage light controllers.
Logic Level Techniques for Power Reduction GargiKhanna1
This document discusses various logic level techniques for low power VLSI design, including:
- Gate reorganization techniques like combining gates to reduce switching activity.
- Signal gating to block propagation of unwanted signals using AND/OR gates or latches.
- Logic encoding methods like gray code counting to reduce bit transitions.
- State machine encoding to lower expected bit transitions in the state register and outputs.
- Precomputation logic that disables inputs to combinational logic when output is invariant, reducing switching activity at the cost of increased area.
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
The aim of project is by using GDI technique the power consumption, delay, chip area and connection and parasitic capacitors is decreased. In this project, we are implementing the new T-flip flop using GDI technique for low power and high speed in order to achieve power delay product (PDP)
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...VLSICS Design
This paper discusses the implementation of digital circuits using the Gate Diffusion Input (GDI) technique for low power design. GDI reduces power dissipation, propagation delay, and area compared to other techniques like Pass Transistors and Transmission Gates. A 4x1 Multiplexer, 8x3 Encoder, BCD Counter, and Mealy Machine were designed using GDI, Pass Transistors, and Transmission Gates. Simulation results showed that circuits implemented with GDI exhibited the lowest power dissipation. Therefore, GDI is an efficient technique for optimizing power in digital circuits.
This document summarizes the management of DS1 data streams between a TI C671x DSP and two Infineon PEB2256 framers on a board. It describes in detail:
1) The interface between the McBSP peripherals on the DSP and the framers, including clocking modes and signal connections.
2) How the EDMA is configured on the DSP to efficiently handle the data streams without burdening the CPU.
3) The programming of registers on the framers and DSP peripherals to correctly format and channelize the T1/E1 data streams for processing by the DSP algorithms.
This document discusses interfacing an LCD display to an 8051 microcontroller. It covers the objectives of connecting an LCD to an 8051, deciding which ports to use, important LCD commands, timing considerations, and writing a subroutine to write data to the LCD. Example pseudo-code is provided to initialize the LCD and display text on the two lines by calling subroutines to write commands and data. Additional steps are needed during hardware testing to fully initialize the LCD. The tasks for the lab involve displaying a workstation number and student IDs on the LCD's two lines.
The document describes an ultra-low power asynchronous logic in-situ self-adaptive VDD system for wireless sensor networks. The proposed system uses quasi-delay-insensitive asynchronous logic implemented with pre-charged static logic circuits. It features a self-adaptive VDD scaling system that dynamically adjusts the supply voltage based on processing requirements to minimize power consumption while operating robustly in the sub-threshold voltage region. The system design includes an asynchronous filter bank module powered by the adjustable VDD rail and a power management module that monitors circuit delays to determine the optimal VDD setting.
This document describes the design and implementation of a basic calculator using an LCD display module with an FPGA. It includes objectives to write Verilog code for the calculator logic and driving the LCD display. The design is a simple four-function calculator that takes two single-digit inputs and an operation and displays the result. The document outlines the state machine design and functions for converting values to ASCII format for the LCD. It provides details on interfacing with and controlling the LCD module through its control lines and registers. The implementation in Verilog is described including the top module ports and behavioral simulation steps to test the design functionality.
This document provides details about an EE 329 product design and management project to create a stage light control system. A group of 3 students designed a universal keypad and address selection protocol to control up to 32 remote terminal units for brightness or position. The system allows controlling multiple lights simultaneously or individually in 7 different modes using ergonomic potentiometers and an Arduino-based control panel. Codes for the master control station and remote terminal units are included along with a user guide explaining the operating modes. The project aims to provide an ergonomic, environmentally friendly, and low-cost alternative to existing stage light controllers.
Logic Level Techniques for Power Reduction GargiKhanna1
This document discusses various logic level techniques for low power VLSI design, including:
- Gate reorganization techniques like combining gates to reduce switching activity.
- Signal gating to block propagation of unwanted signals using AND/OR gates or latches.
- Logic encoding methods like gray code counting to reduce bit transitions.
- State machine encoding to lower expected bit transitions in the state register and outputs.
- Precomputation logic that disables inputs to combinational logic when output is invariant, reducing switching activity at the cost of increased area.
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
The aim of project is by using GDI technique the power consumption, delay, chip area and connection and parasitic capacitors is decreased. In this project, we are implementing the new T-flip flop using GDI technique for low power and high speed in order to achieve power delay product (PDP)
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...VLSICS Design
This paper discusses the implementation of digital circuits using the Gate Diffusion Input (GDI) technique for low power design. GDI reduces power dissipation, propagation delay, and area compared to other techniques like Pass Transistors and Transmission Gates. A 4x1 Multiplexer, 8x3 Encoder, BCD Counter, and Mealy Machine were designed using GDI, Pass Transistors, and Transmission Gates. Simulation results showed that circuits implemented with GDI exhibited the lowest power dissipation. Therefore, GDI is an efficient technique for optimizing power in digital circuits.
This document summarizes the management of DS1 data streams between a TI C671x DSP and two Infineon PEB2256 framers on a board. It describes in detail:
1) The interface between the McBSP peripherals on the DSP and the framers, including clocking modes and signal connections.
2) How the EDMA is configured on the DSP to efficiently handle the data streams without burdening the CPU.
3) The programming of registers on the framers and DSP peripherals to correctly format and channelize the T1/E1 data streams for processing by the DSP algorithms.
This document discusses interfacing an LCD display to an 8051 microcontroller. It covers the objectives of connecting an LCD to an 8051, deciding which ports to use, important LCD commands, timing considerations, and writing a subroutine to write data to the LCD. Example pseudo-code is provided to initialize the LCD and display text on the two lines by calling subroutines to write commands and data. Additional steps are needed during hardware testing to fully initialize the LCD. The tasks for the lab involve displaying a workstation number and student IDs on the LCD's two lines.
This document presents a study comparing different circuit designs for a 1-bit full adder cell, including CMOS, CPL, DPL, and a novel GDI technique. It finds that the GDI technique can reduce power consumption, propagation delay, transistor count, and area compared to conventional CMOS and other pass-transistor logic designs. Schematics and layouts are presented for XOR/XNOR-based full adders implemented using the GDI technique. Simulation results show improvements in area, power, delay, and power-delay product compared to CPL and DPL designs. The GDI technique is concluded to be an effective low-power alternative for digital circuit design.
Implementation of 1 bit full adder using gate diffusion input (gdi) techniqueGrace Abraham
This document discusses the implementation of a 1-bit full adder circuit using the Gate Diffusion Input (GDI) technique. GDI is introduced as a low-power logic design style that can reduce transistor counts, power consumption, and propagation delay compared to traditional CMOS designs. The document first reviews the advantages of GDI and the basic GDI cell functions. It then describes how a conventional CMOS 1-bit full adder works before presenting the design of a XOR-based and GDI-based 1-bit full adder. Transient analysis and comparisons show that the GDI full adder uses fewer transistors and has lower power and delay than traditional CMOS designs. The document concludes that GDI is an
The document summarizes information about liquid crystal displays (LCDs), including:
- LCDs are replacing LED displays due to declining prices, ability to display text/graphics, and ease of programming text/graphics.
- It describes the pin connections and functions of an LCD, including power supply pins, data/command selection pins, data bus pins, and enable pin.
- It provides notes on programming an LCD, including using the busy flag pin to check if the LCD is busy before writing data.
This document discusses various topics related to flip-flops and shift registers including:
1. Flip-flop timing parameters like setup time, hold time, and propagation delay.
2. The JK master-slave flip-flop configuration which uses two flip-flops to avoid unwanted state changes.
3. Switch contact bounce and how an RS latch can be used in a de-bounce circuit.
4. Different representations of flip-flops like truth tables, characteristic tables, and state diagrams.
5. HDL implementations of different types of flip-flops.
6. Shift register types like serial-in serial-out, serial-in parallel-out, parallel-in serial-
This document describes experiments with analog to digital converters (ADCs) using an 8-bit and 10-bit converter to read voltage input and display the results on a 7-segment LED display. It provides algorithms and code for initializing the ADC, taking samples, and performing conversions to extract the digital values for display. Procedures are outlined for 8-bit and 10-bit conversions using interrupts or polling and arithmetic operations to handle the 10-bit values.
The document describes a study and performance analysis of the Modified Gate Diffusion Input (MGDI) technique. It provides details on MGDI logic, including how it overcomes limitations of the Gate Diffusion Input (GDI) technique. Various logic gates and circuits like full adders, flip-flops, and finite state machines are designed using MGDI. Simulation results show that MGDI outperforms GDI and traditional CMOS logic in terms of transistor count, power dissipation, and delay. While self-resetting logic has higher transistor count and power, it provides an alternative to dynamic logic by removing the need for a global clock.
The document summarizes a vertical form fill seal machine that uses a Delta servo drive and motor for the puller application. The Delta ASD-A2 servo drive receives trigger signals from an eye mark sensor and the PLC to start the pulling process. It then completes predefined positioning and sends outputs to the PLC indicating when pulling and masking are complete. The drive uses position latch and compare functions to ensure accurate positional control. Wiring details and specifications for the Delta servo motor and drive are also provided.
Analog to digital converter is one of the most important feature of micro controller. here i am explaining about basic of ADC, working and how exactly controller do it. Here i also explaining registers of ADC and attached a sample code.
This document provides information about various digital circuits including half adder, full adder, encoder, decoder, multiplexer, demultiplexer, seven segment display circuit, clock, flip flop, integrated circuit and more. It defines combinational and sequential circuits. It describes half adder, full adder, encoder, decoder, multiplexer, demultiplexer and seven segment display circuits. It also explains clock, flip flops including SR, D, JK flip flops, integrated circuits and definitions.
An Arithmetic Logic Unit (ALU) is a functional block of any
processor. It is used to perform arithmetical and logical
operations. ALU’s are designed to perform integer based
operations. In this module, we have designed an ALU which
performs certain specific operations on 32 bit numbers.
The arithmetic operations performed are: Addition, subtraction
and multiplication. The logical operations performed are: AND,
OR, XNOR, left shift and right shift.
The behavioral Verilog code and testbench were simulated using
MODELSIM to verify the functionality.
The individual gates (INVERTER, NAND2, NOR2, XOR2, OAI3222,
AOI22, MUX2:1) which constituted to the cell library were laid out
in CADENCE. The DRC and LVS run were successfully completed
to ensure usage. These individual layouts were combined and the
combined DRC was run without any errors.
The D flip flop (DFF) was laid out and the static timing analysis
were done using Waveform viewer and it’s functionality was
verified and the D flip flop times were calculated.
By putting together these cells which were designed, the ALU was
developed and the outputs were obtained.
This document describes the design and implementation of a 0-99 digital BCD counter circuit. The circuit uses a 4026 IC and 7-segment displays to display the count. It can operate in two modes - manually using a switch or automatically using a 555 timer as a clock. The circuit was designed, simulated in Proteus, built on a breadboard, and tested to meet the criteria of counting from 0-99 on two displays.
MX Lap Timer - An automatic stopwatch for MotocrossGuilherme Pohl
This document describes an automatic stopwatch system for motocross using infrared transmission. The system has two main modules: a transmitter module that generates infrared pulses and a main module that calculates lap times, displays data on an LCD, and stores lap times in an SD card. The main module uses an infrared receiver to detect pulses from the transmitter and calculates lap times and performance metrics. Validation testing with an oscilloscope confirmed the system accurately detects transmitted pulses and measures lap times. The stored lap time data can be analyzed with graphs to evaluate a rider's performance over a season.
The document introduces ladder diagrams and their basic components and logic. Ladder diagrams are a graphical programming language used to program programmable logic controllers (PLCs). Each rung represents a program statement with inputs on the left and outputs on the right. The PLC executes the ladder diagram by reading input states and determining output states from top to bottom. The document also describes common logic components like contacts, coils, timers, and counters used in ladder diagrams.
Design and Implementation of DC Motor Speed Control using Fuzzy LogicWaleed El-Badry
This document describes the design and implementation of a fuzzy logic controller for DC motor speed control using a laptop computer. A tachometer is connected to the motor to provide feedback to the controller. The controller is implemented using a .NET class library developed by the author to allow students to easily design fuzzy logic systems. Experimental results show that the fuzzy logic controller is able to control the speed of the DC motor to follow a desired setpoint.
The document describes the DMC-18x6 PCI bus motor controller. It is available with 1 to 8 axes and each axis can be configured for stepper or servo motors. It provides features such as PID compensation, multi-axis coordinated motion, digital and analog I/O, and communication over PCI. Standard motion modes include point-to-point positioning, contouring and electronic gearing.
This document describes using a fuzzy logic controller to control the speed of a DC motor. It begins by introducing fuzzy logic and how it works, explaining linguistic variables and fuzzy sets. It then details the structure of a fuzzy logic controller, including fuzzification to convert real inputs to fuzzy values, an inference engine to apply fuzzy rules, and defuzzification to convert fuzzy outputs to real values. The document provides an example of a temperature control system to illustrate these concepts. It concludes by describing the advantages of fuzzy control over conventional techniques for applications like DC motor speed control.
This document discusses interfacing a 16x2 LCD display with an 8051 microcontroller. It includes sections on LCD components and operation, the 16x2 LCD module pinout and commands, initialization steps, sending data to the LCD, contrast control, timing diagrams for read/write operations, and an example code for interfacing the LCD with 8051 microcontroller ports and registers. The code initializes the LCD, clears the display, positions the cursor, and continuously displays the letters "FAJR".
This presentation provides an overview of microcontrollers and robotics. It discusses the PIC18F4520 microcontroller, including its architecture, features, and programming. Examples are provided of programming LED patterns, 7-segment displays, PWM, and timers using assembly and C languages. Robotics concepts covered include locomotion systems, power supplies, actuators, and control systems. Static and dynamic stability in legged robot locomotion are also explained.
Spectrum analysis characterizes the frequency content of signals. Power spectral estimation methods obtain an approximate estimate of the power spectral density of random processes. Non-parametric power spectral estimation does not assume any data generation process or model, and involves dividing a signal into segments and averaging the periodograms of each segment to reduce variance. Common non-parametric methods include Bartlett's method, Welch's method, and Blackman-Tukey method.
1) The document discusses power spectrum estimation methods for digital signal processing.
2) It describes five common non-parametric power spectrum estimation techniques: periodogram method, modified periodogram method, Bartlett's method, Welch's method, and Blackman-Tukey method.
3) Each method has different tradeoffs between frequency resolution, variance, and bias that make some techniques better for certain applications like feature extraction.
This document presents a study comparing different circuit designs for a 1-bit full adder cell, including CMOS, CPL, DPL, and a novel GDI technique. It finds that the GDI technique can reduce power consumption, propagation delay, transistor count, and area compared to conventional CMOS and other pass-transistor logic designs. Schematics and layouts are presented for XOR/XNOR-based full adders implemented using the GDI technique. Simulation results show improvements in area, power, delay, and power-delay product compared to CPL and DPL designs. The GDI technique is concluded to be an effective low-power alternative for digital circuit design.
Implementation of 1 bit full adder using gate diffusion input (gdi) techniqueGrace Abraham
This document discusses the implementation of a 1-bit full adder circuit using the Gate Diffusion Input (GDI) technique. GDI is introduced as a low-power logic design style that can reduce transistor counts, power consumption, and propagation delay compared to traditional CMOS designs. The document first reviews the advantages of GDI and the basic GDI cell functions. It then describes how a conventional CMOS 1-bit full adder works before presenting the design of a XOR-based and GDI-based 1-bit full adder. Transient analysis and comparisons show that the GDI full adder uses fewer transistors and has lower power and delay than traditional CMOS designs. The document concludes that GDI is an
The document summarizes information about liquid crystal displays (LCDs), including:
- LCDs are replacing LED displays due to declining prices, ability to display text/graphics, and ease of programming text/graphics.
- It describes the pin connections and functions of an LCD, including power supply pins, data/command selection pins, data bus pins, and enable pin.
- It provides notes on programming an LCD, including using the busy flag pin to check if the LCD is busy before writing data.
This document discusses various topics related to flip-flops and shift registers including:
1. Flip-flop timing parameters like setup time, hold time, and propagation delay.
2. The JK master-slave flip-flop configuration which uses two flip-flops to avoid unwanted state changes.
3. Switch contact bounce and how an RS latch can be used in a de-bounce circuit.
4. Different representations of flip-flops like truth tables, characteristic tables, and state diagrams.
5. HDL implementations of different types of flip-flops.
6. Shift register types like serial-in serial-out, serial-in parallel-out, parallel-in serial-
This document describes experiments with analog to digital converters (ADCs) using an 8-bit and 10-bit converter to read voltage input and display the results on a 7-segment LED display. It provides algorithms and code for initializing the ADC, taking samples, and performing conversions to extract the digital values for display. Procedures are outlined for 8-bit and 10-bit conversions using interrupts or polling and arithmetic operations to handle the 10-bit values.
The document describes a study and performance analysis of the Modified Gate Diffusion Input (MGDI) technique. It provides details on MGDI logic, including how it overcomes limitations of the Gate Diffusion Input (GDI) technique. Various logic gates and circuits like full adders, flip-flops, and finite state machines are designed using MGDI. Simulation results show that MGDI outperforms GDI and traditional CMOS logic in terms of transistor count, power dissipation, and delay. While self-resetting logic has higher transistor count and power, it provides an alternative to dynamic logic by removing the need for a global clock.
The document summarizes a vertical form fill seal machine that uses a Delta servo drive and motor for the puller application. The Delta ASD-A2 servo drive receives trigger signals from an eye mark sensor and the PLC to start the pulling process. It then completes predefined positioning and sends outputs to the PLC indicating when pulling and masking are complete. The drive uses position latch and compare functions to ensure accurate positional control. Wiring details and specifications for the Delta servo motor and drive are also provided.
Analog to digital converter is one of the most important feature of micro controller. here i am explaining about basic of ADC, working and how exactly controller do it. Here i also explaining registers of ADC and attached a sample code.
This document provides information about various digital circuits including half adder, full adder, encoder, decoder, multiplexer, demultiplexer, seven segment display circuit, clock, flip flop, integrated circuit and more. It defines combinational and sequential circuits. It describes half adder, full adder, encoder, decoder, multiplexer, demultiplexer and seven segment display circuits. It also explains clock, flip flops including SR, D, JK flip flops, integrated circuits and definitions.
An Arithmetic Logic Unit (ALU) is a functional block of any
processor. It is used to perform arithmetical and logical
operations. ALU’s are designed to perform integer based
operations. In this module, we have designed an ALU which
performs certain specific operations on 32 bit numbers.
The arithmetic operations performed are: Addition, subtraction
and multiplication. The logical operations performed are: AND,
OR, XNOR, left shift and right shift.
The behavioral Verilog code and testbench were simulated using
MODELSIM to verify the functionality.
The individual gates (INVERTER, NAND2, NOR2, XOR2, OAI3222,
AOI22, MUX2:1) which constituted to the cell library were laid out
in CADENCE. The DRC and LVS run were successfully completed
to ensure usage. These individual layouts were combined and the
combined DRC was run without any errors.
The D flip flop (DFF) was laid out and the static timing analysis
were done using Waveform viewer and it’s functionality was
verified and the D flip flop times were calculated.
By putting together these cells which were designed, the ALU was
developed and the outputs were obtained.
This document describes the design and implementation of a 0-99 digital BCD counter circuit. The circuit uses a 4026 IC and 7-segment displays to display the count. It can operate in two modes - manually using a switch or automatically using a 555 timer as a clock. The circuit was designed, simulated in Proteus, built on a breadboard, and tested to meet the criteria of counting from 0-99 on two displays.
MX Lap Timer - An automatic stopwatch for MotocrossGuilherme Pohl
This document describes an automatic stopwatch system for motocross using infrared transmission. The system has two main modules: a transmitter module that generates infrared pulses and a main module that calculates lap times, displays data on an LCD, and stores lap times in an SD card. The main module uses an infrared receiver to detect pulses from the transmitter and calculates lap times and performance metrics. Validation testing with an oscilloscope confirmed the system accurately detects transmitted pulses and measures lap times. The stored lap time data can be analyzed with graphs to evaluate a rider's performance over a season.
The document introduces ladder diagrams and their basic components and logic. Ladder diagrams are a graphical programming language used to program programmable logic controllers (PLCs). Each rung represents a program statement with inputs on the left and outputs on the right. The PLC executes the ladder diagram by reading input states and determining output states from top to bottom. The document also describes common logic components like contacts, coils, timers, and counters used in ladder diagrams.
Design and Implementation of DC Motor Speed Control using Fuzzy LogicWaleed El-Badry
This document describes the design and implementation of a fuzzy logic controller for DC motor speed control using a laptop computer. A tachometer is connected to the motor to provide feedback to the controller. The controller is implemented using a .NET class library developed by the author to allow students to easily design fuzzy logic systems. Experimental results show that the fuzzy logic controller is able to control the speed of the DC motor to follow a desired setpoint.
The document describes the DMC-18x6 PCI bus motor controller. It is available with 1 to 8 axes and each axis can be configured for stepper or servo motors. It provides features such as PID compensation, multi-axis coordinated motion, digital and analog I/O, and communication over PCI. Standard motion modes include point-to-point positioning, contouring and electronic gearing.
This document describes using a fuzzy logic controller to control the speed of a DC motor. It begins by introducing fuzzy logic and how it works, explaining linguistic variables and fuzzy sets. It then details the structure of a fuzzy logic controller, including fuzzification to convert real inputs to fuzzy values, an inference engine to apply fuzzy rules, and defuzzification to convert fuzzy outputs to real values. The document provides an example of a temperature control system to illustrate these concepts. It concludes by describing the advantages of fuzzy control over conventional techniques for applications like DC motor speed control.
This document discusses interfacing a 16x2 LCD display with an 8051 microcontroller. It includes sections on LCD components and operation, the 16x2 LCD module pinout and commands, initialization steps, sending data to the LCD, contrast control, timing diagrams for read/write operations, and an example code for interfacing the LCD with 8051 microcontroller ports and registers. The code initializes the LCD, clears the display, positions the cursor, and continuously displays the letters "FAJR".
This presentation provides an overview of microcontrollers and robotics. It discusses the PIC18F4520 microcontroller, including its architecture, features, and programming. Examples are provided of programming LED patterns, 7-segment displays, PWM, and timers using assembly and C languages. Robotics concepts covered include locomotion systems, power supplies, actuators, and control systems. Static and dynamic stability in legged robot locomotion are also explained.
Spectrum analysis characterizes the frequency content of signals. Power spectral estimation methods obtain an approximate estimate of the power spectral density of random processes. Non-parametric power spectral estimation does not assume any data generation process or model, and involves dividing a signal into segments and averaging the periodograms of each segment to reduce variance. Common non-parametric methods include Bartlett's method, Welch's method, and Blackman-Tukey method.
1) The document discusses power spectrum estimation methods for digital signal processing.
2) It describes five common non-parametric power spectrum estimation techniques: periodogram method, modified periodogram method, Bartlett's method, Welch's method, and Blackman-Tukey method.
3) Each method has different tradeoffs between frequency resolution, variance, and bias that make some techniques better for certain applications like feature extraction.
A spectrum analyzer measures the amplitude of an input signal versus frequency. There are two main types: swept tuned and FFT-based. A swept tuned spectrum analyzer sweeps across frequencies to display all components, while an FFT analyzer digitizes and converts the signal to the frequency domain. Key components are the RF attenuator, mixer, IF gain, filter, detector, video filter, local oscillator, sweep generator and display. It can operate over a wide frequency range at a lower cost than other analyzers, but cannot measure phase or transient events.
non parametric methods for power spectrum estimatonBhavika Jethani
non-parametric methods for power spectrum estimation which includes bartlett method, welch method , blackman and tukey methods and also the comparision of all these methods
The document discusses spectrum analyzers, which measure the magnitude of an input signal versus frequency. It describes the basic components and theory of operation of spectrum analyzers. The key components are the RF input, mixer, IF filter, detector, video filter and local oscillator. It also compares spectrum analyzers to oscilloscopes, describes common measurements, and types of analyzers including Fourier transform and swept analyzers. Finally, it discusses the front panel functions of spectrum analyzers.
The document provides an overview of advanced spectrum analyzer measurements and architecture. It begins with a definition of a spectrum analyzer and its basic components. It then discusses features such as resolution bandwidth, detectors, and measurements over time. The document outlines the evolution of spectrum analyzer capabilities from the 1990s to present. It concludes with descriptions of standard measurements and an introduction to advanced measurements capabilities of modern spectrum analyzers.
Bio-Electronics, Bio-Sensors, Smart Phones, and Health CareJeffrey Funk
Improvements in ICs, MEMS, bio-electronic ICs, and other electronics are enabling a wide range of new solutions for health care. So-called lab-on-a-chip can sense and process many types of biological data and thus help monitor health. Smart phones are becoming an important part of this process as attachments for phones proliferate. Big data services will be necessary to benefit from these new devices.
Frequency Domain Image Enhancement TechniquesDiwaker Pant
The document discusses various techniques for enhancing digital images, including spatial domain and frequency domain methods. It describes how frequency domain techniques work by applying filters to the Fourier transform of an image, such as low-pass filters to smooth an image or high-pass filters to sharpen it. Specific filters discussed include ideal, Butterworth, and Gaussian filters. The document provides examples of applying low-pass and high-pass filters to images in the frequency domain.
This project describes a DC motor speed control system using an STM32 microcontroller. The speed of the DC motor is measured by an optocoupler encoder and sent to the controller. The user can set the target speed using push buttons. The controller then adjusts the motor speed using PWM output to try and match the target speed. The current and target speeds are displayed on an LCD screen.
This document describes how to interface an LCD display with an 8051 microcontroller kit. It provides details on the LCD module including its pinout, commands, initialization process, and sending data. It also includes the circuit diagram showing how the LCD is connected to the microcontroller ports and includes components for backlight control and contrast adjustment. The aim is to understand the interface between an LCD display and the 8051 microcontroller.
The document describes an embedded controller evaluation board that contains an AT89C51ED2 microcontroller, LEDs, switches, an LCD display, serial interface, ADC, DAC, RTC, and other peripherals. It provides instructions on applying power, serial communication, and examples of programs to blink LEDs, use timers to delay and toggle an LED, interface with the LCD display, and read a 4x4 keypad. The goal is to help users understand the capabilities of the microcontroller and experiment with its various features.
This document discusses clock sources and peripheral modules on the ZedBoard. It describes the different clock sources available, including a 100 MHz on-board oscillator. It also shows how to generate clocks of different frequencies using clock division. As an example, it demonstrates connecting and driving a seven segment display Pmod peripheral module to display digits using time multiplexing at a rate of 50 Hz or faster.
Here are the key steps for how SPI works:
1. The master device initiates the data transfer by selecting a slave device using the chip select (CS) line. This brings the slave device online.
2. The master outputs the clock signal (SCLK) which is used by both the master and slave devices to synchronize the data transfer.
3. The master sends data on the MOSI (master out, slave in) line which the slave receives on its SDI pin in sync with the clock.
4. In parallel, the slave sends data on the MISO (master in, slave out) line which the master receives on its SDO pin, also in sync with the clock.
This document describes an energy saving visitor counter project that uses a microcontroller and infrared sensors. The objective is to design a circuit that can count the number of people entering and exiting a room and control the room light accordingly. It uses an IR transmitter and receiver to detect movement and increments or decrements the counter value, which is displayed on seven-segment displays. The microcontroller controls the counting and display functionality while receiving input from the IR sensors. Proteus and Keil software are used to simulate and program the microcontroller respectively.
The correct 8-bit encoding for 5 volts given an analog input range of 0-15 volts is:
01010000
To get this encoding using successive approximation:
1) Start with the most significant bit (MSB) of 128 set: 10000000
2) Compare analog input (5V) to half scale (7.5V): 5V < 7.5V so keep MSB reset
3) Move to next bit and divide range in half: 01001000
4) Compare input (5V) to new half scale (5.625V): 5V > 5.625V so set this bit
5) Repeat for each bit until the input voltage is approximated
This document discusses interfacing a 16x2 LCD display module to an 8051 microcontroller. It provides the pin connections between the LCD and microcontroller, describes the LCD commands used to control the display, and includes two code examples in C language to initialize and write text to the LCD.
This document discusses processor design, including custom single-purpose processors and general-purpose processors. It covers topics such as combinational and sequential logic design, finite state machine design, optimizing custom processors by improving the original program, finite state machine with datapath, and datapath and finite state machine. General-purpose processors are also introduced, including their basic architecture consisting of a control unit and datapath.
This document describes a digital alarm clock designed and implemented on an Artix7 FPGA development board using Verilog HDL. The clock displays time in hours, minutes and seconds using 8 seven-segment displays and blinks the decimal point LED between hour and minute display. It allows the user to set the current time and alarm time using buttons and has functionality for clock setting, alarm setting and an alarm alert indicator LED or sound. The design was tested successfully using hardware on the FPGA board and some minor issues were addressed. Future work proposed includes modifying the clock format and adding a date display.
This document describes a moving message display circuit using an AVR microcontroller and 16x2 LCD. It uses an ATmega16 microcontroller connected to the LCD via its ports. The software program demonstrates scrolling text across the LCD continuously. The program initializes the LCD, clears the display, defines the text to show, and uses a for loop to scroll it at a defined rate while waiting between iterations. Compiling the code generates a hex file that can be programmed onto the microcontroller.
This document describes a low power pipelined FFT processor architecture based on the Radix-4 single delay commutator (R4SDC) algorithm. It implements and compares 16, 64, and 256-point FFT architectures using conventional R4SDC, a complex multiplier, and a multiplier-less architecture based on common subexpression technique. For the 16-point FFT, an ordered R4SDC architecture is proposed that reorders coefficients and inputs to minimize switching activity and reduce power consumption compared to the conventional design. Simulation results show the area and power requirements of the different architectural implementations.
This document describes the implementation of a Snake game on an FPGA board using Verilog. The game logic and hardware description are written in Verilog. Key components include a Xilinx Zybo Zynq-7000 FPGA board connected to a VGA monitor. Verilog code is used to generate the VGA signals and implement the snake game logic including movement, boundaries, scoring, and reset. The design is tested through simulation and implemented on the FPGA board.
This document discusses JK flip-flops and their applications in counters and seven segment displays. It describes the structure of a JK flip-flop, including its inputs of J, K, PR, CLR and CLK, and its outputs of Q and Q'. It explains the four modes of operation for a JK flip-flop: hold, set, reset, and toggle. Counters are described as using multiple flip-flops connected in series to count pulses. Seven segment displays are discussed as a way to display numbers visually using an arrangement of LED segments, with drivers needed to interpret BCD input for the display.
The 4-bit CPU was designed to execute 18 distinct operations from a lookup table. It was tested by executing an instruction set that performed operations like load, store, add, and jump instructions. The accumulator and program counter displays were observed after each instruction to verify the correct operations. Various components like a RAM, ALU, program counter, and decoders were used in the design. The group members demonstrated different parts of the instruction set to verify the CPU was functioning properly.
For the optimization of given network, VHDL
/Verilog code convert into BLIF / BLIF_MV (Berkeley
Logic Interchange Format /Berkeley Logic Interchange
Format for multi-valued network ) format with the help of
VIS / Vl2mv tool of Berkeley. In this paper, we optimize on
a number of standard industrial benchmark circuit by
MVSIS and ABC tool.
The document provides instructions for a unit assignment involving simplification of logic expressions using the Variable Elimination Method (VEM) technique. It lists 3 steps - 1) simplify an expression using VEM, 2) obtain the minimal product, 3) simplify another expression using VEM. It then provides 4 logic expressions that need simplification.
This document provides instructions for additional functions on the Casio fx-570MS and fx-991MS calculators. It covers mathematical expression calculations, complex number calculations, scientific function calculations, and more. Key functions include replay copy to combine expressions, using CALC memory to quickly perform calculations with variables, and the SOLVE function to solve expressions directly without transforming them. Engineering symbols can be turned on for scientific calculations.
This document discusses testing and programming the ADF4113 frequency synthesizer chip. It shows initialization code, setting the frequency and function registers through API calls, and an example main program that initializes the chip and allows changing the output frequency and function settings through buttons. Initialization sets the frequency to 2476 MHz, and pressing button 2 changes settings like loop bandwidth and current before setting a new frequency of 2423 MHz. The API functions HalSynInit(), HalSynStart(), and halSynSetFunc() are used to control the chip.
This document describes a 10-bit 165MSPS video ADC. It uses a time-interleaved SAR architecture with multiple low-power SAR ADCs operating in parallel to achieve the high sampling rate. Each SAR ADC samples every nth cycle, resulting in an effective sampling rate that is n times higher than an individual ADC. The design achieves low power consumption and area through its digital nature and use of scaled CMOS technology. It provides offset correction through a calibration technique to improve accuracy for video applications.
1. IMPLEMENTATION OF CORDIC
ALGORITHM ON FPGA
HDL MINI PROJECT
Submitted By: PANDU RANGA M (M150213EC)
VIVEK KUMAR SHUKLA (M150149EC)
NIT CALICUT
2. 1
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
IMPLEMENTATION OF CORDIC
ALGORITHM ON FPGA
HDL MINI PROJECT
ABSTRACT
The aim of this project is to implement the Cordic Algorithm on FPGA for calculation of sine
function. CORDIC (Coordinate Rotation Digital Computer) is a method for computing functions
like trigonometric, exponential and other elementary mathematical functions. Cordic algorithm
will be implemented on FPGA using Spartan 3E kit. The input angle will be taken from
keyboard and result will be shown LCD module of the Spartan 3E kit.
THEORY
FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a
customer or a designer after manufacturing – hence "field-programmable".
FPGAs are programmable digital logic chips. What that means is that it can be programmed to
do almost any digital function. A computer can be used to describe a "logic function" or else one
can draw a schematic, or create a text file describing the function, doesn't matter.
SPARTAN 3E compile the "logic function" on computer, using software provided by the FPGA
vendor. That creates a binary file that can be downloaded into the FPGA.
SPARTAN 3E connect a cable from a computer to the FPGA, and download the binary file to
the FPGA. It can download FPGAs as many time as we want - no limit - with different
functionalities every time if we want.
FPGAs lose their functionality when the power goes away (like RAM in a computer that loses its
content). we have to re-download them when power goes back up to restore the functionality.
3. 2
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family
and provides a convenient development board for embedded processing applications.
Spartan-3E FPGA specific features-
Parallel NOR Flash configuration
MultiBoot FPGA configuration from Parallel NOR Flash PROM
SPI serial Flash configuration
Embedded development
Micro Blaze™ 32-bit embedded RISC processor
Pico Blaze™ 8-bit embedded controller
DDR memory interfaces
2-line, 16-character LCD screen
PS/2 mouse or keyboard port
50 MHz clock oscillator
Eight discrete LEDs
Four slide switches
Four push-button switches
ABOUT CORDIC ALGORITHM
CORDIC (Coordinate Rotation Digital Computer) is a method for computing elementary
functions using minimal hardware such as shifts, adds/subs and compares.
CORDIC works by rotating the coordinate system through constant angles until the angle is
reduces to zero. The angle offsets are selected such that the operations on X and Y are only shifts
and adds
This section describes the mathematics behind the CORDIC algorithm.
The CORDIC algorithm performs a planar rotation. Graphically, planar rotation means
Y
X
(Xj, Yj)
(Xi, Yi)
4. 3
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
transforming a vector (Xi, Yi) into a new vector (Xj, Yj).
Using a matrix form, a planar rotation for a vector of (Xi, Yi) is defined as
i
i
j
j
Y
X
Y
X
cossin
sincos
(1)
The q angle rotation can be executed in several steps, using an iterative process. Each step
completes a small part of the rotation. Many steps will compose one planar rotation. A single
step is defined by the following equation:
n
n
nn
nn
n
n
Y
X
Y
X
cossin
sincos
1
1
(2)
Equation 2 can be modified by eliminating the ncos factor.
n
n
n
n
n
n
n
Y
X
Y
X
1tan
tan1
cos
1
1
(3)
Equation 3 requires three multiplies, compared to the four needed in equation 2.
Additional multipliers can be eliminated by selecting the angle steps such that the tangent of a
step is a power of 2. Multiplying or dividing by a power of 2 can be implemented using a simple
shift operation.
The angle for each step is given by
nn
2
1
arctan (4)
All iteration-angles summed must equal the rotation angle q.
0n
nnS (5)
where
1;1 nS (6)
This results in the following equation for ntan
n
nn S
2tan (7)
Combining equation 3 and 7 results in
5. 4
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
n
n
n
n
n
n
n
n
n
Y
X
S
S
Y
X
12
21
cos
1
1
(8)
Besides for the ncos coefficient, the algorithm has been reduced to a few simple shifts and
additions. The coefficient can be eliminated by pre-computing the final result. The first step is to
rewrite the coefficient.
nn
2
1
arctancoscos (9)
The second step is to compute equation 9 for all values of ‘n’ and multiplying the results, which
we will refer to as K.
607253.0
2
1
arctancos
1
0
n
n
P
K (10)
K is constant for all initial vectors and for all values of the rotation angle, it is normally referred
to as the congregate constant. The derivative P (approx. 1.64676) is defined here because it is
also commonly used.
We can now formulate the exact calculation the CORDIC performs.
sincos
sincos
iij
iij
XYKY
YXKX
(11)
Because the coefficient K is pre-computed and taken into account at a later stage, equation 8 may
be written as
n
n
n
n
n
n
n
n
Y
X
S
S
Y
X
12
21
1
1
(12)
or as
n
n
nnn
n
n
nnn
XSYY
YSXX
2
1
2
1
2
2
(13)
At this point a new variable called ‘Z’ is introduced. Z represents the part of the angle q which
has not been rotated yet.
n
i
inZ
0
1 (14)
For every step of the rotation Sn is computed as a sign of Zn.
6. 5
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
01
01
n
n
n
Zif
Zif
S (15)
Combining equations 5 and 15 results in a system which reduces the not rotated part of angle q to
zero.
Or in a program-like style:
For n=0 to [inf]
If (Z(n) >= 0) then
Z(n + 1) := Z(n) – arctan(1/2^n);
Else
Z(n + 1) := Z(n) + arctan(1/2^n);
End if;
End for;
The atan(1/2^i) is pre-calculated and stored in a table. [inf] is replaced with the required number
of iterations, which is about 1 iteration per bit (16 iterations yield a 16bit result).
If we add the computation for X and Y we get the program-like style for the CORDIC core.
For n=0 to [inf]
If (Z(n) >= 0) then
X(n + 1) := X(n) – (Yn/2^n);
Y(n + 1) := Y(n) + (Xn/2^n);
Z(n + 1) := Z(n) – atan(1/2^n);
Else
X(n + 1) := X(n) + (Yn/2^n);
Y(n + 1) := Y(n) – (Xn/2^n);
Z(n + 1) := Z(n) + atan(1/2^n);
End if;
End for;
This algorithm is commonly referred to as driving Z to zero. The CORDIC core computes:
0,sincos,sincos,, iiiiiiiijjj ZXZYPZYZXPZYX
7. 6
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
LCD Display
LCD (Liquid Crystal Display) screen is an electronic display module and find a wide range of
applications. A 16x2 LCD display is very basic module and is very commonly used in various
devices and circuits. These modules are preferred over seven segments and other multi segment
LEDs. The reasons being: LCDs are economical; easily programmable; have no limitation of
displaying special & even custom characters (unlike in seven segments), animations and so on.
A 16x2 LCD means it can display 16 characters per line and there are 2 such lines. This LCD has
two registers, namely, Command and Data.
The command register stores the command instructions given to the LCD. A command is an
instruction given to LCD to do a predefined task like initializing it, clearing its screen, setting the
cursor position, controlling display etc. The data register stores the data to be displayed on the
LCD. The data is the ASCII value of the character to be displayed on the LCD.
Following diagram shows the ASCII value of each character that can be displayed on LCD.
Initialization of Display
The initialization sequence is simple and ideally suited to the highly-efficient 8-bit picoblaze
embedded controller. After initialization, the PicoBlaze controller is available for more complex
control or computation beyond simply driving the display.After power-on, the display must be
initialized to establish the required communication protocol.
Power-On Initialization-
The initialization sequence first establishes that the FPGA application wishes to use the four-bit
data interface to the LCD as follows:
1. Wait 15 ms or longer, although the display is generally ready when the FPGA finishes
configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
2. Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
3. Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
4. Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
8. 7
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
5. Wait 100 μs or longer, which is 5,000 clock cycles at 50 MHz.
6. Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
7. Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
8. Write SF_D<11:8> = 0x2, pulse LCD_E High for 12 clock cycles.
9. Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
Display Configuration-
After the power-on initialization is completed, the four-bit interface is now established. The
next part of the sequence configures the display:
1. Issue a function set command, 0x28, to configure the display for operation on the
Spartan-3E Starter Kit board.
2. Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
3. Issue a Display On/Off command, 0x0C, to turn the display on and disables the
cursor and blinking.
4. Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock cycles)
after issuing this command.
Writing Data to the Display
The board uses a 4-bit data interface to the character LCD. The following figures illustrates a
write operation to the LCD, showing the minimum times allowed for setup, hold, and enable
pulse length relative to the 50 MHz clock (20 ns period) provided on the board.
Figure 1: Timing diagram to show write operation
9. 8
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
DESIGN AND DESCRIPTION
Parallel/Cascaded CORDIC Architecture
Combinational circuit
� More Delay, but processing time is reduced as compared to iterative circuit.
� Shifters are of fixed shift, so they can be implemented in the wiring.
� Constants can be hardwired instead of requiring storage space.
FIGURE 2:PARALLEL CORDIC
Parallel Pipelined CORDIC Architecture
Parallel CORDIC can be pipelined by inserting registers between the adders stages.
In most FPGA architectures there are already registers present in each logic cell, so pipeline
registers has no hardware cost.
Number of stages after which pipeline register is inserted can be modeled, considering clock
frequency of system.
10. 9
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
When operating at greater clock period power consumption in later stages reduces due to lesser
switching activity in each clock period.
SCHEMATIC DIAGRAM
VHDL CODE
For cordic algorithm(sine)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use work.packint.all;
entity cordic_algorithm is
port(clk,reset:in std_logic;
11. 10
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
angle :in std_logic_vector(15 downto 0);--angle in radians qformat Q13
sine:out std_logic_vector(15 downto 0) --value in Q14
);
end cordic_algorithm;
architecture Behavioral of cordic_algorithm is
signal
x,x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14:std_logic_vector(15
downto 0):=(others=>'0');
signal
y,y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14:std_logic_vector(15
downto 0):=(others=>'0');
signal
temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp9,temp10,temp11:std_logic
_vector(15 downto 0):=(others=>'0');
signal temp12,temp13,temp14,temp15:std_logic_vector(15 downto
0):=(others=>'0');
signal acc1,
acc2,acc3,acc4,acc5,acc6,acc7,acc8,acc9,acc10,acc11,acc12:std_logic_vector(15
downto 0):=(others=>'0');
signal acc13,acc14,acc15:std_logic_vector(15 downto 0):=(others=>'0');
signal sine_result:std_logic_vector(31 downto 0);
begin
process(reset,clk)
begin
if(reset = '1') then
acc2<=x"0000";
acc3<=x"0000";
acc4<=x"0000";
acc5<=x"0000";
acc6<=x"0000";
acc7<=x"0000";
acc8<=x"0000";
acc9<=x"0000";
18. 17
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
SIMULATION WAVEFORM
SYNTHESIS REPORT
Final Report
=====================================================================
Final Results
RTL Top Level Output File Name : cordic_algorithm.ngr
Top Level Output File Name : cordic_algorithm
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 34
Cell Usage :
# BELS : 2398
# GND : 1
# INV : 34
# LUT1 : 19
# LUT2 : 436
# LUT3 : 368
# LUT4 : 59
# MUXCY : 841
19. 18
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
# VCC : 1
# XORCY : 639
# FlipFlops/Latches : 642
# FDC : 212
# FDE : 430
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 33
# IBUF : 17
# OBUF : 16
# MULTs : 1
# MULT18X18SIO : 1
=====================================================================
Device utilization summary:
Selected Device : 3s500efg320-4
Number of Slices: 461 out of 4656 9%
Number of Slice Flip Flops: 642 out of 9312 6%
Number of 4 input LUTs: 916 out of 9312 9%
Number of IOs: 34
Number of bonded IOBs: 34 out of 232 14%
Number of MULT18X18SIOs: 1 out of 20 5%
Number of GCLKs: 1 out of 24 4%
20. 19
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
VHDL CODE TO INTERFACE LCD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.packint.all;
entity lcd is
port(clk, reset : in std_logic;
SF_D : out std_logic_vector(3 downto 0);
LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic);
end lcd;
architecture behavior of lcd is
signal display_byte:std_logic_vector(19 downto 0):=(others=>'0');
signal m:std_logic_vector(7 downto 0);
signal radian: std_logic_vector(15 downto 0):=x"0000";
signal valueout: std_logic_vector(15 downto 0):=x"0000";
type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold,
fortyus, done);
signal tx_state : tx_sequence := done;
signal tx_byte : std_logic_vector(7 downto 0);
signal tx_init : std_logic := '0';
type init_sequence is (idle, fifteenms, one, two, three, four, five, six,
seven, eight, done);
signal init_state : init_sequence := idle;
signal init_init, init_done : std_logic := '0';
signal i : integer range 0 to 750000 := 0;
signal i2 : integer range 0 to 2000 := 0;
signal i3 : integer range 0 to 82000 := 0;
signal SF_D0, SF_D1 : std_logic_vector(3 downto 0);
21. 20
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
signal LCD_E0, LCD_E1 : std_logic;
signal mux : std_logic;
type display_state is (init, function_set,entry_set, set_display,
clr_display, pause, set_addr, char_sign, char_1, char_dot,
char_2,char_3,char_4,char_5, done);
signal cur_state : display_state := init;
signal binary_int:integer;
signal inter :std_logic_vector(31 downto 0);
signal inter2:std_logic_vector(31 downto 0);
begin
m<=x"3C";--input angle for calculation of value
degreetoradian_unit:entity work.degreetoradian port map(m,radian);
cordic_unit:entity work.cordic_algorithm port map(clk,reset,radian,valueout);
binary_int<=binary_to_int(valueout);
inter<=convert_bin(binary_int);
inter2<=divide(inter,x"000003E8");
bcdunit:entity work.binary_bcd port map(clk,reset,inter2,display_byte);
SF_CE0 <= '1'; --disable intel strataflash
LCD_RW <= '0'; --write only
--The following "with" statements simplify the process of adding and removing
states.
--when to transmit a command/data and when not to
with cur_state select
tx_init <= '0' when init | pause | done,
'1' when others;
--control the bus
with cur_state select
mux <= '1' when init,
'0' when others;
--control the initialization sequence
22. 21
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
with cur_state select
init_init <= '1' when init,
'0' when others;
--register select
with cur_state select
LCD_RS <= '0' when function_set|set_display|clr_display|set_addr|entry_set,
'1' when others;
display: process(clk, reset)
begin
if(reset='1') then
cur_state <= function_set;
elsif(clk='1' and clk'event) then
case cur_state is
when init => if(init_done = '1') then
cur_state <= function_set;
else
cur_state <= init;
end if;
when function_set => tx_byte <= "00101000";
if(i2 = 2000) then
cur_state <= entry_set;
else
cur_state <= function_set;
end if;
when entry_set => tx_byte <= "00000110";
if(i2 = 2000) then
cur_state <= set_display;
else
cur_state <= entry_set;
23. 22
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
end if;
when set_display => tx_byte <= "00001100";
if(i2 = 2000) then
cur_state <= clr_display;
else
cur_state <= set_display;
end if;
when clr_display => tx_byte <= "00000001";
i3 <= 0;
if(i2 = 2000) then
cur_state <= pause;
else
cur_state <= clr_display;
end if;
when pause =>
else if(i3 = 82000) then
cur_state <= set_addr;
i3 <= 0;
cur_state <= pause;
i3 <= i3 + 1;
end if;
when set_addr => tx_byte <= "10000000";
if(i2 = 2000) then
cur_state <= char_sign;
else
cur_state <= set_addr;
end if;
when char_sign =>
if(i2 = 2000) then
cur_state <= char_1;
else
24. 23
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
if(valueout(15)='1') then
tx_byte<=X"2D";
elsif(valueout(15)='0') then
tx_byte<=X"2B";
cur_state <= char_sign;
end if;
end if;
when char_1=>
if(i2 = 2000) then
cur_state <= char_dot;
else
if(valueout(14)='0') then
tx_byte<=X"30";
elsif(valueout(14)='1') then
tx_byte<=X"31";
cur_state <= char_sign;
end if;
cur_state <= char_1;
end if;
when char_dot => tx_byte<=X"2E";
if(i2 = 2000) then
cur_state <= char_2;
else
cur_state <= char_dot;
end if;
when char_2 =>tx_byte<=x"3"&display_byte(15 downto 12);
if(i2 = 2000) then
cur_state <= char_3;
else
cur_state <= char_2;
end if;
25. 24
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
when char_3 => tx_byte<=x"3"&display_byte(11 downto 8);
if(i2 = 2000) then
cur_state <= char_4;
else
cur_state <= char_3;
end if;
when char_4 => tx_byte<=x"3"&display_byte(7 downto 4);
if(i2 = 2000) then
cur_state <= char_5;
else
cur_state <= char_4;
end if;
when char_5 => tx_byte<=x"3"&display_byte(3 downto 0);
if(i2 = 2000) then
cur_state <= done;
else
cur_state <= char_5;
end if;
when done => cur_state <= done;
end case;
end if;
end process display;
with mux select
SF_D <= SF_D0 when '0', --transmit
SF_D1 when others; --initialize
with mux select
LCD_E <= LCD_E0 when '0', --transmit
LCD_E1 when others; --initialize
--specified by datasheet
transmit : process(clk, reset, tx_init)
26. 25
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
begin
if(reset='1') then
tx_state <= done;
elsif(clk='1' and clk'event) then
case tx_state is
when high_setup => --40ns
LCD_E0 <= '0';
SF_D0 <= tx_byte(7 downto 4);
if(i2 = 2) then
tx_state <= high_hold;
i2 <= 0;
else
tx_state <= high_setup;
i2 <= i2 + 1;
end if;
when high_hold => --230ns
LCD_E0 <= '1';
SF_D0 <= tx_byte(7 downto 4);
if(i2 = 12) then
tx_state <= oneus;
i2 <= 0;
else
tx_state <= high_hold;
i2 <= i2 + 1;
end if;
when oneus =>
LCD_E0 <= '0';
if(i2 = 50) then
tx_state <= low_setup;
i2 <= 0;
else
28. 27
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
end if;
when done =>
end case;
end if;
end process transmit LCD_E0 <= '0';
if(tx_init = '1') then
tx_state <= high_setup;
i2 <= 0;
else
tx_state <= done;
i2 <= 0;
end if;
;
--specified by datasheet
power_on_initialize: process(clk, reset, init_init) --power on initialization
sequence
begin
if(reset='1') then
init_state <= idle;
init_done <= '0';
elsif(clk='1' and clk'event) then
case init_state is
when idle => init_done <= '0';
if(init_init = '1') then
init_state <= fifteenms;
i <= 0;
else
init_state <= idle;
i <= i + 1;
29. 28
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
end if;
when fifteenms => init_done <= '0';
if(i = 750000) then
init_state <= one;
i <= 0;
else
init_state <= fifteenms;
i <= i + 1;
end if;
when one => SF_D1 <= "0011";
LCD_E1 <= '1';
init_done <= '0';
if(i = 11) then
init_state<=two;
i <= 0;
else
init_state<=one;
i <= i + 1;
end if;
when two =>
LCD_E1 <= '0';
init_done <= '0';
if(i = 205000) then
init_state<=three;
i <= 0;
else
init_state<=two;
i <= i + 1;
end if;
when three =>
SF_D1 <= "0011";
30. 29
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
LCD_E1 <= '1';
init_done <= '0';
if(i = 11) then
init_state<=four;
i <= 0;
else
init_state<=three;
i <= i + 1;
end if;
when four =>
LCD_E1 <= '0';
init_done <= '0';
if(i = 5000) then
init_state<=five;
i <= 0;
else
init_state<=four;
i <= i + 1;
end if;
when five =>
SF_D1 <= "0011";
LCD_E1 <= '1';
init_done <= '0';
if(i = 11) then
init_state<=six;
i <= 0;
else
init_state<=five;
i <= i + 1;
end if;
when six =>
31. 30
IMPLEMENTATIONOFCORDICALGORITHMONFPGA|16-Nov-15
LCD_E1 <= '0';
init_done <= '0';
if(i = 2000) then
init_state<=seven;
i <= 0;
else
init_state<=six;
i <= i + 1;
end if;
when seven =>
SF_D1 <= "0010";
LCD_E1 <= '1';
init_done <= '0';
if(i = 11) then
init_state<=eight;
i <= 0;
else
init_state<=seven;
i <= i + 1;
end if;
when eight =>
LCD_E1 <= '0';
init_done <= '0';
if(i = 2000) then
init_state<=done;
i <= 0;
else
init_state<=eight;
i <= i + 1;
end if;
when done =>