Paper presented at NoCArc'17, October 15, 2017, Boston, MA, USA © 2017 paper URL: https://dl.acm.org/doi/10.1145/3139540.3139544

1. On Error Injection for NoC Platforms:
A UVM-based Practical Case Study
Sameh El-Ashry1, Hala Ibrahim2, Moamen A. Ibrahem2, Mostafa Khamis3,
Ahmed Shalaby4, Mohamed AbdElsalam3,
M. Watheq El-Kharashi1
1Department of Computer and Systems Engineering, Ain Shams University, Cairo, Egypt
2Department of Communications and Electronics, Faculty of Engineering, Alexandria University, Alexandria, Egypt
3Mentor Graphics, Cairo, Egypt
4Department of Computer Science, Faculty of Computers and Informatics, Benha University, Egypt
NoCArc'17, October 15, 2017, Boston, MA, USA © 2017

2. NoCArc'17, October 15, 2017, Boston, MA, USA © 2017
Outline
◎ Motivation.
◎ Introduction.
◎ Related Work.
◎ Proposed UVM Error Injection Methodologies.
1. Faulty UVM Sequence Item or Transaction.
2. Faulty UVM Reference Model.
3. Bus Error-Injector Agent between Routers.
◎ Case Studies.
1. A Base Router.
2. A Configurable Router: Daniel Router.
◎ Proposed UVM Architecture to Support Error Injection Techniques.
1. Modifications Made to a Typical SB Structure.
2. Simulation Results: Actual Response.
◎ Conclusion.
◎ Future Work.
◎ References.
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Motiviation
Why?
How?
• To test the reliability of any
system.
• To help verification engineers
design dependable UVM
scoreboards to detect errors.
• Decide on the feasibility of
error injection techniques
with NoC platforms.
• By using UVM environment
to both inject and detect the
errors.
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Why UVM (Universal Verification Methodology)?
We want to check
that NoC systems
meet design
specifications.
We build verification
environments to validate the
reliability of NoC different
architectures.
We inject errors to
verify that the system
either handles them or
ignores them.
We cannot use traditional
testbenches because NoCs
are complex and scalable
systems.
We use UVM as it
contains generic
components that
can be reused.
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Traditional
Universal Verification Methodology (UVM)
 UVM:
- A complete verification environment composed of reusable verification
components.
- Needs no re-construction when design under test (DUT) changes.
- A comprehensive methodology of constrained-random, coverage-driven
verification.
* Basic UVM, Verification Academy.
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Dependences between faults, errors, and
failure
 Modern device scaling results in deep sub-micron noises, which cause
interconnects errors to be more dominant and harder to predict, and result
in new error sources.
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Hardware-level detectable errors types
 Correctable errors. Correction is typically made through encoding schemes
at the physical layer level.
 Non-correctable, but recoverable errors. Recovery is done through data
retransmission, managed by higher-level protocol layers.
 Non-correctable, irrecoverable errors. These errors are detected and
reported to software layers through a set of status registers and error-
triggered interrupts.
 State-confusing errors. Such errors lead to undefined system state,
requiring a physical hardware reset to recover.
Hardware-level detectable errors can also be
classified to design, operational, and
algorithmic errors.
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8. Error
Injection
Directions
Design errors could pass verification tests and
manifest suddenly at runtime, causing state
malfunction, data loss, and software
application or entire system failure.
Operational errors by corrupting
a predetermined percentage of
the data transferred between
routers.
Algorithmic errors depend on the
failure of an algorithm to perform
its required task correctly.
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Related Work1
 Steinberg proposed a typical memory model that is configured to store
data with a Verilog-based error injector to inject errors to verify the soft
error scenarios in modern digital RTL circuits [1].
 A comprehensive fault-tolerant verification platform is presented in [2]. It
is used to characterize the impact of fault attribute on error coverage. It
introduced a tool performing fault injection into VHDL models at chip-level,
register-level, and gate-level using the built-in commands of the RTL
simulator.
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Related Work2
 A custom verification system is designed to evaluate the application
behavior on embedded microprocessors under faulty conditions [3], The
fault injection block is part of the DUT itself.
 Error injection techniques are surveyed in [4]. Hardware based fault
injection, Software-based fault injection, Simulation based fault injection,
and Emulation-based fault injection.
 To the best of our knowledge, no previous work has discussed error
injection in NoC several architectures. This makes our work the first to
cover how error injection is carried out and detected in NoC designs.
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Proposed UVM Error Injection
Methodologies
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Faulty UVM Sequence Item or Transaction (Method 1)
 This method can be considered as negative testing that sends
meaningless or non-interpretable data formats to the NoC environment.
 It is implemented through building wrong sequences in the test layer and
applying them to the NoC environment.
 After that, the DUT’s response is checked in a newly-built scoreboard
(SB), named “Error Detection SB”.
 To implement this method, we have to be fully aware of the router’s
architecture, used algorithms, and various parameters.
Targeted
layer
Scoreboard
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Faulty UVM Reference Model (Method 2)
 A router might suffer from any type of faults during runtime. So, a proper
validation of the network performance is carried out through modeling
runtime errors that happen in a single router by inserting a SystemVerilog
faulty router that has an issue with one or more of the router’s used
algorithm-based blocks.
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Bus Error-Injector Agent between Routers (Method 3)
 In this methodology, the UVM architecture is modified and the
connection made on the top level file for the NoC is altered.
 Instead of using normal Verilog wires, we use SystemVerilog interface
and the new interface is passed to a new agent called bus injector
agent.
 As a result, we can disable or enable the bus injector at any place in
the network through the UVM Configuration file.
 Through this agent, we can block the data flow between the routers
and inject errors.
 Injecting errors here is done through generating cycle delays or
corrupting the data itself.
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Case Studies
A Base Router A Configurable
Router: Daniel Router
Input port
East
West
North
South
Local
Output port
East
West
North
South
Local
ReqCntReqUpstr
GntUpstr
FullUpstr
PacketIn
ReqDnstr
GntDnstr
FullDnstr
PacketOut
GntCnt
Packet
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A Base Router Packet format Vs Daniel Router
Packet format
Base Router Packet Format
Daniel Router Packet Format
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A Base Router [5]
 Injecting errors through a faulty sequence item or transaction is done
through generating meaningless or Out-Of-Range (OOR) data.
 Injecting errors through a faulty UVM reference model is done through
connecting a faulty SystemVerilog router.
 Using a bus error-injector agent between routers, we are able to monitor
the flowing data between routers with prior knowledge of the packet
format. We are now able to corrupt data by applying delay or portion
masking.
 The error severity can vary when more important fields of the packet bits
are affected. Most probably, the impact of these errors is not predictable.
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A Configurable Router: Daniel Router [7]
 Injecting errors through a faulty sequence item or transaction does
not differ greatly from that in the base router; differences are due
to architecture and data format variations that add new meaningful
fields to Daniel Router.
 Injecting errors through a faulty UVM reference model is done
through more important modules that can be modified to give a
faulty behavior, such as virtual channel allocation.
 Using a bus error-injector agent between routers, the methodology
will be more noticeable in Daniel Router, because the channel bits
have a higher percentage of meaningful and dedicated information
specified in the channel and flit fields.
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UVM for Router Vs UVM for NoC

Proposed UVM environment for Router[8]
Proposed UVM environment for NOC[6]
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Proposed UVM Architecture to Support Error
Injection Techniques
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Simulation Results: Actual Response (Base Router)
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Simulation Results: Actual Response (Daniel Router)
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Conclusions
 This paper presented reusable mechanisms for NoC error-injection
using UVM.
 A novel methodology of error injection based on bus-injector is
proposed to detect NoC transmission errors in the simulation
environment.
 Verification plan for negative scenarios are applied to two NoC case
studies and results are evaluated to detect and check the error
severity in the UVM SB.
 Experimental results show the efficiency of proposed techniques
when adopting them using UVM.
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Future Work
 Our future work would investigate the evaluation of error-injection
effect on the NoC performance metrics, such as latency and
throughput.
 It will also determine error severity levels through the functional
coverage while, varying different NoC parameters.
 Holding a comparative evaluation between differently applied error
injection methodologies with varying different NOC parameters.
Detect a runtime errors in the Hardware Emulation by a runtime
UVM monitors as the emulation will give us the ability to run the
UVM environment while prototyping the Network on Chip in a real
Hardware Emulation.
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References
[1] D. Steinberg, “Constrained random error injection for functional verification”, US
Patent NO. 8,595,680, 2013.
[2] Y. Y. Chen and G. E. Jan, “Development of scenario-based fault injection
platform and its application study”, Tamkang Journal of Science and Engineering,
Vol. 13, No. 2, 2010, pp. 205–214.
[3] B. Ustaoglu and B. Ors, “Design and implementation of a custom verification
environment for fault injection and analysis on an embedded microprocessor”,
Technological Advances in Electrical, Electronics and Computer Engineering
(TAEECE), 2015.
[4] H. Ziade, "A survey on fault injection techniques", The International Arab
Journal of Information Technology (IAJIT), vol. 1, no. 2, 2004, pp. 171–186.
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References
[5] M. S. Sayed, A. Shalaby, M. El-Sayed, and V. Goulart ,“Flexible router
architecture for network-on-chip”, Computers & Mathematics with Applications, 64
(5),1301–1310, 2012.
[6] A. S. Eissa, M. A. Ibrahem, M. A. Elmohr, Y. Zamzam, A. El-Yamany,
S. El-Ashry, M. Khamis, and A. Shalaby, “A reusable verification environment for
NoC Platforms using UVM” in Proceedings of 17th IEEE International Conference
on Smart Technologies (EUROCON), 2017.
[7] D. U. Becker, N. Jiang, G. Michelogiannakis, and W. J. Dally, “Adaptive
backpressure: Efficient buffer management for On-Chip Networks,” in Proceedings
of the 30th IEEE International Conference on Computer Design (ICCD), 2012, pp.
419–426.
[8] A. El-Naggar, E. Massoud, A. Medhat, H. Ibrahim, B. Al-Abassy, S. El-Ashry,
M. Khamis, and A. Shalaby,“A Narrative of UVM testbench environment for
interconnection routers: A practical approach”, in Proceedings of the 11th
International Design & Test Symposium (IDT), 2016, pp. 98-103.
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27. Thanks for your attention
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28. Questions?