This document summarizes a new fault injection approach for testing network-on-chip (NoC) architectures. The approach uses a dual-processor system on an FPGA to inject faults into a NoC design under test and evaluate the effects. Faults are injected by modifying the FPGA configuration memory to physically implement different fault models. The approach allows testing of routing and logic resources without intrusive test modules. Experimental results demonstrate the effectiveness of classifying faults in a mesh NoC case study implemented on the FPGA.
Fault Injection Approach for Network on Chipijsrd.com
Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption. However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows evaluating the fault tolerance capability of NoCs. Presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows investigating the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale.
There is no doubt that network coding is a promising enhancement of routing to improve network throughput and provide high reliability. However, there are several open problems in practical network coding, especially on how to guarantee coding advantage for a decentralized control network without the knowledge of the network topology. The biggest benefit of OpenFlow is to decouple the control plane from the data plane, allowing the centralized forwarding decisions in comparison to traditional distributed control network. As a result, we propose a Software-Defined coding network and address key technical challenges in practice. We design NC-OF, a framework to enable networking coding in SDN networks, and use MMF-NC coding strategy proposed by Guan Xu in NC-OF. Finally, we proved that our solutions can effectively improve network performance through simulation experiments. And we also find that network coding is not necessary when the link bandwidth is enough , because it will bring the problems of time delay, the increase in the amount of calculation and so on.
HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKSijngnjournal
As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high
performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it
more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA
Controller Area Network is an ideal serial bus design suitable for modern embedded system based networks. It finds its use in most of critical applications, where error detection and subsequent treatment on error is a critical issue. CRC (Cyclic Redundancy Check) block was developed on FPGA in order to meet the needs for simple, low power and low cost wireless communication. This paper gives a short overview of CRC block in the Digital transmitter based on the CAN 2.0 protocols. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. This technique is also sometimes applied to data storage devices, such as a disk drive. In this paper a technique to model the error detection circuitry of CAN 2.0 protocols on reconfigurable platform have been discussed? The software simulation results are presented in the form of timing diagram.FPGA implementation results shows that the circuitry requires very small amount of digital hardware. The Purpose of the research is to diversify the design methods by using VHDL code entry through Modelsim 5.5e simulator and Xilinx ISE8.3i.The VHDL code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Sparten3 FPGA .Here, Simulation and Synthesized results are also presented to verify the functionality of the CRC -16 Block. The data rate of CRC block is 250 kbps .Estimated power consumption and maximum operating frequency of the circuitry is also provided.
Greetings from IGeekS Technologies ….
We were humbled to receive your enquiry regarding your academic project. We assure you to give all kinds of guidance for you to successfully complete your project.
IGeekS Technologies is a company located in Bangalore, India. We have being recognized as a quality provider of hardware and software solutions for the student’s in order carry out their academic Projects. We offer academic projects at various academic levels ranging from graduates to masters (Diploma, BCA, BE, M. Tech, MCA, M. Sc (CS/IT)). As a part of the development training, we offer Projects in Embedded Systems & Software to the Engineering College students in all major disciplines.
Academic Projects
As a part of our vision to provide a field experience to young graduates, we offering academic projects to MCA/B.Tech/BE/M.Tech/BCA students. Normally our way of project guidance will start with in-depth training. Why because unless and until a student know the technology, he cannot implement a project. We designed such courses based on industry requirements.
Placements
Our support never ends with training. We are maintaining a dedicated consulting division with 5 HR executives to assist our students to find good opportunities. Once a student finishes his course and project, immediately we will collect their profiles and will contact with the companies. Since January 2010, more than 450 students got placed with the help of our quality training, project assistance and placement support.
Facilities
• Project confirmation and completion certificate.
• Project base paper, synopsis and PPT.
• In-depth training by industry experts
• Project guidance from experienced people
• Regular seminars and group discussions
• Lab facility
• Good placement assistance
• A CD which contains all the required softwares and materials.
• Lab modules with 100s of examples to improve students programming skills.
Please visit our websites for further information:-
www.makefinalyearproject.com
www.igeekstechnoloiges.com
We look forward to have you in our office for a detailed technical discussion for in-depth understanding of the base paper and synopsis. Our training methodology includes to first prepare the candidates to the relevant technology used in the selected project and then start the project implementation; this gives the candidate the pre-requisite knowledge to understand not only the project but also the code in which the project is implemented.The program concludes by issuing of project completion certificate from our organization.
We attached the proposed project titles for the academic year 2015. Find the attachment. Select the titles we will send the synopsis and base paper...If have any own topic (base paper) pls send us.we will check and confirm the implementation.
We will explain the base paper and synopsis, for technical discussion or admission contact Mr. Nandu-9590544567.
Optimization of Remote Core Locking Synchronization in Multithreaded Programs...ITIIIndustries
This paper proposes the algorithms for optimization of Remote Core Locking (RCL) synchronization method in multithreaded programs. The algorithm of initialization of RCL-locks and the algorithms for threads affinity optimization are developed. The algorithms consider the structures of hierarchical computer systems and non-uniform memory access (NUMA) to minimize execution time of RCLprograms. The experimental results on multi-core computer systems represented in the paper shows the reduction of RCLprograms execution time.
Fault Injection Approach for Network on Chipijsrd.com
Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption. However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows evaluating the fault tolerance capability of NoCs. Presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows investigating the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale.
There is no doubt that network coding is a promising enhancement of routing to improve network throughput and provide high reliability. However, there are several open problems in practical network coding, especially on how to guarantee coding advantage for a decentralized control network without the knowledge of the network topology. The biggest benefit of OpenFlow is to decouple the control plane from the data plane, allowing the centralized forwarding decisions in comparison to traditional distributed control network. As a result, we propose a Software-Defined coding network and address key technical challenges in practice. We design NC-OF, a framework to enable networking coding in SDN networks, and use MMF-NC coding strategy proposed by Guan Xu in NC-OF. Finally, we proved that our solutions can effectively improve network performance through simulation experiments. And we also find that network coding is not necessary when the link bandwidth is enough , because it will bring the problems of time delay, the increase in the amount of calculation and so on.
HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKSijngnjournal
As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high
performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it
more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA
Controller Area Network is an ideal serial bus design suitable for modern embedded system based networks. It finds its use in most of critical applications, where error detection and subsequent treatment on error is a critical issue. CRC (Cyclic Redundancy Check) block was developed on FPGA in order to meet the needs for simple, low power and low cost wireless communication. This paper gives a short overview of CRC block in the Digital transmitter based on the CAN 2.0 protocols. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. This technique is also sometimes applied to data storage devices, such as a disk drive. In this paper a technique to model the error detection circuitry of CAN 2.0 protocols on reconfigurable platform have been discussed? The software simulation results are presented in the form of timing diagram.FPGA implementation results shows that the circuitry requires very small amount of digital hardware. The Purpose of the research is to diversify the design methods by using VHDL code entry through Modelsim 5.5e simulator and Xilinx ISE8.3i.The VHDL code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Sparten3 FPGA .Here, Simulation and Synthesized results are also presented to verify the functionality of the CRC -16 Block. The data rate of CRC block is 250 kbps .Estimated power consumption and maximum operating frequency of the circuitry is also provided.
Greetings from IGeekS Technologies ….
We were humbled to receive your enquiry regarding your academic project. We assure you to give all kinds of guidance for you to successfully complete your project.
IGeekS Technologies is a company located in Bangalore, India. We have being recognized as a quality provider of hardware and software solutions for the student’s in order carry out their academic Projects. We offer academic projects at various academic levels ranging from graduates to masters (Diploma, BCA, BE, M. Tech, MCA, M. Sc (CS/IT)). As a part of the development training, we offer Projects in Embedded Systems & Software to the Engineering College students in all major disciplines.
Academic Projects
As a part of our vision to provide a field experience to young graduates, we offering academic projects to MCA/B.Tech/BE/M.Tech/BCA students. Normally our way of project guidance will start with in-depth training. Why because unless and until a student know the technology, he cannot implement a project. We designed such courses based on industry requirements.
Placements
Our support never ends with training. We are maintaining a dedicated consulting division with 5 HR executives to assist our students to find good opportunities. Once a student finishes his course and project, immediately we will collect their profiles and will contact with the companies. Since January 2010, more than 450 students got placed with the help of our quality training, project assistance and placement support.
Facilities
• Project confirmation and completion certificate.
• Project base paper, synopsis and PPT.
• In-depth training by industry experts
• Project guidance from experienced people
• Regular seminars and group discussions
• Lab facility
• Good placement assistance
• A CD which contains all the required softwares and materials.
• Lab modules with 100s of examples to improve students programming skills.
Please visit our websites for further information:-
www.makefinalyearproject.com
www.igeekstechnoloiges.com
We look forward to have you in our office for a detailed technical discussion for in-depth understanding of the base paper and synopsis. Our training methodology includes to first prepare the candidates to the relevant technology used in the selected project and then start the project implementation; this gives the candidate the pre-requisite knowledge to understand not only the project but also the code in which the project is implemented.The program concludes by issuing of project completion certificate from our organization.
We attached the proposed project titles for the academic year 2015. Find the attachment. Select the titles we will send the synopsis and base paper...If have any own topic (base paper) pls send us.we will check and confirm the implementation.
We will explain the base paper and synopsis, for technical discussion or admission contact Mr. Nandu-9590544567.
Optimization of Remote Core Locking Synchronization in Multithreaded Programs...ITIIIndustries
This paper proposes the algorithms for optimization of Remote Core Locking (RCL) synchronization method in multithreaded programs. The algorithm of initialization of RCL-locks and the algorithms for threads affinity optimization are developed. The algorithms consider the structures of hierarchical computer systems and non-uniform memory access (NUMA) to minimize execution time of RCLprograms. The experimental results on multi-core computer systems represented in the paper shows the reduction of RCLprograms execution time.
FPGA IMPLEMENTATION OF DEBLOCKING FILTER CUSTOM INSTRUCTION HARDWARE ON NIOS-...VLSICS Design
This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOSII processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.
Design and Implementation Of Packet Switched Network Based RKT-NoC on FPGAIJERA Editor
In this Paper we proposed a new network on chip that handles accurate localization of the faulty parts of NoC. The proposed NoC is based on new error detection mechanism and modified xy routing algorithm. Error detection mechanism suitable for dynamic NoCs, where the number and position of the processor elements or faulty blocks vary during run time. This paper also presents a modified xy routing algorithm combined with a scheduler to be used on NoCs.This proposed method is fast way to transferring data via specific path between two nodes in the network and the scheduler further helps to avoid collision. More latency and fewer throughputs are obtained with contentation in network. As mesh size increases latency and throughputs increases accordingly. The proposed design implemented in SPARTAN III FPGA by using Xilinx ISE13.4and simulated in Questa sim 10.0b.
MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER ...VLSICS Design
The use of asynchronous design approaches to construct digital signal processing (DSP) systems is a
rapidly growing research area driven by a wide range of emerging energy constrained applications such
as wireless sensor network, portable medical devices and brain implants. The asynchronous design
techniques allow the construction of systems which are samples driven, which means they only dissipate
dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous
design over conventional synchronous circuits allows them to be energy efficient. However the
implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industrystandard
synchronous design tools and modelling languages. This paper devises a novel asynchronous
design for a finite impulse response (FIR) filter, an essential building block of DSP systems, which is
synthesizable and suitable for implementation using conventional synchronous systems design flow and
tools. The proposed design is based on a modified version of the micropipline architecture and it is
constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been
developed on an FPGA, and systematically verified. The results prove correct functionality of the novel
design and a superior performance compared to a synchronous FIR implementation. The findings of this
work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and
performance benefits.
In this talk, we will explain the functioning of Wireless LANs in theory and in practice.
We will present the IEEE 802.11 standard in general and MAC protocols in particular, by discussing the functions of MAC sublayer management entity and the MAC layer frames in detail.
We will discuss the changes in the states of a WiFi client as it goes through the process of WiFi communication.
Towards the end, we will briefly talk about various vantage points ( at the client side as well as in the air ) that allow us to capture network traffic.
Software Defined Networking: A Concept and Related IssuesEswar Publications
SDN (Software Defined Networking) is the networking architecture that has gained attention of researchers in recent past. It is the future of programmable networks. Traditional networks were very complex and difficult to manage. SDN is going to change this by offering a standard interface (OpenFlow) between the control plane and the networking devices (data plane). Its implementation is fully supported by software so that we can control the behavior of networking devices through programmatic control. This programmatic control provides various new ways to find breakpoints and failures in networking devices. Today SDN has become an important part of networking, so it is important to emulate its behavior. SDN support virtualization which makes it scalable and flexible. Data traffic resides in the data plane. The main function of intelligent controller is to decide the routing
policy and manage the traffic in data plane. So effectively SDN emerges as a networking architecture that has the ability to solve all problems those were found in traditional architecture In this paper the authors discussed historical perspective of SDN, languages that support SDN, emulation tools, security issues with SDN and advantages that makes SDN suitable choice for today’s network.
Black Box Model based Self Healing Solution for Stuck at Faults in Digital Ci...IJECEIAES
The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
To Get any Project for CSE, IT ECE, EEE Contact Me @ 09666155510, 09849539085 or mail us - ieeefinalsemprojects@gmail.com-Visit Our Website: www.finalyearprojects.org
Arteris network on chip: The growing cost of wiresArteris
Arteris NoC SoC Interconnect presentation given by Jonah Probell at ARM Technology Conference 9-11 Nov 2010. Explains how traditional AXI fabrics require huge numbers of wires and leads to routing congestion, and how network on chip interconnects address routing congestion by allowing fewer wires. Explains the basics of NoC packetization and serialization.
FPGA IMPLEMENTATION OF DEBLOCKING FILTER CUSTOM INSTRUCTION HARDWARE ON NIOS-...VLSICS Design
This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOSII processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.
Design and Implementation Of Packet Switched Network Based RKT-NoC on FPGAIJERA Editor
In this Paper we proposed a new network on chip that handles accurate localization of the faulty parts of NoC. The proposed NoC is based on new error detection mechanism and modified xy routing algorithm. Error detection mechanism suitable for dynamic NoCs, where the number and position of the processor elements or faulty blocks vary during run time. This paper also presents a modified xy routing algorithm combined with a scheduler to be used on NoCs.This proposed method is fast way to transferring data via specific path between two nodes in the network and the scheduler further helps to avoid collision. More latency and fewer throughputs are obtained with contentation in network. As mesh size increases latency and throughputs increases accordingly. The proposed design implemented in SPARTAN III FPGA by using Xilinx ISE13.4and simulated in Questa sim 10.0b.
MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER ...VLSICS Design
The use of asynchronous design approaches to construct digital signal processing (DSP) systems is a
rapidly growing research area driven by a wide range of emerging energy constrained applications such
as wireless sensor network, portable medical devices and brain implants. The asynchronous design
techniques allow the construction of systems which are samples driven, which means they only dissipate
dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous
design over conventional synchronous circuits allows them to be energy efficient. However the
implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industrystandard
synchronous design tools and modelling languages. This paper devises a novel asynchronous
design for a finite impulse response (FIR) filter, an essential building block of DSP systems, which is
synthesizable and suitable for implementation using conventional synchronous systems design flow and
tools. The proposed design is based on a modified version of the micropipline architecture and it is
constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been
developed on an FPGA, and systematically verified. The results prove correct functionality of the novel
design and a superior performance compared to a synchronous FIR implementation. The findings of this
work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and
performance benefits.
In this talk, we will explain the functioning of Wireless LANs in theory and in practice.
We will present the IEEE 802.11 standard in general and MAC protocols in particular, by discussing the functions of MAC sublayer management entity and the MAC layer frames in detail.
We will discuss the changes in the states of a WiFi client as it goes through the process of WiFi communication.
Towards the end, we will briefly talk about various vantage points ( at the client side as well as in the air ) that allow us to capture network traffic.
Software Defined Networking: A Concept and Related IssuesEswar Publications
SDN (Software Defined Networking) is the networking architecture that has gained attention of researchers in recent past. It is the future of programmable networks. Traditional networks were very complex and difficult to manage. SDN is going to change this by offering a standard interface (OpenFlow) between the control plane and the networking devices (data plane). Its implementation is fully supported by software so that we can control the behavior of networking devices through programmatic control. This programmatic control provides various new ways to find breakpoints and failures in networking devices. Today SDN has become an important part of networking, so it is important to emulate its behavior. SDN support virtualization which makes it scalable and flexible. Data traffic resides in the data plane. The main function of intelligent controller is to decide the routing
policy and manage the traffic in data plane. So effectively SDN emerges as a networking architecture that has the ability to solve all problems those were found in traditional architecture In this paper the authors discussed historical perspective of SDN, languages that support SDN, emulation tools, security issues with SDN and advantages that makes SDN suitable choice for today’s network.
Black Box Model based Self Healing Solution for Stuck at Faults in Digital Ci...IJECEIAES
The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
To Get any Project for CSE, IT ECE, EEE Contact Me @ 09666155510, 09849539085 or mail us - ieeefinalsemprojects@gmail.com-Visit Our Website: www.finalyearprojects.org
Arteris network on chip: The growing cost of wiresArteris
Arteris NoC SoC Interconnect presentation given by Jonah Probell at ARM Technology Conference 9-11 Nov 2010. Explains how traditional AXI fabrics require huge numbers of wires and leads to routing congestion, and how network on chip interconnects address routing congestion by allowing fewer wires. Explains the basics of NoC packetization and serialization.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Design and implementation of secured agent based NoC using shortest path rout...IJECEIAES
Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Performance analysis and implementation of modified sdm based noc for mpsoc o...eSAT Journals
Abstract To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability,
system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based
MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based
NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing
based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient
SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.
Keywords: NoC, MPSoC, FPGA, NoCs, SDM Based NoC
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
The processor designing and development was designed to perform various complex logical information exchange and processing operations in a variety of resolutions. They mainly rely on concurrent and sync, both that of the software and hardware to enhance the productivity and performance. With the high speed growth approaching multi-billion transistor integration era, some of the main problems which are symbolized by all gate lengths in the range of 60-90 nm, will be from non-scalable delays generated by wire. All similar problems may be solved by using Network on Chip (NOC) systems. In the presented paper, we have summarized research papers and contributions in NOC area. With advancement in the technology in the on chip communication, faster interaction between devices is becoming vital. Network on Chip (NOC) can be one of the solutions for faster on chip communication. For efficient link between devices of NOC, routers are needed. This paper also reviews implementation of routing techniques. The use of routing gives higher throughput as required for dealing with complexity of modern systems. It is mainly focused on the routing design parameters on both system level including traffic pattern, network topology and routing algorithm, and architecture level including arbitration algorithm.
Area-Efficient Design of Scheduler for Routing Node of Network-On-ChipVLSICS Design
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIPVLSICS Design
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
A efficacy of different buffer size on latency of network on chip (NoC)journalBEEI
Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.
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The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
Low power network on chip architectures: A surveyCSITiaesprime
Mostly communication now days is done through system on chip (SoC) models so, network on chip (NoC) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
1. IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834, p- ISSN: 2278-8735. Volume 5, Issue 2 (Mar. - Apr. 2013), PP 01-06
www.iosrjournals.org
New Fault Injection Approach for Network on Chip
Tapas Patel
Gujarat technological University, Gujarat, India
Abstract: Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively
replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better
performances and lower power consumption. However, modern generations of MP-SoCs have an increasing
sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault
sensitivity in NoC architectures, there is the need of accurate test solution which allows to evaluate the fault
tolerance capability of NoCs. This paper presents an innovative test architecture based on a dual-processor
system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed
methods since it is based on a NoC physical implementation which allows to investigate the effects induced by
several kind of faults thanks to the execution of on-line fault injection within all the network interface and router
resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform
using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated
the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our
solutions suitable for testing large scale NoC design.
I. Introduction
Today, the incessant reduction of the feature size of digital Very Large Scale Integration (VLSI) circuits
allows integrating several hundreds of processing elements such as computational cores on a single chip. These
resources are increasing demanding high performance communication; therefore traditional solution provided by
on-chip buses can no longer sustain this demand. In order to improve the performances and structural
weaknesses of traditional buses, Networks on Chip (NoCs) are being adopted. Nevertheless, NoCs are
characterized by high performances and low power consumption; one of the open problems that afflict research
activities on NoCs is the evaluation of their fault tolerance capabilities. Indeed, as specified in , faults are
increasing happening and a very large set of effects must be considered in new generation of NoCs. The larger
occurrence of fault is mostly due to the technology scaling of the new chip generations that result more
susceptible to fault appearance induced by different phenomena such as single-event upsets, cross-talk, age-
related degradation or process variability. Generally, test method of NoC infrastructures address two issues:
testing the switch blocks and testing the interconnection segments layout including the logic routers logic
resources. Different testing techniques have been proposed in order to evaluate fault effects on NoC. Several
NoC test methods have been focused on testing of the functional IP cores using Test Access Mechanism (TAM).
Other authors assumed specific fault model for NoC fabric and subsequently adopting it to test the data
transportation and the functional blocks. Vice versa, dedicated TAM based on specific on-chip network is
adopted by functional test solutions on SoCs multi-cores. The solution of our work improves previously
proposed method by developing a flexible and accurate fault injection environment, which can be adopted in
order to evaluate the fault tolerance capability of different NoC architectures. The main advantage of the
proposed solution rely on the possibility to apply different fault models that can emulate the effective faults
affecting NoC architectures, besides the proposed solutions has a full controllability an observability of the NoC
under test, since interconnections values and routers functional behaviour can be directly observed during the
test operations, feature which is extremely reduced for test solutions applied directly to the manufactured chip,
since NoC interconnections are deeply embedded and spread across the chip, therefore adding of probe
interconnections results inapplicable. The implementation of our solution relies on the main idea illustrated in
Figure 1. The fault injection method we developed is innovative since it is based on single reconfigurable chip,
such a Static RAM-based Field Programmable Gate Array (SRAM-based FPGAs) where thanks to a suitable
architecture, faults can be injected and evaluated. As illustrated in Figure 1, the architecture consists of two
processors: the processor 1 is devoted to the application of the test pattern to the NoC under test while the
processor 2 performs the injection of the faults. The execution of the fault injection does not require the insertion
of intrusive module into the NoC architecture, since modifying the configuration memory bit of the FPGA
device thus physically inserting the desired fault performs the injection. This operation is performed thanks to
the availability of the Configuration Access Port which is located internally to the device and can be controlled
by a logic core; in our case by the processor 2. Thanks to our solution the fault injection into the NoC
architecture can be performed without intrusive modules affecting the real behaviour and with optimal
performances, since the working frequency of the NoC is not drastically degraded by the fault insertion. Figure
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2. New Fault Injection Approach for Network on Chip
1. The main architectural scheme of the proposed approach. The rest of this paper is organized as follows. In
Section II we present the main background concepts behind the implementation and testing of NoC. The
description of the fault injection method, the developed architecture and the NoC fault models are presented in
Section III. Section IV describes the testing routines developed for testing the router logic blocks and the NoC
switches and interconnections. Fault injection results performed on a real NoC case study are presented in
Section V. Finally, conclusions and future works are drawn in Section VI.
II. Background
A Network on Chip is an interconnection architecture consisting of a 2-D mesh of routers each of which
connected to a set of interconnection resources. An example of NoC structure is illustrated by the NoC Under
Test box in Figure 1. Each router may be connected to its four neighboring routers and to a set of other routers
not located on its same row and column. Various NoC architectures have been proposed basing on the 2-D
matrix of resources. All of them are characterized by several aspects including topology, routing algorithms,
switching and flow control mechanisms. Several NoC architectures have been proposed in the past. The typical
NoC design is based on the data exchange between the functional IP cores in the form of data packets.
Depending on the adopted communication scheme, data packets are transmitted through routers and
interconnections from the source to the destination IP port. Different schemes have been proposed for NoC
communication such as communication switching, virtual cut-through and wormhole switching. While
communication switching is more applicable to small-size networks, virtual cut-through and wormhole switching
are appropriate for large MPSoCs since data have to traverse large distances and packets are buffered by halfway
routers on the routing path from the source to the destination. NoC architecture embeds two main resources:
interconnections and routers. Interconnections are wire segments that link the various routers inside to the NoC
array architecture, while routers are the most complex part of the NoC architecture. The details of a generic
router are illustrated in the following section.
2.1. Overview on the router architecture
The architecture of a NoC router, which an example is illustrated in Figure 2, consists of a set of FIFO
buffers forming the input and output data ports, a crossbar switch controlled by a logic circuitry that allow to
implement the transportation methodology. A router generally consists of multiple buffer stages connected
through the input and output ports to the routers placed on the same row (SR), column (SC) or on other locations
(OL) of the considered router. Each input/output buffer stage form an input/output queue which is internally
connected to a crossbar switch. The crossbar switch is the core of the router since it allows to form the links
between the input and output queues in all the possible combinations. The connection between the input and
output queues are managed by an arbitration circuitry, which on the basis of the adopted communication protocol
routes the data packets.
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3. New Fault Injection Approach for Network on Chip
III. The proposed fault injection method
The environment of the proposed method consists of an host-PC which communicate to the FPGA board
through a JTAG connection and a RS-232 serial cable. The method consists of the preliminary generation of the
fault list performed on the host-PC by parsing the NoC netlist and creating all the possible fault locations
according to the used synthesis model. The fault locations are consequently transferred through the JTAG cable
to the processor 2 dedicated memory. The fault injection execution flow is illustrated in Figure 3. It consists on
the following principal modules:
1. Fault Application: Fault Application: the fault application module is executed by the processor 2 and consists
on all the operations dedicated to the insertion of a fault into the NoC architecture. At first a fault location is read
from the memory module, secondly, the fault location is converted into the correspondent FPGA’s configuration
memory coordinates that control the selected NoC resource. Finally, the processor 2 accesses to the FPGA’s
internal configuration access port facility and activates the reconfiguration of the configuration memory bits
related to the selected coordinates. During the modification of the FPGA’s configuration memory, the NoC
functionality is temporary freeze. This has not any impact on performance degradation of the NoC, since the
freezing is synchronized with the microprocessor control clock.
2. Configuration memory coordinates: The configuration memory coordinates are the physical identification of
the FPGA’s configuration memory bits. Each configuration memory coordinate is associated to a correspondent
sequence of FPGA’s configuration memory bits.
3. FPGA configuration memory: The FPGA’s configuration memory contains million of SRAM cells that
configure the behavior of the circuit mapped on the FPGA device. The main idea of the present work consists in
acting on the configuration memory cells related to the behavior of the NoC architecture in order to insert a fault.
Therefore, in order to perform the right fault injection it is necessary to know the exact correspondence between
each configuration memory bit and the controlled FPGA’s resource. The modification of the configuration
memory is performed by the Internal Configuration Access Port (ICAP) controlled by the software running on
the Processor 2. Through the ICAP port it is possible to modify selectively a single FPGA configuration frame in
a small amount of time (dependent from the kind of FPGA device adopted).
4. Patterns generator: The patterns generator aims at generating the test stimuli applied to the NoC. The stimuli
are generated in the form of data packets transmitted from a source to a destination IP considering a NoC using a
Wormhole transport methodology. The patterns are generated by the software running on the Processor 1. Each
pattern consists of a signature composed by the identification of the source and destination IPs and by the
complete data packet. The application of the test patterns is executed by the Processor 2 by executing the
following steps: at first the signature is decoded individuating the source IP; secondly the Processor 2 access
through the On-Chip Peripheral Bus (OPB) to the source IP and send the data packet; third, the signature is
decoded individuating the destination IP and finally, the Processor 2 reads through the OPB bus the data packet
received by all the IP (except to the source one).
5. Fault classification: The fault classification is executed by the Processor 2. The first action consists on
capturing all the outputs of the IP destination ports. Secondly, the pattern signature is decoded individuating the
destination IP.
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4. New Fault Injection Approach for Network on Chip
6. Network-on-Chip Under Test: It consists on the architecture of the NoC under evaluation. The NoC model
should be described in HDL language in order to facilitate the integration in our environment. The integration
into the testing environment is performed by linking each NoC’s port to the platform IP port.
IV. Routing and logic fault model
The developed environment allows to inject a faults into a NoC architecture by acting through the
FPGA’s configuration memory. Principally, when a fault occurs into a NoC architecture, it may affect routing or
logic resources. A fault into routing resources may interest the hardwired interconnections between routers or the
programmable wires internally to each router’s crossbar switch. Conversely, a fault into logic resource may
essentially affect logic within router elements such as Flip-Flops (FFs) belonging to input / output queues or the
circuitry of the control and arbitration logic modules.
4.1. The routing fault model
When a fault occurs into interconnection router resources, it has a probability to affect one or more
wires for a duration of some times units (typically clock or transfer cycles) with different possible effects. When
a faults affects an interconnection resource it may create two possible effects: a transient modification of the
logic value physically transferred by the wire, a permanent modification of the wire behavior. Since transient
effects, such as pulses (i.e. 0-1-0 or 1-0-1) becomes critical only if the propagation of the pulse is captured by FF
after the wire, we modeled such effect into the logic fault model. Vice versa, the permanent modification of the
routing may introduce a physical change on the routing behavior. In order to model, all the possible effects into
the routing resources, either belonging to interconnections or internal router wires, we defined five different
effects depicted in Table 1, where each effect description is associated to the correspondent modification of the
FPGA resources necessary to physically implement the injection of the fault within the NoC model. Table 1.
Routing Fault Effect Description and the Corresponding FPGA Fault Injection Model.
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5. New Fault Injection Approach for Network on Chip
Considering the original wire segment configuration illustrated in Table I and implemented by the FPGA routing
resources using a sequence of Programmable Interconnection Points (PIPs), a routing fault may provoke:
A. The inversion of the propagated logic value in case a fault modifies the electrical behavior of the affected
routing wires. Typically this effects appear into interconnections between NoC routers;
B/C. The physical rupture of a routing segment is modeled as an open effect on routing segment.
Depending on the position of the rupture, a break into a routing segment may create a permanent propagation of
logic value 0/1. This effect may principally affect routing resources within the router crossbar switch due to the
permanent rupture of a given configuration.
D. The modification of multiple demultiplexer configurations is modeled by a bridge effect. This effect
may principally affect routing resources within the router crossbar switch due to permanent rupture of two
demultiplexer configurations where a configuration interferers to the other one.
E. The modification of the propagation delay of a routing resource is modeled by the physical modification of
the number of routing PIPs in order to insert the selected delay fault. The physical modification of the FPGA
resource in order to insert the previously described fault model is performed through the partial configuration of
the FPGA configuration memory which is described in the injection process section.
4.3. The injection process
The injection process is performed by a synchronized cooperation between the injection of a fault
performed by the processor 2 and the application of the test patterns executed by the processor 1 this operation is
explicated in the following six steps:
1. The processor 2 reads the fault location from the previously generated fault list.
2. The processor 2 configures the internal register of the FPGA’s ICAP module in order to apply the
reconfiguration of the configuration memory cells according to the location and type of fault. The selection of
the configuration memory cells is read from an appropriate DB containing the configuration memory bit and
resource correspondence and the physical locations of NoC routing and logic resources.
3. Once the ICAP module is configured, the processor 2 starts the modification of the configuration memory.
4. In parallel to the steps 2 and 3, the processor 1 generates the test patterns. We adopted a random generation
either for the source/destination locations of the packets and for the content of the data packet. The whole test
patterns are stored into a on-board DDRAM memory available on the FPGA carry board.
5. When the processor 2 has terminated the reconfiguration process, the processor 1 starts the application of the
test patterns. IP output ports are read at each clock cycle.
6. At the end of the application of all the test patterns, the processor 2 classify the faults according to the
previously described fault classification. These steps are repeated for all the faults available in the fault list.
During the execution of the fault injection process the processor 2 communicates to the host-PC by means of the
serial connection providing information about the status of the test, and finally providing the final result of the
test.
V. Experimental results
We implemented the described approach on a Xilinx Development Board equipped with a Spartan 6
XC6SLX45T SRAM-based FPGA. The environment has mapped using two Microblaze processors
communicating by means of on-chip processor local bus and connected to the NoC under test by means of on-
chip peripheral bus. Each IP input / output port has been implemented with software accessible registers, by this
way the software mapped on the processor 1 may rapidly access to the NoC ports.
5.1. Case study: NoCem
In this work, we rely on the Network on Chip emulator (NoCem) which consists of an open source
HDL model of a Network on Chip . NoCem allows different parametric regulations in terms of network
configurations, buffering schemes and arbitration logic. The NoCem model is targeted Xilinx-based
SRAMFPGAs and it uses different generics and generate statement in order to create a complete NoC design For
the purpose of this work we configured the NoCem model using NoC with 32 bits dataword size, packet length
of 16 datawords, router FIFO buffer length of 8, a square grid configuration with 16 IPs which correspond to a
4x4 2D mesh. The FPGA resource utilization in terms of LUT and FF of the NoC under test and of the
developed environment are reported in the Table II.
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6. New Fault Injection Approach for Network on Chip
5.2. Fault Injection Results
We run four different fault injection campaign, in order to test inverted wire faults, stuck-at 0/1 faults,
bridge faults and delay faults. The obtained results are illustrated in Table III where we reported the number of
Injected and Detected Faults and the fault injection time required by the developed platform. The average time
required by the developed platform in order to perform the physical modification of the FPGA configuration
memory in order to inject a wire, stuck-at or bridge faults is of 12 μs. While it increases to 18 μs in case of the
delay faults due to the more configuration steps required for adding extra PIPs. The great part of the fault
injection time is due to the random patterns application which on the average requires around 73 ms for each
injected fault.
In order to compare the effectiveness of the proposed approach with consolidated techniques, we compared the
fault injection experiments with the results obtained by means of fault simulation of stuck at faults using the
Tetramer fault simulation tool applying the same test patterns. The results reports exactly the same data obtained
with the developed Stuck-at fault injection but the time required by the simulation has been of around 13 hours
with respect to the 5.6 hours required by the developed approach. Please note that the detected delay faults are
extremely low due to the very low coverage of the random test patterns.
VI. Conclusions and future works
In this paper we present a novel test approach based on a dual-processor system implemented on SRAM
based FPGA which is able to test mesh-based Network On Chips. The approach has several advantages:
flexibility, observability and test speed. The approach has been implemented on an FPGA platform and a real
NoC architecture using standard communication protocol has been tested. The experimental result demonstrated
the effectiveness of the developed approach and makes our approach suitable for testing large scale NoC design.
As future activities, we plan to extend our emulation platform to analyze the effects of delay faults and to
improve the delay fault model.
References
[1] S. Borkar, “Designing reliable systems from unreliable components: the challenges of transistor variability and degradation”, IEEE
Micro, Vol. 25, No. 6, pp. 10-16, November 2005.
[2] L. Chunsheng, V. Iyengar, S. Jiangfan, E. Cota, “Power- Aware Test Scheduling in Network-on-Chip Using Variable-Rate On Chip
Clocking”, IEEE International Very Large Scale of Integration Test Symposium , 2005, pp. 349 – 354
[3] B. Vermeulen, J. Dielissen, K. Goossens, C. Ciordas, “Bringing communications networks on a chip: test and verification
implications”, IEEE Communications Magazine, Volume 41, Septmber, 2003, pp. 74 – 81.
[4] A. Kohler, G. Schley, M. Radetzki, “Fault Tolerant Network on Chip Switching With Graceful Performance Degradation”, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 6, June 2010, pp. 883 – 896.
[5] M. Nahvi, A. Ivanov, “Indirect Test Architecture for SoC Testing”, IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, Volume 23, Issue 7, July 2004, pp. 1128 – 1142.
[6] Xilinx Product Specification, “LogiCORE IP XPS HIWCAP”, Product Spec., DS586, June 22, 2011.
[7] T. Bjerregaard and S. Mahadevan, “A survey of research and practices of network-on-chip”, ACM Computing Surveys, Vol. 38, pp.
1-51, March, 2006.
[8] J. Duato, S. Yalamanchili, L. Ni, “Interconnection Networks – An Engineering Approach”, Morgan Kaufmann, 2002.
[9] C. Grecu, P. Pande, A. Ivanov, R. Saleh, “Timing Analysis of Network-on-chip Architectures for MP-SoC Platforms”, Elsevier
Microelectronics Journa, XX
[10] L. Benini, D. Bertozzi, “Xpipes: A Network-on-chip architecture for gigascale systems-on-chip”, IEEE Circuits and Systems
Magazine, Volume 4, Issue 2, 2004, pp. 18-31.
[11] S. Pasricha, Y. Zou, D. Connors, H. J. Siegel, “OE+IOE: A novel turn model based fault tolerant routing scheme for networks-on-
chip”, IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2010, pp. 85 – 93
[12] H. Zimmer, A. Jantsch, “A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip”,
IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003, pp. 188 – 193.
[13] E. Cota,”Power aware NoC Reuse on the Testing of Core-Based Systems”, proceedings of the IEEE International Test Conference
2003, pp. 612 – 621.
[14] Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu, “On the Design and Analysis of Fault Tolerant NoC
Architecture Usin Spare Routers”, International DAC Conference, 2011, pp. 431 – 436.
[15] L.Sterpone, M. Violante, “A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through
SRAM-based FPGAs”, IEEE Transactions on Nuclear Science, Vol. 52, Issue 6, 2005, b pp. 2217 - 2223.
[16] A. Perreira, J. P. Teixeir and M. Santos, “A Novel Approach to FPGA-based Hardware Fault Modelling and Simulation”, IEEE
International Workshop on Design and Diagnostic of Electronic Circuits and Systems, 2003, pp. 17 – 24.
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