SystemVerilog Assertion

1. SystemVerilogアサーション 入
門
ヅオン・ディエップ

2.  SystemVerilog Assertion?
 SystemVerilog アサーション？
 SVA Checker Library
 SVA チェック・ライブラリ
 Custom Assertion
 カスタム・アサーション
 Advanced SVA
 アドバンスト SVA
 Appendix

3.  A language to describe sequence of
events
 Let you test for their occurrence by adding
verification code to design
 A part of SystemVerilog language

4.  Concurrent （コンカレント）
 assert property
 Immediate （イミディエイト）
 assert

5.  Behaviors suited to assertions
 Interface protocols
 Temporal relationships
 FSM operation
 Signal/command level
 Behaviors better suited to Hardware
Verification language
 Complex mathematical formula
 Complex data transaction

6.  General library of common property
checks
 Two forms
 Module based and Interface based
 Directory （ディレクトリ）
 $VCS_HOME/packages/sva/
 Document （ドキュメント）
 $VCS_HOME/doc/UserGuide

7.  Many basic properties
can be checked using
SVA Checker Library
 Fast and easy
 Pre-written/ Pre-verified
Verilog
source
SVA
source
vcs
simv
DVE
sim

8.  $> vcs
-sverilog // Active SV(A) compilation
+define+ASSERT_ON // Enable the checking functionality
-y $VCS_HOME/packages/sva // Directory of Checker library
+libext+.sv //
+incdir+$VCS_HOME/packages/sva // Include directory
-debug_all // Turn on debug and line stepping
-assert dve // Dump SVA data for DVE debug
<verilog source code>
 $> ./simv -gui

9.  DVE
 Debug GUI
 -assert report and –assert success
 Quick debugging through textual report
 $assert_monitor
 Trace debugging in textual format

10.  SVA syntax （SVA シンタックス）
 SVA compile options

11.  Sequence （シーケンス）
 ##t1, ##[t1:t2], ##[t1:$]
 [*r1:r2], [->r1:r2], [=r1:r2]
 and, or, throughout, intersect, within, first_match, |->, |=>
 Function （ファンクション）
 $rose, $fell, $stable
 System （システム）
 $isunknow, $info, $error, $warning, $fatal, $past, $countones,
$onehot, $onehot0
 Keyword （キーワード）
 bind, sequence, property, assert, not, ended, matched
 endsequence, endproperty, assert property, cover property

12.  Verify Directives
 assert, cover, bind,…
 Property Operators
 |->, |=>, disable iff, not,…
 Sequence Operators
 And, or, ##t, ##[t1:t2], …

13.  Used to capture certain functionality
 Used to describe a pattern that we want to
check for
 Two important aspects
 Whether the simulation results match the
expression
 The start and end time of the evaluation
sequence <name>(<arguments>)
<clock> <expression>;
endsequence

14.  Specifying Delays
 Fixed time
 ##1
 ##0: Special case used to joint two sequences
 Time interval
 ##[1:3]
 Open ended, eventually
 ##[1:$]: Next clock cycles to the end of simulation
 The delay is in clock cycles, not nanoseconds

15.  How to use?
 req ##2 ack
 ack should be high two cycles after req
 req ##2 ack ##3 !ack
 ack will remain high for only 3 cycles
 req ##2 ack ##3 !ack ##[1:3] $fell(done)
 done falls 1 to 3 clocks after ack is removed

16.  Defines the behavior of the design
 Can be declared in a module or in an
interface
 Can optionally have formal arguments
 Built from sequences or Boolean expressions
property <name>;
<clock> <expression>;
// <clock><sequence name>;
// <sequence name>;
endproperty

17.  Sequences are often used to construct
properties
 Breaks down complex functionality
 Promotes re-use
Using sequence Without sequence
sequence s1;
req && !ack;
endsequence
property p1;
@(posedge clk) s1;
Endproperty
property p1;
@(posedge clk) req && !ack;
endproperty

18.  Produces results that are visible
externally: reports, waveforms, …
 An assert either passes, fails or remains
incomplete
<label> assert property <property_name>;
Assertions used as check Assertions used as forbid
property p1_check;
@(posedge clk) b ##1 c;
endproperty
a1: assert property (p1_check);
property p1_check;
@(posedge clk) not (b ##1 c);
endproperty
a1: assert property (p1_check);

19.  Assert statements can also have action block associated with
it.
 When no action block is specified its treated as null
 Action block cannot contain another assert statement
property p1_check;
@(posedge clk) b |-> ##1 c;
endproperty
a1: assert property (p1_check) else begin
$display(“the p1_check failed”);
notifier = 1;
$my_c_function; //Task call
end

20.  An assert statement can be embedded
within procedural always blocks
 Clock and enabling signals are automatically
inherited
 Immediate Assertion
 Evaluated when the assert statement is
executed in the procedural code.
 Good for combinational checks (non temporal)
 Only Boolean expressions are allowed
 No sequences or properties

21.  @(<clock_edge> <clock_name>)
Clock in sequence Clock in property Clock in assert
sequence s1;
@(posedge clk)
req && !ack;
endsequence
property p1;
s1;
endproperty
a1: assert property (p1);
sequence s1;
req && !ack;
endsequence
property p1;
@(posedge clk) s1;
endproperty
a1: assert property (p1);
sequence s1;
req && !ack;
endsequence
a1: assert property
@(posedge clk)
(s1);

22.  Signal level sampling (信号レベルのサンプリ
ング)
property p_reg;
@(posedge clk) reg;
endproperty
property p_ack;
@(posedge clk) !ack;
endproperty
a_req: assert property (p_reg);
a_ack: assert property (p_ack);

23.  Signal Edge sampling (信号エッジサンプリング）
 $rose(<signal_name>)
 Returns true if a positive edge was detected between the last
and current samples.
 $fell(<signal_name>)
 Returns true if a negative edge was detected between the
last and current samples.

24.  Property adds constructs for evaluation
control
 not: inverts the expression
 Good for forbid a property
 Implication: |->, |=>
 disable iff (if and only if)

25.  Implication is equivalent to if-then structure
 Overlapped implication: |->
 If antecedent evaluates to true, the consequent is
evaluated on same clock cycle
 Assertion does not fail if antecedent is false
 Vacuous Success
 Non-overlapped implication: |=>
 If there is a match on the antecedent, the consequent is
evaluated one clock cycle later
 The statement: a |=> b is equivalent to: a |-> ##1 b
 Useful to synchronize data between multiple clocks

26.  Implication has a default else clause
 The statement: req |-> ack is equivalent to: if
req then ack else 1
 The following are NOT the same:
 req && ack
 Fails when req = 0
 req |-> ack
 Succeeds when req = 0

27. property p_andand;
@(posedge clk) reg && ack;
endproperty
property p_ol_implication; // overlapped implication
@(posedge clk) req |-> ack;
endproperty
property p_nol_implication; // non-overlapped implication
@(posedge clk) req |=> ack;
endproperty
a_andand: assert property (p_andand);
a_ol_implication: assert property (p_ol_implication);
a_nol_implication: assert property (p_nol_implication);

28.  Use disable iff to abort property valuation
on a Boolean condition (e.g., reset)
 If reset is TRUE, terminates the attempt with a
vacuous success

29.  $stable(expr)
 Returns true if the value of an expression did not
change between the last and current samples.
 $past(expr, n)
 Returns the value of an expr n samples earlier.
 $isunknown(expr)
 Returns true if any bit of the expression is X or Z.
 $countones(expr)
 Returns an integer equal to the number of 1’s in the
expression.

30.  Bindings are used to attach SVAs to the
design
 Allows SVAs to be written in a separate module
 Module bindings
 The module/interface containing the properties become
part of that module and all its instances
bind <module_name> <SVA_module_name> #(parameter_list)
<instance_name> (port_list);
 Instance bindings
 The module/interface containing the properties become
part of the specific instance
bind <instance_name> <SVA_module_name> #(parameter_list)
<instance_name> (port_list);

31.  Bindings are easy way to use checker libraries
 Verification engineers developing complex properties to verify
interfaces should write properties in a separate module/interface and
bind it to the design
module check_par(clk, parity, data);
input clk, parity; input [31:0] data;
property p_check_par;
@(posedge clk) ^(data^parity) == 1’b0;
endproperty
a_check_par: assert property(p_check_par);
endmodule
bind data_bus check_par a1(m_clk, m_parity, m_data);
bind top.mid.u1 check_par a2 (i_clk, i_parity, i_data);

32. Option Description
-assert enable_diag Control assertions at runtime
-assert dve Enable dumping assertion information in a VPD file
-assert disable Disable all SVAs in the design
-assert disable_cover Disable assertion coverage
-assert dumpoff Disable the dumping of SVA information
-assert finish_maxfail=N
-assert global_finish_maxfail=N
Terminate simulation after certain number of assertion
failures
-assert success Show both passing and failing assertions
-assert maxsuccesses=N Limit the maximum number of successes reported
-assert quiet Disable the display of messages when assertions fail
-assert report=file_name Generate a report file
-cm assert Specifies monitoring for SystemVerilog assertions coverage

33.  Sequence repetition operators
 Consecutive repetition [*n]
 Range repetition [*min:max]/ [*min:$]
 Go to repetition [->n]
 Non-consecutive repetition [=n]
 Implication and repetition
 Repetition as an antecedent
 Repetition as an consequence

34.  A[*1]: A ##1 A
 A[*n]: A ##1 A ##1 A ##1 A …. ##1 A
 A[*1:$]: A[*1], A[*2], A[*3], …
 A[*min:max]
 A[->1]  (!A[*0:$] ##1 A)
 A[->n]  (!A[*0:$] ##1 A)[*n]  A[->1][*n]
 A[->1:3]  A[->1] or A[->2] or A[->3]
 A[->min:max]  A[->min] or A[->(min+1)] or… A[->(max-
1)] or A[->max]
 A[=1]  (A[->1] ##1 !A[*0:$])
 A[=n]  (A[->n] ##1 !A[*0:$])

35.  Use the repetition operator to loop on a
sequence or Boolean expression
 sequence [*n] // n = integer number of
iterations
 There is an implicit ##1 between each loop
 “ready asserted for 3 consecutive cycles”
 ready ##1 ready ##1 ready
property p_ready_3;
@(posedge clk) ready[*3];
endproperty

36.  Same as consecutive but with an upper bound
sequence [*min:max]
 Generates (max – min) + 1 threads
 There is an implicit ##1 between each loop
 “ ready repeated 1 to 3 times”
 ready or ready ##1 ready or #ready ##1 ready ##1 ready
property p_ready_13;
@(posedge clk) ready[*1:3];
endproperty
 A[*1:$]: A[*1], A[*2], A[*3], …
 Upper bound $: the sequence repeats at least the number
of times specified by the lower bound.

37.  Non-consecutive exact repetition' operator for
Boolean expression
 It checks if a Boolean expression has been true
for specified number of times but not necessarily
on consecutive clock cycles.
 The sequence starts with the first occurrence of
the Boolean expression and ends with the last
 A[->1]  (!A[*0:$] ##1 A)
 A[->n]  (!A[*0:$] ##1 A)[*n]  A[->1][*n]
 A[->1:3]  A[->1] or A[->2] or A[->3]
 A[->min:max]  A[->min] or A[->(min+1)] or… A[->(max-1)] or
A[->max]

38.  Similar to the [-> ] operator
 When the ends with the last true value of
the operand, [= ] operation may extend
beyond such last true value.
 A[=1]  (A[->1] ##1 !A[*0:$])
 A[=n]  (A[->n] ##1 !A[*0:$])

39.  Repetition can be used on either side of the
implication operators “|->” and “|=>”
 When repetition is used with implication:
 In antecedent:
 Vacuous successes for unmatched threads
 Matched threads result in continued evaluation of
consequent
 In consequent:
 Only one of thread needs to match

40. property p_antecedent;
@(posedge clk) req[*3] |=> ack;
endproperty
property p_antecedent;
@(posedge clk) req[*1:3] |=> ack;
endproperty

41. property p_consequence;
@(posedge clk) $rose(gnt) |-> ack[*2:3] ##1 !ack;
endproperty