MOSFET....complete PPT

Electronic Circuits
1
Dr. S. M. Gulhane, PREC, Loni

2
Savitribai Phule Pune University
Second Year of Electronics/E & TC Engineering (2019 Course)
204181: Electronic Circuits
Teaching Scheme: Credit Examination Scheme:
TH: 03 hrs. / week 03
In-Sem (Theory): 30 Marks
End Sem (Theory): 70 Marks
Course Objectives: To make the students understand
 Semiconductor device MOSFET, its characteristics, parameters & applications.
 Concepts of feedbacks in amplifiers & oscillators.
 Operational amplifier, concept, parameters & applications.
 ADC, DAC as an interface between analog & digital domains.
 Concepts, characteristics & applications of PLL.
Course Outcomes: On completion of the course, learner will be able to –
CO1: Assimilate the physics, characteristics and parameters of MOSFET towards its application as an
amplifier.
CO2: Design MOSFET amplifiers, with and without feedback, & MOSFET oscillators, for given Specifications.
CO3: Analyze and assess the performance of linear and switching regulators, with their variants, towards
applications in regulated power supplies.
CO4: Explain internal schematic of Op-Amp and define its performance parameters.
CO5: Design, Build and test Op-amp based analog signal processing and conditioning circuits towards
various real time applications.
CO6: Understand and compare the principles of various data conversion techniques and PLL with their
applications.

3
Course Contents
Unit I MOSFET & its Analysis (08 Hrs)
Enhancement MOSFET: Construction, Characteristics, AC equivalent ckt, Parameters,
Parasitics, Non ideal characteristics: Body effect, Sub-threshold conduction, W/L ratio.
Common source amplifier & analysis, DC Load line, Source follower.
CO1
Unit II MOSFET Circuits (06 Hrs)
MOSFET as switch: CMOS inverter, resistor/diode. Current sink & source, Current mirror.
Four types of feedback amplifiers, Effects of feedback, Voltage series & current series
feedback amplifiers and analysis. Barkhausen criterion, Wein bridge & phase shift
oscillator.
CO2
Unit III Voltage Regulators (06 Hrs)
Three terminal voltage regulator (317 and 337)
Block diagram of linear voltage regulator, IC 317 and IC337, Features and specifications,
typical ckts, Current boosting. Low Dropout Regulator (LDO).
SMPS: Block diagram, Types, features and specifications, typical circuits buck and
boost converter
CO3
Unit IV Operational Amplifier (08 Hrs)
Block diagram, Differential Amplifier configurations, Differential amplifier analysis for
dual input balanced output mode (using r parameters), Current mirror Circuits, Level
shifter, Op amp parameters (AC & DC) and comparison with ideal Op-Amp. Voltage
series & voltage shunt feedback amplifiers, Effect on Ri, Ro, gain & bandwidth
CO4

4
Course Contents
Unit V Op-Amp Applications (10 Hrs)
Inverting amplifier, Non inverting amplifier, Voltage follower, Summing amplifier,
Differential amplifier, Practical integrator, Practical differentiator, Instrumentation
amplifier, Comparator, Schmitt trigger, Square & triangular wave generator, Precision
rectifiers.
CO5
Unit VI Converters & PLL (06 Hrs)
DAC & ADC: Resistor weighted and R-2R DAC, SAR, Flash and dual slope ADC Types /
Techniques, Characteristics, block diagrams, Circuits, Specifications, Merits, Demerits,
Comparisons.
PLL: Block Diagram, Characteristics/Parameters, phase detectors, Details of PLL IC 565 &
Applications.
CO6
Text Books:
1. Donald Neaman, “Electronic Circuits – Analysis and Design” Third edition, Mc Graw Hill.
2. Ramakant Gaikwad, “Op amps & Linear Integrated Circuits”, Pearson Education.
Reference Books:
1. Millman Halkias, “Integrated Electronics”.
2. Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”, Second Edition, Oxford.
3. Salivahan and Kanchana Bhaskaran, “Linear Integrated Circuits”, Tata McGraw Hill.
MOOC / NPTEL Courses:
1. NPTEL Course “Analog Electronic Circuits” https://nptel.ac.in/courses/108/105/108105158/
2. NPTEL Course on “Analog Circuits” https://nptel.ac.in/courses/108/101/108101094/

Electronic Circuits
5
Dr. S. M. Gulhane, PREC, Loni

6
Savitribai Phule Pune University
Second Year of Electronics/E & TC Engineering (2019 Course)
204181: Electronic Circuits
Teaching Scheme: Credit Examination Scheme:
TH: 03 hrs. / week 03
In-Sem (Theory): 30 Marks
End Sem (Theory): 70 Marks
Course Objectives: To make the students understand
 Semiconductor device MOSFET, its characteristics, parameters & applications.
 Concepts of feedbacks in amplifiers & oscillators.
 Operational amplifier, concept, parameters & applications.
 ADC, DAC as an interface between analog & digital domains.
 Concepts, characteristics & applications of PLL.
Course Outcomes: On completion of the course, learner will be able to –
CO1: Assimilate the physics, characteristics and parameters of MOSFET towards its application as an
amplifier.
CO2: Design MOSFET amplifiers, with and without feedback, & MOSFET oscillators, for given Specifications.
CO3: Analyze and assess the performance of linear and switching regulators, with their variants, towards
applications in regulated power supplies.
CO4: Explain internal schematic of Op-Amp and define its performance parameters.
CO5: Design, Build and test Op-amp based analog signal processing and conditioning circuits towards
various real time applications.
CO6: Understand and compare the principles of various data conversion techniques and PLL with their
applications.

7
Course Contents
Unit I MOSFET & its Analysis (08 Hrs)
Enhancement MOSFET: Construction, Characteristics, AC equivalent ckt, Parameters,
Parasitics, Non ideal characteristics: Body effect, Sub-threshold conduction, W/L ratio.
Common source amplifier & analysis, DC Load line, Source follower.
CO1
Unit II MOSFET Circuits (06 Hrs)
MOSFET as switch: CMOS inverter, resistor/diode. Current sink & source, Current mirror.
Four types of feedback amplifiers, Effects of feedback, Voltage series & current series
feedback amplifiers and analysis. Barkhausen criterion, Wein bridge & phase shift
oscillator.
CO2
Unit III Voltage Regulators (06 Hrs)
Three terminal voltage regulator (317 and 337)
Block diagram of linear voltage regulator, IC 317 and IC337, Features and specifications,
typical ckts, Current boosting. Low Dropout Regulator (LDO).
SMPS: Block diagram, Types, features and specifications, typical circuits buck and
boost converter
CO3
Unit IV Operational Amplifier (08 Hrs)
Block diagram, Differential Amplifier configurations, Differential amplifier analysis for
dual input balanced output mode (using r parameters), Current mirror Circuits, Level
shifter, Op amp parameters (AC & DC) and comparison with ideal Op-Amp. Voltage
series & voltage shunt feedback amplifiers, Effect on Ri, Ro, gain & bandwidth
CO4

8
Course Contents
Unit V Op-Amp Applications (10 Hrs)
Inverting amplifier, Non inverting amplifier, Voltage follower, Summing amplifier,
Differential amplifier, Practical integrator, Practical differentiator, Instrumentation
amplifier, Comparator, Schmitt trigger, Square & triangular wave generator, Precision
rectifiers.
CO5
Unit VI Converters & PLL (06 Hrs)
DAC & ADC: Resistor weighted and R-2R DAC, SAR, Flash and dual slope ADC Types /
Techniques, Characteristics, block diagrams, Circuits, Specifications, Merits, Demerits,
Comparisons.
PLL: Block Diagram, Characteristics/Parameters, phase detectors, Details of PLL IC 565 &
Applications.
CO6
Text Books:
1. Donald Neaman, “Electronic Circuits – Analysis and Design” Third edition, Mc Graw Hill.
2. Ramakant Gaikwad, “Op amps & Linear Integrated Circuits”, Pearson Education.
Reference Books:
1. Millman Halkias, “Integrated Electronics”.
2. Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”, Second Edition, Oxford.
3. Salivahan and Kanchana Bhaskaran, “Linear Integrated Circuits”, Tata McGraw Hill.
1. NPTEL Course “Analog Electronic Circuits” https://nptel.ac.in/courses/108/105/108105158/
2. NPTEL Course on “Analog Circuits” https://nptel.ac.in/courses/108/101/108101094/

Electronic Circuits
Teaching Methodology & Depth of Topic
9

Unit1: MOSFET & its Analysis
10

UNIT-1 [MOSFET & its Analysis]
11

UNIT-1 [MOSFET & its Analysis]
Text Books:
• T1: Donald Neaman, “Electronic Circuits – Analysis and Design” Third edition, Mc
Graw Hill.
• T2: Ramakant Gaikwad, “Op amps & Linear Integrated Circuits”, PHI 4th Education.
• T3: Boylestad and Nashelsky “Electronic Devices and Circuit Theory” Prentice Hall
Seventh Edition
Reference Books:
• R1: Millman Halkias, “Integrated Electronics”.
• R2: Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”, Second Edition,
Oxford.
• R3: Salivahan and Kanchana Bhaskaran, “Linear Integrated Circuits”, Tata McGraw
Hill.
• R4: Pucknell and Kamran
1. NPTEL Course “Analog Electronic Circuits”
• https://nptel.ac.in/courses/108/105/108105158/
2. NPTEL Course on “Analog Circuits”
12

Unit-II: MOSFET Circuits
13

UNIT-2 [ MOSFET Circuits]
Text Books:
Graw Hill.
• T2: Ramakant Gaikwad, “Op amps & Linear Integrated Circuits”, Pearson Education.
Reference Books:
Oxford.
Hill.
16

Unit-III: Voltage Regulators
17

UNIT-3 [Voltage Regulators]
18

UNIT-3 [Voltage Regulators]
Text Books:
Graw Hill.
• T3: K. R. Botkar, “Integrated Circuits” Page No: 27 to 772
Reference Books:
Oxford.
Hill.
19

Unit-IV: Operational Amplifier
20

UNIT-4 [Operational Amplifier]
21

22

Text Books:
Graw Hill.
• T2: Ramakant Gaikwad, “Op amps & Linear Integrated Circuits”, PHI 4th Edition.
Reference Books:
Oxford.
Hill.
• https://nptel.ac.in/courses/108/101/108101094/ 23

Unit-V: Op-Amp Applications
24

UNIT-5 [Op-Amp Applications]
25

26

27

Text Books:
Graw Hill.
• T2: Ramakant Gaikwad, “Op amps & Linear Integrated Circuits”, PHI 4th Education.
Reference Books:
Oxford.
Hill.

Unit-VI: Converters & PLL
29

UNIT-6 [Converters & PLL] ]
31

UNIT-6 [Converters & PLL]
Text Books:
Graw Hill.
Reference Books:
Oxford.
Hill.

Field Effect Transistor
• BJT: Bipolar Junction Transistor
 Involve two types of charge carriers; majority and minority charge carriers in its operation
 (‘n’ and ‘p’ carriers respectively in npn and vice-versa in pnp transistor)
 Control the flow of majority charge carriers by controlling minority charge carriers
 Current Operating device: Ib controls flow of Ic/Ie
 Storage of charge carriers in the base region limits the speed of
operation
 Bigger in size compared to FET
 Temperature sensitive
 More noisy
 Low input impedance
 More power consumption
 Not suitable for VLSI ICs
33

• FET: Field Effect Transistor
 Unipolar device
 Involve only one type of charge carriers; ‘n’ or ‘p’ in its operation
 Control the flow of charge carriers by controlling the electric field
 Voltage controlled Device (gate voltage controls drain current)
 Less Noisy as Compared to BJT
 No minority carrier storage (Turn off is faster)
 Very small in size, occupies very small space in ICs
 Low Voltage Low Current Operation (Low-power consumption)
 Has higher input impedance
 less sensitive to temperature variations
 more easily integrated on IC’s
34

• FET: Field Effect Transistor
 Provide less gain compared to BJT
 More static sensitive than BJT’s
35

Field Effect Transistor: Types
36

Junction Field Effect Transistor (JFET)
37
3D View
n-channel JFET
Cross sectional View
Typically L>>2a
Heavily doped
p-region
N-type substrate
Ohmic Contact

38
Simplified Physical structure
n-channel JFET
The n-type region between the p regions offers a resistance to current flow.
The resistance varies with the voltage applied to gate terminal VG .

• Basic Operation of JFET:
 The Field Effect Transistor has three terminals: Gate (G), Drain (D) and Source (S)
 In n-channel FET, Drain (D) and Source (S) are connected to n-channel and Gate (G)
is connected to the p-type material
 The voltage applied at gate terminal controls the current flow between the other
two terminals; source and drain
 a FET can be thought of as a resistance connected between Source and Drain D,
which is a function of the gate voltage VG .
 The mechanism of gate control varies in different types of FETs
39

• Basic Operation of JFET:
 In the operation of JFET, a reverse voltage
is applied to the Gate (G) and forward
voltage between Drain (D) and Source (S)
40

Basic Operation of JFET: VG=0V and VDS=0V
 consider the case, VG=0V and VDS=
0V
 There occurs a formation of depletion
region at the p-n junction as the
electrons from n-channel combine
with holes from p-gate.
 Since no voltages are applied, the
depletion regions are of equal
thickness and symmetrical
 Drain current ID is zero as VD is 0V
wrt source
41

Basic Operation of JFET: VG=0V and VDS is +ve
 consider the case, VG=0V and VDS is
increased from 0 to a more positive
voltage
 the depletion region between p-gate and
n-channel increases as more electrons
from n-channel combine with holes from
p-gate.
 increasing the depletion region,
decreases the size of the n-channel which
increases the resistance of the n-channel.
 Though the resistance of the channel
increases with increasing VDS, the
current ID doesn't decrease, rather it
increases because drain voltage wet
source increases.
42The drain end of the channel has a larger reverse bias than the source end.
wedge-shaped depletion regions
+
-

Basic Operation of JFET: Pinch-off
+
-
 If VGS = 0 and VDS is further increased to a
more positive voltage, then the depletion
zone gets so large that it reaches near to
pinch off the n-channel.
 The channel width becomes very narrow and
remain constant and the current ID doesn't
vary irrespective of variation in VDS
At the pinch-off point:
 any further increase in VDS does not produce
any increase in ID.
 ID is at saturation or maximum. It is referred
to as IDSS and the value of VDS at which
saturation starts is referred to as Vp
 Also the resistance of the channel is at
maximum
43
0V

Basic Operation of JFET: VDS-ID Characteristics
44
JFET modeling when ID=IDSS,
VGS=0,
VDS>VP

Basic Operation of JFET: VGS is reverse biased
and VDS is +ve constant
 consider the case, VG=-ve and VDS is
some constant positive voltage
 As VGS becomes more negative the
depletion region increases..
 Now if VDS is increases, the JFET will
operate near to pinch-off at a lower
voltage (Vp).
 ID reached to saturation value earlier
(ID < IDSS) and will remain constant
even though VDS is increased.
 Further increase in reverse biased
increases the depletion region and hence
decreases ID
 Eventually ID will reach 0A. VGS at this
point is called Vp or VGS(off). 45
+
-
-
+
+
-
VDS= +ve
VGS=- VGS(off)

Drain characteristics: VDS-ID Characteristics
46

Drain characteristics : VDS-ID Characteristics
47
 Also note that at high
levels of VDS the JFET
reaches a breakdown
situation.
 if VDS > VDSmax, ID
will increases
uncontrollably
Ohmic
region
Saturation region
Cut-off region
VGS=-1V
VGS=0V
VGS=-1V
VGS=-5V
=-2V
=-3V
=-4V
5 10 15 20 25

Drain characteristics : VDS-ID for p-chanel FET
48
 In p-channel FET,
substrate is p-type and
gate is n type
 To make Drain to source
forward bias a negative
voltage is applied
between Drain and
source
 To make Gate-Source
voltage reverse bias a p
ositive voltage is applied
between Gate to Source
Ohmic
region
Saturation region
Cut-off region

Transfer Characteristics : VGS-ID Characteristics
49
 The transfer characteristic of
JFET is the input (VGS)-to-
output (ID) characteristics
 It can be easily drawn from
the VDS-ID Characteristics by
determine the value of ID for
a given value of VGS.
 In a JFET, the relationship of
VGS (input) and ID (output)
is given as
Where, IDSS is the short circuit drain current, VP is the pinch off voltage

Transfer Characteristics : VGS-ID Characteristics
50
Non-saturation (Ohmic) Region:
Saturation (or Pinchoff) Region:

REGIONS OF JFET ACTION :
• Ohmic Region
 linear region
 JFET behaves like an ordinary resistor
• Pinch Off Region
 Saturation Region
 JFET operates as a constant current device
 The JFET is used as an amplifier in this region
• Breakdown Region
 If VDS is increased beyond its avalanche breakdown voltage
 Id increases to an excessive value.
• Cut Off Region
 Two depletion regions touch each other, channel width is zero, ID
is zero
 VGS (off) = -Vp 51

Biasing Circuits of FET
52Dr. S. M. Gulhane

Junction Field Effect Transistor
• Biasing Circuits used for JFET:
53
 For the JFET to operate in
active region, the operating
range of the input signal of
a JFET should be between 0
to – VGS(off)
 To ensure the operating
range of varying input
signal, an operating point
(Quiescent point) (VDS, ID)
is set by using biasing
Circuit
 The operating point of the
JFET is located at the
coordinate (VDS, ID) on the
characteristic graph.

• Biasing Circuits used for JFET:
 Fixed bias circuit
 Self bias circuit
 Potential Divider bias circuit
54

• Fixed Bias Circuit :
55
 As, in JFET there is no gate
current,We can find the value of drain
current ID from the relation given
below
 The value of VDS can be found by applying KVL at
output circuit
VDS

• Self Bias Circuit :
56
 The drain current flows
through Rs and produces the required
bias voltage. Therefore, Rs is the bias
resistor.
 The voltage across RS would be
 As there is no gate current, zero
ground potential appears at the gate
terminal.

VDS

• Voltage Divider Bias Circuit :
57
 Here, resistor R1 and R2 form a
voltage divider circuit across drain
supply voltage (VDD).
VDS

• Biasing Circuits for n-channel JFET:
58

Parameters of JFET
• Transconductance (gm) − It is the ratio of change in drain current (ΔID) to the
change in gate source voltage (ΔVGS) at constant drain-source voltage. It can be
expressed as,
This value is maximum at VGS = 0. This is denoted by gmo. This maximum value
(gmo) is specified in a JFET data sheet. The transconductance at any other value
of gate to source voltage (gm) can be determined as follows.
The expression of drain current (ID) is
• At VGS = 0, the transconductance gets its maximum value and that is
• Therefore, we can write,
59
gm = (ΔID)/(ΔVGS) at constant VDS

Parameters of JFET
• AC drain resistance (rd) − It is the ratio of change in the drain source voltage
(ΔVDS) to the change in drain current (ΔID) at constant gate-source voltage. It
can be expressed as,
• Amplification Factor (µ) − It is the ratio of change in drain-source voltage
(ΔVDS) to the change in gate source voltage (ΔVGS) constant drain current (ΔID).
It can be expressed as,
60
rd = (ΔVDS)/(ΔID) at constant VGS
µ = (ΔVDS)/(ΔVGS) at constant ID

Parameters of JFET
• Gate Cut Off Voltage (VGSoff) − The relation between gate to source voltage
and drain current is given below.
After a certain gate to source voltage (VGS), the drain current ID becomes zero.
This voltage is known as Cut Off Gate Voltage (VGS(off)). This voltage numerically
equals the pinch-off drain to source voltage (Vp).
• Shorted Gate Drain Current (IDSS) − This is the maximum drain current that can
flow through the channel when the gate terminal is in ground potential. This
current is fixed for a JFET and this is called shorted gated drain current and
generally denoted by IDSS.
61

Parameters of JFET
• Gate Cut Off Voltage (VGSoff) − The relation between gate to source voltage
and drain current is given below.
After a certain gate to source voltage (VGS), the drain current ID becomes zero.
This voltage is known as Cut Off Gate Voltage (VGS(off)). This voltage numerically
equals the pinch-off drain to source voltage (Vp).
• Shorted Gate Drain Current (IDSS) − This is the maximum drain current that can
flow through the channel when the gate terminal is in ground potential. This
current is fixed for a JFET and this is called shorted gated drain current and
generally denoted by IDSS.
62

MOSFET
MOSFET:
Metal Oxide Semiconductor Field Effect Transistor
Dr. S. M. Gulhane
63

MOSFET
 FETs have a few disadvantages
 high drain resistance,
 moderate input impedance and
 slower operation.
MOSFET overcomes these disadvantages
 MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor.
 Also called as IGFET meaning Insulated Gate Field Effect Transistor.
 In general, the MOSFET is a four-terminal device with a Drain (D),
Source (S), Gate (G) and a Body (B)/Substrate (SS) terminals. The body
terminal will always be connected to the source terminal hence, the
MOSFET will operate as a three-terminal device.
MOSFET
64

Classification of MOSFET
 Enhancement mode MOSFET (E-MOSFET) and
 Depletion mode MOSFET (D-MOSFET),
MOSFETs are further classified based on the material used for
construction as n-channel and p-channel.
 n-channel depletion mode MOSFET
 p-channel depletion mode MOSFET
 n-channel enhancement mode MOSFET
 p-channel enhancement mode MOSFET
MOSFET
65

D-MOSFET
• Depletion-type MOSFET:
 The depletion –type MOSFET has characteristics similar to those of a JFET
between cutoff and saturation i.e between VGS =0 to VGS = VGSoff and it
also has the added feature of characteristics to extend beyond saturation.
 In JFET for its operation, the Gate to Source voltage VGS should always be
reverse biased and Drain to Source voltage VDS should be forward biased.
But in MOSFET, the voltage VGS can either be reverse or forward biased.
When reverse biased it just act similar to JFET and the MOSFET is said to be
working in depletion mode. When VGS is forward biased, higher current
than the IDSS flows through it and the MOSFET is said to be in
enhancement mode.
 Thus Depletion-type MOSFET can operate in both depletion and
enhancement mode. Where as enhancement-type MOSFET is operated in
only enhancement mode.
66

n-type Depletion MOSFET Construction
D-MOSFET
67
 A p-type substrate is used as
the foundation on which the
device is constructed.
 Two n+-doped regions linked
by an n-channel lies on a p-
doped substrate
 The Drain (D) and Source (S)
terminals are connected
through metallic contacts to
the n-doped regions.
 The substrate is either
internally connected or taken
out as an additional terminal
labeled SS resulting in four
terminal device.
+
+

n-type Depletion MOSFET Construction
D-MOSFET
68
 The gate is insulated from
the n-channel by a very thin
layer of silicon dioxide (SiO2)
and a gate terminal is taken
out through metallic contact.
 SiO2 layer act as an insulator
which sets up opposing electric
fields within the dielectric when
an external field is applied.
 Due to SiO2 insulating layer,
there is no direct electrical
connection between the gate
and channel which accounts for
very high input impendence of
MOSFET.

Basic Operation:
D-MOSFET
69
When VGS=0 and VDS is applied across
drain to source terminals, the free
electrons enters from the source get
attracted towards positive terminal
through n-channel and a current flow
similar to that through the channel of JFET
 When a negative voltage VGS is
applied, the negative potential at the gate
will tend to reple electrons towards the p-
type substrate and attract holes from the
p-type substrate thereby recombining the
electrons and holes which reduces the
number of free electrons in the channel
and hence the current flowing through it.

Basic Operation:
D-MOSFET
70
More the negative bias, the higher is
the rate of recombination and therefore
lesser is the flow of drain current.
When VGS=>VGSoff, all the free
electrons get recombined with holes, the
channel becomes depleted of charge
carriers, the pinch-off occurs and hence
no current flows.
 When a positive voltage VGS is applied,
the gate will draw additional free
electrons from the p-substrate due to the
reverse leakage current and establish new
carriers through the collisions. As the VGS
continues to increase in the positive
direction, the drain current is increased at
a rapid rate.

71
Basic Operation: Thus the application of positive
voltage VGS, enhance the level of
free carriers in the channel
compared to that encountered
with VGS =0 V.
 For this reason, in the region of
positive gate-to-source voltage, the
MOSFET is said to be operating in
enhancement mode whereas in
the region of VGS=0 and negative
VGS, the MOSFET is said to be
operating in depletion mode.
 The Schokley’s equation is
applicable for the depletion type
MOSFET characteristics in both the
depletion and enhancement
region.
MOSFET

72
p-channel Depletion MOSFET :
 The p-channel Depletion MOSFET is similar to the n-channel except that
the voltage polarities and current directions are reversed.
D-MOSFET

MOSFET
73
Differentiating points between MOSFET and JFET
 In MOSFET or IGFET, the gate is insulated from the channel where as in JFET
Gate is not insulated from the channel.
 In MOSFET, channel and gate forms parallel plate capacitor; in JFET, channel
and gate forms two pn junctions.
 MOSFET has four leads. The substrate is normally connected to the source
making it three terminal device; JFET has 3 leads
 JFET can be operated in depletion mode only; D-MOSFET can be operated in
both depletion and enhancement mode; E-MOSFET can be operated in
enhancement mode only.
 The insulated gate in MOSFETs result in much greater input impedance than
that of JFET.
 Inter electrode capacitance are independent of bias voltage and these
capacitances are smaller incase of MOSFETs than JEFT.
 It is easier to fabricate MOSFET than JFET

E-MOSFET:
Enhancement Mode - Metal Oxide Semiconductor
Dr. S. M. Gulhane
74

n-type Enhancement MOSFET Construction
E-MOSFET
75
 A p-type substrate is used as the
foundation on which the device is
constructed.
 The Drain (D) and Source (S)
terminals are connected through
metallic contacts to n-doped
regions.
 The absence of channel between
two n-doped regions is the primary
difference between depletion and
enhancement type MOSFET
The SiO2 layer isolate the gate
from the region between the source
and drain.
Channel
is absent

Basic Operation:
E-MOSFET
76
 when VGS=0V and VDS=0V, the
absence of channel between drain and
source will result in zero current.
 when VGS=0V and VDS is some positive
voltage, there exist two reverse biased
junction between the n-doped regions
and p-substrate and absence of channel
between source and drain which cause
zero current to flow.
 Thus, when VGS=0 and voltage VDS is
applied across drain to source terminals,
the absence of channel will result in zero
drain current as against the depletion
type MOSFET where ID=IDSS when VGS=0.

Basic Operation:
E-MOSFET
77
 When VGS and VDS are set to some
positive voltages, then the positive potential
get established at drain and the gate with
respect to the source
 The positive potential at gate will repel the
holes in p-type substrate along the edge of
the SiO2 layer however the electrons which is
minority carrier in p-substrate will be
attracted to the positive gate and get
accumulated in the region near the surface of
the SiO2 layer. The insulating SiO2 layer
prevent the electrons being absorbed by
positive gate.
 As VGS increases, the concentration of
electrons increases such that a channel is
induced between drain and source which
allow flow of electrons from drain to source
hence the flow of drain current.
+
+

Basic Operation:
E-MOSFET
78
 The level of VGS that starts flow of
current is called threshold voltage VGS(th)
or V . For N-type MOSFET it is referred to
VTN
 Since the channel is not in existent with
VGS=0V and enhance by the application of
positive VGS, this type of MOSFET is called
an enhancement mode MOSFET.
 Both depletion and enhancement type
MOSFETs have enhancement region.
 The depletion type MOSFETs can operate
in both depletion and enhancement regions
whereas enhancement type MOSFET can
only operate in enhancement regions.
+
+

Basic Operation:
E-MOSFET
79
Figure a. when VGS < VTN , Figure b. when VGS => VTN ,

Basic Operation: Applying a small VDS
E-MOSFET
80
 when VGS > VTN , application of a small
VDS causes a current iD to flow through an
induced channel which increases with
increase in VDS.
 An E-MOSFET with a small VDS is applied
acts as a resistance whose value is
determined by VGS.
 when VGS < VTN, iD =0, R= infinity
 when VGS > VTN, a channel is induced
causing flow of electrons, hence flow of iD,
making R finite
 as VGS increases, free electrons
increases, drain current increases and R
decreases.

Basic Operation:
E-MOSFET
81
 when VGS > VTN, a channel is induced and
application of positive VDS cause drain current
to flow.
 Now if you keep VGS fixed and VDS is
increased, the drain terminal becomes more
positive than gate. The charge carriers get
attracted towards drain rather getting
accumulated near SiO2 surface and hence the
charge density in the channel towards drain
decreases. Therefore, increase in VDS will
narrow down the induced channel towards
drain but the high potential at drain attract
increased number of charge carriers to flow
through narrow channel.
 with further increase in VDS, the drain
current will eventually reach to a saturation
level that occurs due to pinch-off process
depicted by the narrower channel..
n
n

Basic Operation:
E-MOSFET
82
 Increase in VGS will cause the pinch-off
to occur at higher value of VDS than the
earlier.
Thus higher the VGS, higher is the current
flow and higher is the value of VDS that
cause pinch-off or saturation condition.
 The saturation value of VDS is given by
 If VGS < VT, the drain current ID = 0 and
the MOSFET is said to be in cutoff region
 for VGS > VT and VDS <= VGS-VT, the
MOSFET operate in non-saturation or
triode region
for VGS >VT and VDS >= VGS-VT, the
MOSFET operate in saturation or pinch-off
region

Drain Characteristics:
E-MOSFET
83
 In non-saturation or triode region.
VGS > VTN and VDS < VDS(sat)
 when VGS > VTN and VDS >
VDS(sat) =>saturation region
where Cox is the oxide capacitance
per unit area.
The capacitance is given by
Cox = Єox/tox
where tox is the oxide thickness and
Єox is the oxide permittivity.
Conduction
parameter
Cut-off region VGS < VTN

Drain Characteristics curves:
E-MOSFET
84
 when VGS > VTN and for a
small values of VDS, a
complete channel from drain
to source is induced
 E-MOSFET acts as a resistor
whose value is determined by
VGS
 when VGS > VTN and VDS is
larger value but VDS < VDS(sat)
the induced inversion charge
density near the drain
decreases and hence the
incremental conductance of
the channel at the drain
decreases,

Drain Characteristics :
E-MOSFET
85
 when VGS > VTN and VDS
= VDS(sat), the induced
inversion charge density at
the drain terminal is zero
hence the incremental
channel conductance at the
drain is zero
 Pinch-off point is at drain
 when VGS > VTN and VDS
> VDS(sat), the point in the
channel at which the
inversion charge is zero
moves toward the source
terminal
 The MOSFET operate in
pinch-off/saturation region

Transfer Characteristics: VGS-iD characteristics
E-MOSFET
86

p-channel Enhancement-type MOSFET :
E-MOSFET
87
 The p-channel Enhancement-type MOSFET is similar to the n-channel
except that the voltage polarities and current directions are reversed.

88
Symbol of MOSFET :
Depletion-mode Enhancement-mode
E-MOSFET
p
 The dashed line between the source and drain in enhancement-type
MOSFET reflects that no channel is physically constructed between source
to drain . Channel get induced when VGS > VT.

89
Symbol of MOSFET :
n-channel p-channel
E-MOSFET

Example 1 :
 Consider an n-channel enhancement-mode MOSFET with the following
parameters: VTN = 0.4 V, W = 20 μm, L = 0.8 μm, μn = 650 cm2/V–s, tox = 200 Å,
and ox = (3.9)(8.85 × 10−14) F/cm.
Determine the current when the transistor is biased in the saturation region for
(a) VGS = 0.8 V and (b) VGS = 1.6 V..
Solution
The value of the conduction parameter
E-MOSFET
90
Kn = 1.40 mA/V2

E-MOSFET:
Non-Ideal Characteristics of E-MOSFET
Dr. S. M. Gulhane
91

N-channel E-MOSFET: Ideal characteristics
E-MOSFET
92

E-MOSFET
93
Non-ideal Current–Voltage Characteristics of MOSFET:
There are five non-ideal effects in the current–voltage characteristics of MOSFET
transistors
I. Finite output resistance in the saturation region,
II. Body effect,
III. Sub-threshold conduction,
IV. Breakdown effects, and
V. Temperature effects

E-MOSFET
94
1. Finite output resistance in the saturation region :
iD-VDS relationship in saturation region is given by
where
 In the ideal case, when a MOSFET is biased in the saturation
region, the drain current iD is independent of drain-to-source voltage VDS.
 However, in actual MOSFET iD versus VDS characteristics, a nonzero slope does
exist beyond the saturation point.
 For VDS > VDS(sat), the actual point in the channel at which the inversion
charge goes to zero i.e. the pinch-off point moves away from the drain terminal
 Therefore the effective channel length decreases, producing the phenomenon
called channel length modulation where the channel length varies with VDS.
 Since iD is inversely proportional to the channel length, iD increases with VDS
and hence output resistance has some finite value though very high.

E-MOSFET
95
Finite output resistance in the saturation region :
 Considering the channel length modulation effect, the iD-VDS relationship in
saturation region is written as
 where λ is a positive quantity called the channel-length modulation parameter
which can be obtained from the iD-VDS characteristics by extrapolating the
characteristics curves to the VDS axis
the output resistance,
evaluated at the Q-point, is

E-MOSFET
96
2. Body effect :
 In MOSFET, if the substrate, or body, is connected to the source then the
substrate does not play any role in circuit operation and its existence can be
ignored.
 In integrated circuits, however, the substrates of all n-channel MOSFETs are
usually common and are connected to the most negative potential in the
circuit..
 Consider an example of two n-
channel MOSFETs in series formed on
a single p-substrate.
 the drain of M1 is common to the
source of M2. When the two
transistors are conducting, there is a
nonzero drain-to-source voltage on
M1, which means that the source of
M2 is not at the same potential as the
substrate.

E-MOSFET
97
Body effect :
where VTNO is the threshold voltage for VSB = 0,
γ- is the bulk threshold or body-effect parameter, is related to device properties,
and is typically on the order of 0.5 V1/2; and
φf- is a semiconductor parameter, typically on the order of 0.35 V, and is a
function of the semiconductor doping
 Thus there exist a reverse bias voltage across the source–
substrate pn junction which have an effect on MOSFET
operation.
 This reverse bias widen the depletion layer between the
source–substrate junction and thereby changes the
threshold voltage VTN. This is called the body effect.
 The relation between VTN and VSB is given by
 Equation reveals that the threshold voltage increases due to the body effect
 The body effect can cause a degradation in circuit performance because of the
changing threshold voltage.

E-MOSFET
98
3. Sub-threshold Conduction:
iD-VDS relationship in saturation region is given by
Taking the square root
 Equation shows that √id is a linear function of VGS.
 But in practice, when VGS is slightly less than VTN, the
drain current is not zero, This current which appeared
in practice for VDS less than VTN is called the sub-
threshold current.
 The effect may not be significant for a single device,
but if thousands or millions of devices on an integrated
circuit are biased just slightly below the threshold
voltage, the power supply current will not be zero but
may contribute to significant power dissipation in the
integrated circuit.
 Proper biasing must be design for a MOSFET to
achieve “true” cutoff.

E-MOSFET
99
4. Breakdown Effects:
 Several types of breakdowns occur in MOSFET; they are
 Avalanche breakdown:
 If the applied drain voltage is too high then avalanche multiplication occurs
which cause the p-n junction between the drain and substrate suffers
avalanche breakdown.
 This breakdown usually occurs at voltages of 20V to 150V and results in rapid
increase in current.
 Punch-through breakdown:
 Punch-through breakdown occurs when the drain voltage is large enough for
the depletion region around the drain to extend completely through the
channel to the source terminal.
 It occurs in devices with small size having relatively short channel. This effect
causes the drain current to increase rapidly with only a small increase in
drain voltage.
 Punch-through breakdown effect occurs at lower voltages (20V). Normally
punch-through does not result in permanent damage to the device.

E-MOSFET
100
Breakdown Effects:
 Near-avalanche or snapback breakdown :
 In MOSFET, the source-substrate-drain structure is equivalent to that of a
bipolar transistor with source region serves as the emitter, substrate as
base and drain as the collector. It is important to keep this BJT OFF all the
times by keeping the potential of the base as close to the emitter potential
otherwise the potential at the base would turn on the BJT and lead the
device into latchup condition which would destroy the device.
 Breakdown in an oxide:
 If the electric field in the oxide becomes large enough, breakdown can also
occur in the oxide. In the MOSFET of oxide layer thickness of 500 Å, the
gate to source voltage of about 30V would cause breakdown in an oxide
 Since the MOSFET has very high input impedance at the gate and a very
small input capacitance, a small amount of static charge accumulating on
the gate can cause the breakdown voltage to be exceeded.
 To prevent the accumulation of static charge, a gate protection device, such as a
reverse-biased diode, is usually included at the input of a MOS integrated circuit.

E-MOSFET
101
5. Temperature effects:
 In MOSFET, both the threshold voltage VTN and conduction parameter Kn are
functions of temperature.
 The magnitude of the threshold voltage decreases with temperature, which
means that the drain current increases with temperature at a given VGS.
 However, the conduction parameter decreases as the temperature increases.
 With increasing temperature, the effect of decrease in Kn is more dominant than
decrease in VTN, therefore the net effect of increasing temperature is a decrease
in drain current at a given VGS.
 A decreasing value of Kn inherently limits the channel current and provides
stability for a power MOSFET.

E-MOSFET:
DC Biasing and DC Analysis of E-MOSFET
Dr. S. M. Gulhane
102

D.C. Biasing for MOSFET
• Biasing Circuits used for MOSFET:
103
 An essential step in the design of a MOSFET amplifier
circuit is the establishment of an appropriate dc operating
point.
 Biasing circuit ensures operation of MOSFET in the
saturation region for all expected input-signal levels.
 The operating point of the MOSFET is located at the
coordinate (VDS, ID) on the characteristic graph.

• Feedback Biasing :
104
 A popular biasing arrangement for enhancement-type MOSFETs
 Here the large feedback resistance RG forces the dc voltage at the gate to
be equal to that at the drain (because IG = 0). Since IG=0 mA and
VRG=0 V, the dc equivalent network appears as shown
 A direct connection now exists between drain and gate, resulting in

• DC loadline:
105

Example 1 :
 Determine IDQ and VDSQ for the
enhancement-type MOSFET
E-MOSFET
106
 Solution:
We have
ID(ON) = 6 mA
VGS(ON) = 8 V
VGS(Th) = 3 V
ID = Kn(VGS- VGS(Th) )2
Kn
From the dc equivalent circuit
VGS = VDS
VDD = ID RD+ VDS
VDS = VDD - ID RD
VGS = VDS = VDD - ID RD

E-MOSFET
107
ID = Kn(VDD - ID RD - VGS(Th) )2
ID = 0.24x(12 - 2xID - 3)2
ID = 0.24x(9 - 2ID )2
ID = 0.24x(81- 36xID +4xID
2 )
ID = 19.44- 8.64 ID + 0.96(ID )2
0= 19.44- 9.64 ID + 0.96(ID )2
0= (ID )2 – 10.04ID +20.25
ID1 = 2.8 mA or ID2 = 7.24 mA
VGS1 = VDS = VDD - ID RD = 12 - 2x 2.8 = 6.4 V
VGS2 = VDS = VDD - ID RD = 12 - 2x 7.24 = -2.48 V VGS1 < VGS(Th) X
VGS1 > VGS(Th) √
IDQ = 2.8 mA VDSQ = 6.4 V √

Example 2 :
Draw Transfer Characteristics and DC
load line and determine IDQ and VDSQ
E-MOSFET
108
 Solution:
We have
ID(ON) = 6 mA
VGS(ON) = 8 V
VGS(Th) = 3 V
Kn
VGS = VGS(Th) =3 => ID = 0
ID = 0.24(VGS- VGS(Th) )2
VGS = 6 => ID = 2.16 mA
VGS = 8 => ID = 6 mA
VGS =10 => ID = 11.76 mA

From the DC equivalent circuit
E-MOSFET
109
VGS = VDS
VDD = ID RD+ VDS
VDS = VDD - ID RD
VGS = VDS = VDD - ID RD
VGS = 12- ID x 2K
Two extreme points on DC load line
Can be obtained for VGS = 0 and ID = 0
VGS =0 => ID= 6mA
ID= 0 => VGS =12 V
From the figure
IDQ= 2.75mA and VGSQ = 6.4 V
VDSQ = VGSQ = 6.4 V
2K
12 V

• Voltage Devider Biasing :
110
 Another popular biasing arrangement for enhancement-type MOSFETs
Since IG=0 mA
VG = VGS + ID RS
VDD = ID RD+ VDS + ID RS
VGS = VG - ID RS
VDS = VDD - ID (RD+ RS)

• Example 3 :
111
Determine IDQ, VGSQ, and VDS for the network
ID(ON) = 3 mA
VGS(ON) = 10 V
VGS(Th) = 5 V
 Solution:
We have ID = Kn(VGS- VGS(Th) )2
Kn
From the circuit
ID = 0.12(18 – 0.82ID- 5)2

ID = 0.12(13 – 0.82ID)2
ID = 0.12x(169- 21.32xID +0.67xID
2 )
ID = 20.28- 2.56 ID + 0.08(ID )2
0= 20.28- 3.56 ID + 0.08(ID )2
0= (ID )2 – 44.5ID +253.5
ID1 = 6.71 mA or ID2 = 37.79 mA
VGS1=VG-ID1RS = 18- 0.82x 6.71= 12.5V
VGS2=VG-ID2RS= 18- 0.82x 37.79 = -12.98V VGS1 < VGS(Th) X
VGS1 > VGS(Th) √
IDQ = 6.71 mA √
VDS = VDD - ID (RD+ RS) = 40 – 6.71(3+0.82) = 14.36 V
IDQ = 6.71 mA VDSQ = 14.36 V √

Example 4 :
For the network determine:
(a) IDQ, (b) VGSQ and VDSQ,
(b) (c) VD and VS. (d) VDS.
E-MOSFET
113
ID(ON) = 5 mA
VGS(ON) = 7 V
VGS(Th) = 4 V
Example 5 :
For the voltage-divider configuration
determine:
(a) IDQ and VGSQ, (b) VD and VS.

114
Example 6: Calculate the drain current and drain-to-source voltage of a
common source circuit with an n-channel enhancement-mode MOSFET. Find the
power dissipated in the transistor. Given R1 = 30 k, R2 = 20 k, RD = 20 k,
VDD = 5 V, VTN = 1 V, and Kn = 0.1 mA/V2.
From the circuit
= (0.1)(2 − 1)2 = 0.1 mA
VDS = VDD − ID RD
= 5 − (0.1)(20) = 3 V
PT = ID x VDS = (0.1)(3) = 0.3 mW
Since VDS (3V) > VDS(sat) = VGS – VTN = 2-1 =1 => MOSFET is in saturation

E-MOSFET
E-MOSFET:
AC equivalent circuit and Parameters,
Dr. S. M. Gulhane
115

E-MOSFET
Parameters of E-MOSFET
• AC drain resistance (rd) − It is the ratio of change in the drain source voltage
(ΔVDS) to the change in drain current (ΔID) at constant gate-source voltage. It is
expressed as,
• Transconductance parameter (gm): It is the ratio of change in drain current
(ΔID) to the change in gate source voltage (ΔVGS). It is expressed as,
116
rd = (ΔVDS)/(ΔID) at constant VGS
gm = 2Kn(VGS- VGS(Th) )

E-MOSFET
Parameters of E-MOSFET
• Amplification Factor (µ) − It is the ratio of change in drain-source voltage
(ΔVDS) to the change in gate-source voltage (ΔVGS). It is expressed as,
117
µ = (ΔVDS)/(ΔVGS)

E-MOSFET
AC equivalent circuit of n channel E-MOSFET
Small signal equivalent Circuit
118
Since rd is very high
can be neglected from the ckt
• The MOSFET behaves as a voltage-
controlled current source.
• It provides a drain current
proportional to vgs.
• The input resistance is very high —
ideally infinite.
• The output resistance — is also high

E-MOSFET
E-MOSFET as an Amplifier
• In the saturation region, the MOSFET acts as a voltage-controlled current source:
Changes in the gate-to-source voltage vGS causes changes in the drain current iD.
• Thus the saturated MOSFET behaves as trans-conductance amplifier
119
For the circuit output voltage v0 is given by
v0 = vDS = VDD – RDiD
So, changes in vi causes changes in iD which in
turn changes v0.
Thus, the trans-conductance amplifier is
converted into a voltage amplifier.

E-MOSFET
Large signal Transfer Characteristic of MOSFET Circuit
120cutoff
• Load line equation
v0=vDS= VDD – RDiD
• for vi < VTH the transistor will be cut off, iD
will be zero, and v0 = vDS = VDD (point A).
• As Vi exceeds VTH the transistor turns on, iD
increases, and v0 decreases. This
corresponds to points along the segment of
the load line from A to B.
• Saturation-region operation continues until
v0 decreases below vDSsat
• When vDS < vDSsat, the MOSFET enters its
triode region.
• For Vi > VIB, the transistor is driven deeper
into the triode region and voltage decreases
slowly towards zero.

E-MOSFET
Large signal Transfer Characteristic of MOSFET Circuit
121

E-MOSFET
MOSFET as a Switch
• When the MOSFET is used as a switch, it is operated at the
extreme points of the transfer curve.
• The device is turned off by keeping, v < VTH which provide
v0 = VDD.
• The switch is turned on by applying a voltage close to VDD. Here,
v0 is very small.
122

E-MOSFET
E-MOSFET Common Source Amplifier
• For the FET to operate as a linear amplifier, the transistor must be biased in the
saturation region, and the instantaneous drain current iD and drain-to-source voltage
vDS must be confined to the saturation region.
• The device is biased at a somewhere near to the middle of the curve. The voltage signal
to be amplified vi is then superimposed on the dc bias voltage.
• dc voltage VIQ.
123

E-MOSFET
AC equivalent circuit of E-MOSFET
For drawing an ac equivalent circuit of E-MOSFET amplifier Circuit
• Assume all Capacitors C1, C2 as short circuit elements for ac signal
• Short circuit the dc supply
• Replace the MOSFET by its small signal model
124

E-MOSFET
AC equivalent circuit of E-MOSFET
For drawing an ac equivalent circuit of E-MOSFET amplifier Circuit
• Assume all Capacitors C1, C2, Cs as short circuit elements for ac signal
• Short circuit the dc supply
• Replace the MOSFET by its small signal model
125

E-MOSFET
Common Source E-MOSFET Amplifier Analysis
126

 Example: For the circuit shown in Figure , the parameters are: VDD = 3.3 V, RD = 10 k,
R1 = 140 k, R2 = 60 k, and RSi = 4 k. The transistor parameters are: VT N = 0.4 V, Kn = 0.5
mA/V2, and λ = 0.02 V−1. Determine operating point and ac signal parameters
E-MOSFET
127
gm = 2Kn(VGSQ- VGS(Th) )
IDQ = Kn(VGSQ- VGS(Th) )2
gm = 2x0.5(0.99- 0.4 ) = 0.59 mA/V
Since VDSQ >(VGSQ −VTN),
the transistor is biased in the
saturation region.
We need to
determine
IDQ, VDSQ,
Av, Zi, Zo,
gm, r0

E-MOSFET
Analysis of Drain-feedback biased Common source Amplifier
129
To determine Zo:
Substituting Vi=0 V will result in
Vgs=0 V and gmVgs =0, with a short
circuit path from gate to ground RF,
rd, and RD are then in parallel and
Vo = - gmVgs Zo
Vgs=Vi
Vo = - gmVi Zo

E-MOSFET
Analysis of Drain-feedback biased Common source Amplifier
130

E-MOSFET
E-MOSFET Source follower (Common Drain Amplifier)
131
S
DG
+ vgs - S
D
G
ro

E-MOSFET
E-MOSFET Source follower Analysis
132
Vg
Vg
Vg
 Equation shows that the magnitude of
the voltage gain is always less than unity.
 Since the output signal is essentially
equal to the input signal, the circuit is
called a source follower.
Vg

E-MOSFET
E-MOSFET Source follower Analysis
Vg
With Vi =0 and Vo=Vx test signal voltage the voltage Vgs is directly
appear across the current source gmVgs .
This means that the effective resistance of the current source is 1/gm.

E-MOSFET
E-MOSFET Configuration Comparison

E-MOSFET
High frequency equivalent circuit of E-MOSFET
• There are four internal parasitic capacitances that are occurred in MOSFET when
operating in the saturation region
• Cgs - Capacitance between Gate and Source terminals
• Cgd - Capacitance between Gate and Drain terminals
• Csb - Capacitance between Source region and Body terminals
• Cdb - Capacitance between Drain region and Body terminals
135
When the source is connected to
the body, then the Cgs and Csb
capacitance effect can be clubbed
in a single capacitive effect Cgs
n n
Cgsp - Overlap Capacitance gate-source
Cgdp - Overlap Capacitance gate-drain

E-MOSFET
High frequency equivalent circuit of E-MOSFET
• Typical values are
Cgs =25 fF, Cgd = 2 fF, Cdb = 5 fF
• In the above model, Cgd, although small, plays a significant role in determining the
high-frequency response of amplifiers and thus can not be neglected.
• Capacitance Cdb, can usually be neglected.
136
S
DG

E-MOSFET
Miller Capacitance:
• In high frequency equivalent circuit the gate to drain capacitance is appeared in
between input and output . As per Miller theorem, these capacitances is effectively
represented as separate input and output capacitances, called the Miller Capacitances.
• As per the Miller theorem, the effective input capacitance is the value of feedback
capacitance multiplied by the factor (1-Av) while the output capacitance is the value of
feedback capacitance divide by (Av-1) /Av where Av is the gain of the device.
137

E-MOSFET
Frequency Response of MOSFET Common Source Amplifier
138
RL=r0 || RD

E-MOSFET
139
For input coupling capacitor
For output coupling capacitor

E-MOSFET
140

E-MOSFET: NMOS and CMOS inverter
Dr. S. M. Gulhane
141

E-MOSFET
N-MOSFET as a diode/register
• When the gate of the MOSFET is connected
to the drain and VGS = VDS > VT it acts like
a diode with characteristics similar to a pn-
junction diode.
• When the gate is connected to the drain of
an enhancement MOSFET, the MOSFET is
always in the saturation region.
• The relationship between current and
voltage
• MOSFET as a diode can be used as a
nonlinear precision resistor and can be used
as an active load.
142

E-MOSFET
• MOSFET in Saturation region (large R’s)
• Diode-connected loads (small R’s)
• MOSFET Triode-Region (moderate R’s)
143
MOSFET as a resistor (Active Load)

E-MOSFET
• By holding the MOSFET in
saturation with the source and
gate at a constant DC voltage, it
can be used as an active load for
high resistances.
• Drain is connected to circuit
• ro is inversely proportional to ID
144
MOSFET as a high resistor
R= r0

E-MOSFET
• A Diode connected MOSFET can
be used to achieve small
resistances.
• The Drain is directly connected
to Gate, and therefore it can
only be operated in saturation
(or cutoff)
145
MOSFET as a small (precision) resistor

E-MOSFET
146
MOSFET as a moderate resistor
when VGS > VTN then for a small
values of VDS (VDS < VDSsat), a
complete channel from drain to
source is induced

MOSFET as a moderate resistor
E-MOSFET
147
 An E-MOSFET with a small VDS (VDS <
VDSsat) is applied acts as a resistance
whose value is determined by VGS.
 when VGS < VTN, iD =0, R= infinity
 when VGS > VTN, a channel is induced
causing flow of electrons, hence flow of iD,
making R finite
 as VGS increases, free electrons
increases, drain current increases and R
decreases.

E-MOSFET
148
VDD = ID RD+ VDS
VDS = VDD - ID RD
MOSFET as a Switch (logic Inverter) with resistive load

E-MOSFET
149
V0 = VDS = VDD - ID RD
• When the MOSFET is used as a switch, it is
operated at the extreme points of the
transfer curve.
• The output voltage is expressed as shown
• The device is turned off by keeping, Vi < VTH
which provide Vo = VDS = VDD since ID = 0. (The
MOSFET operates in cut-off region)
• The switch is turned on by applying a voltage
close to VDD which causes high value of ID to
flow and hence Vo is very small. (The
MOSFET operates in non-saturation region)
• The common-source MOSFET circuit can be
used as a logic inverter with the "low"
voltage level close to 0 V and the "high" level
close to VDD.

E-MOSFET
150
• In non-saturation region, iD is given by
iD = Kn[2(vGS-VTN )vDS –vDS
2]
iD = Kn[2(vi-VTN )v0–v0
2]
v0 = VDS = VDD - ID RD
v0 = VDD - KnRD[2(vi-VTN )v0–v0
2]

E-MOSFET
MOSFET as a Switch (logic Inverter)
151VDS = VDD - ID RD
The sharpness of the transition region
increases and the output decreases with
increasing load resistance

E-MOSFET
N-MOSFET logic inverter with resistive load
• The common-source MOS circuit can be used as a logic inverter with the
"low" voltage level close to 0 V and the "high" level close to VDD.
152
VDS = VDD - ID RD
 For input logic low level (Vi < VTH )
Output is logic high (Vo = VDD )
 For input logic high level (Vi = VDD)
Output is logic high (Vo ≈ 0 )

E-MOSFET
153
n-MOS Inverter with Active load
•Active Load
•Active Load always in saturation
•Less chip area
A MOSFET as active load always operates in
the saturation region
When vi < VTHD , the driver MOSFET operates
in cut-off region and iD = 0.
 0 = KL(vDSL-VTNL )2
 vDSL-VTNL = 0
From figure vDSL = VDD - v0
 VDD - v0 - VTNL = 0
 VOH = v0 max = VDD - VTNL

E-MOSFET
154
When vi = VDD, driver MOSFET operates in non-saturation
region
iDD = KD[2(vGSD-VTND )vDSD –vDSD
2]
iDD = KD[2(vi-VTND )v0–v0
2]
Since iDD = iDL = KL(vDSL-VTNL )2
KD[2(vi-VTND )v0–v0
2] = KL(VDD - v0 -VTNL )2
Which indicate that the relation between vi and vo is
nonlinear.
KD/KL=(W/L)D /(W/L)L
The conduction parameter can be expressed in terms
of aspect ratio of MOSFET as
KD=(k’D/2 )(W/L)D similarly KL=(k’L/2 )(W/L)L

The above equations can be used in design of NMOS
inverter

E-MOSFET
155
•Active Load
•Active Load always in saturation
•Less chip area
The minimum output voltage, or the logic 0
level, for a high input decreases with increasing
KD/KL ratio

E-MOSFET
156
Example: Design a NMOS inverter for v0 =0.10 V and vi =2.5 V
Given VDD = 3V, k’n = 60uA/V2 ,VTN = 0.5V
Also determine the power dissipation in the inverter
Solution: Since iDD (non-saturation) = iDL(saturation)
KD[2(vGSD-VTND )vDSD–vDSD
2] = KL(vGSL -VTNL )2
vGSD=vi vDSD=v0 and vGSL=vDSL=VDD - v0
KD[2(vi-VTND )v0–v0
2] = KL(VDD - v0 -VTNL )2
KD[2(2.5 - 0.5)(0.1)– (0.1)2] = KL(3 – 0.1 – 0.5)2
KD/KL= 14.8 = (W/L)D /(W/L)L
Assuming (W/L)L = 1 => (W/L)D = 14.8
iD = iDD = iDL =KL(VDD - v0 -VTNL )2
KL=k’L/2 (W/L)L = 60/2 (1) =30 uA/V2
iD = 30(3 – 0.1 – 0.5 )2 = 172.8 uA
P = iDVDD = 172.8 x 3 = 518.4 uW
 High power dissipation

E-MOSFET
• Complementary MOS (CMOS) has much smaller
power dissipation than the NMOS and hence
make CMOS attractive for IC.
• The CMOS inverter is a series combination of a
p-MOS and n-MOS MOSFET.
• The p-MOS transistor is connected to the
supply voltage VDD and n-MOS transistor is
connected to the ground.
• The gates of the two are connected together to
form the input and two drains are connected
together to form the output.
Consider the two extreme cases:
• When vi is at logic-0 level, which is 0 V, and
• when vi is at logic-1 level, which is VDD volts.
157
CMOS Logic Inverter
CMOS has replaced NMOS at all
level of integration, in both analog
and digital applications

E-MOSFET
158
CMOS Logic Inverter n-MOSFET p-MOSFET
Cut-off region vGS < VTN vSG < |VTP|
Saturation region
vDS > vDS(sat)
iD = Kn(vGS - VTN)2 iD = Kp(vSG + VTP )2
vDS(sat) = (vGS - VTN) vDS(sat) = (vSG + VTP)
Non saturation region
vDS < vDS(sat)
iD= Kn[2(vGS-VTN )vDS –vDS
2] iD= Kp[2(vSG + VTP )vSD –vSD
2]
Parameters Kn, VTN and VTN > 0 Kp, VTP and VTP < 0

E-MOSFET
• A separate p-well region is formed
within n-substrate. The n-channel
MOSFET is fabricated in the p-well
region and p-channel MOSFET is
fabricated in the n-substrate
• The hole mobility in p-MOSFET is
approximately one half of the
electron mobility in n-MOSFET.
Therefore a width of p-MOSFET
must be approximately twice as
large as that of n-MOSFET.
159
CMOS Logic Inverter

E-MOSFET
vi is at logic-0 level,
vi = 0 V, v0 = VDD
160
CMOS Logic Inverter
equivalent circuit
Consider the two extreme
cases:
When vi is at logic-0 level,
which is 0 V, and
when vi is at logic-1 level,
which is VDD volts.
For vi = 0, n-MOS is cut-
off, iDN = 0, iDP = 0, and
v0 = VDD
This condition prevail for
vi <= VTN

E-MOSFET
vi is at logic-1 level,
vi = VDD
161
CMOS Logic Inverter
equivalent circuit
For vi = VDD , p-MOS is
cut-off, iDP = 0, iDN = 0,
and v0 = 0
This condition prevail for
VDD -|VTP| <= vi <= VDD
Ideally, the current in the
CMOS inverter in either
steady-state condition is
zero.
In practice there occur a
small leakage current in
both steady-state
condition due to reverse
biased pn junction.

E-MOSFET
162
CMOS Logic Inverter: Transfer Curve
VOPt=
VONt=
VIt=

E-MOSFET
• The CMOS inverter usually design to have
and
• But K’n > K’p
• This can achieved if width of the PMOS is made two to three times than
that of the NMOS device in order to provide a symmetrical transition.
• symmetrical transition results in wide noise margin.
163
CMOS Inverter Design Consideration
| |

E-MOSFET
• In the static state for the input is
either a logic 0 or a logic 1, power
dissipation in CMOS inverter is
virtually zero.
• However, during the switching cycle
from one state to another, current
flows and power is dissipated.
• CMOS logic circuits are used to
drive other MOS devices for which
the input impedance is capacitance.
• During switching cycle this load
capacitance are charged and
discharged.
164
Switch Model of Dynamic Behavior
If the inverter is switched at frequency f, then the power dissipated in the
inverter is given by
P = f CL VDD
2

E-MOSFET
165
CMOS Inverter
Example: For a CMOS inverter with CL =2 pF biased at VDD = 5 V
determine the power dissipation in the inverter. The inverter is switched at
f = 100 KHz
Solution:
P = f CL VDD
2
P = 105 x 2 x 10-12 x 52= 5 uW

E-MOSFET
Example: Sketch the voltage
transfer curve for a CMOS inverter
with specifications Kn = Kp, VTN = -
VTP = 0.8 V, VDD = 5 V
Solution:
166
CMOS Inverter
VOPt=3.3V
VONt= 1.7V
VIt=2.5 V
0.8 V
VOH= 5V
4.2 V 5V

E-MOSFET
• Constant current source/ current mirrors are used for biasing in IC
• On an IC chip with number of amplifier stages, a constant dc current (called a
reference current) is generated at one location and is then replicated at
several other locations for biasing a various amplifier stages through a
process of current steering.
• It provides the advantages that
 In case of variations in power supply voltage or temperature, the bias
currents of various stages track each other.
 Need only one precision resistor external to chip for providing a stable
reference current for all the amplifier stages in the IC chip.
• They are also utilized as an active loads in amplifier circuits.
167
Current Source

E-MOSFET
• The drain current of Q1 is supplied by VDD through R which is external to IC
168
MOSFET Current Source
Thus Io is related to Iref
by the aspect ratio of
transistors

E-MOSFET
169
Basic MOSFET Current Mirror
 For simplicity and generality, a current source is
shown for supplying input reference current.
 If the transistors are identical then Io is mirror
image of Iref Io=Iref, therefore the circuit is
referred as current mirror.
 The name current mirror is used irrespective of
the ratio of device dimension.
 The ratio Io/Iref is referred as the current
gain or current transfer ratio of the current
mirror.

E-MOSFET
170
Current steering Circuit to bias several transistors in an IC
 Note that Q1 pulls its current
I2from a load and Q5 pushes its
current I5 into a load. Thus Q5 act
as a current source and Q2 acts as
a current sink.
 In IC both current sink and
current source are needed..

E-MOSFET
171
MOSFET Scaling
 Design of high density chip in MOS VLSI technology requires that packing
density should increase accordingly size of the IC must decrease.
 This reduction in size, i.e. the dimensions of the MOSFET is termed as
SCALING.
 Moore's law state that the number of transistors on integrated circuits
doubles approximately every two years.
 With the use of Moore’s Law, capabilities such as, processing speed, memory
capacity, efficiency have been improved greatly.
 Scaling is defined as the process of reducing the horizontal and vertical
dimensions of a MOS device by some scaling factor S, which is greater than 1.
 Thus, the scaled device is obtained by simply dividing the key dimensions of
the MOSFET, such as channel length (L), channel width (W), oxide thickness
(tox), junction depth (Xj), by a scaling factor .

E-MOSFET
172
Types of MOSFET Scaling
 Two types of schemes
Constant Field (Full Scaling) and Constant Voltage
Constant Field (Full Scaling):
 In constant-field scaling, the MOSFET dimensions as well as supply voltages
are scaled by the same scaling factor S, S >1.
 The scaling of supply and terminal voltages maintain the same electric field as
that of the original device; hence the name constant-field scaling.
 This scaling is also called full scaling as the dimensions as well as supply
voltages are scaled simultaneously.
 In this scaling technique, the charge densities are advanced by S in order to
maintain the magnitude of the fields inside.

E-MOSFET
173
Types of MOSFET Scaling
 Two types of schemes
Constant Voltage Scaling:
 In constant-voltage scaling, the geometrical dimensions of the MOSFET are
reduced by scaling factor S while the power supply and terminal voltages are
kept constant.
 In this scaling technique, the charge densities are advanced by S2 in order to
maintain the magnitude of the fields inside.
 This scaling is also called partial scaling as the scaling is applied to only
physical dimensions and not to voltages.
 In this scheme, all voltages are kept constant to maintain the same logic levels
as that of the original to provide a compatible interface with peripherals and
I/O devices.


E-MOSFET
174
Parameters of MOSFET Scaling before and after scaling:
Parameters Before Scaling After Scaling
Constant Field
Scaling
Constant Voltage
Scaling
Channel Length L L/S L/S
Channel Width W W/S W/S
Area WL WL/S2 WL/S2
Oxide Thickness tox Tox/S Tox/S
Threshold Voltage Vth Vth/S Vth
Supply voltage VDD VDD/S VDD
Gate voltage VGS VGS/S VGS
Drain voltage VDS VDS/S VDS
Doping NA and ND NA S and ND S NA S2 and ND S2

E-MOSFET
Effect of MOSFET Scaling in scaled device characteristics:
Parameters Before
Scaling
After Scaling
Constant Field Scaling Constant Voltage Scaling
Oxide Capacitance Cox SCox SCox
Gate-Source Capacitance CGS CGS/S CGS/S
delay τ=CGSV/I τ/S τ/S2
Drain current ID ID/S SID
Power Dissipation PD PD/S2 SPD
Power Density PD/WL PD/WL S3(PD/WL)
𝜖ox =Cox tox  C’ox = 𝜖’ox /t’ox  C’ox = 𝜖ox /(tox /S)  C’ox = SCox
Total Gate to source Capacitance C’GS = C’ox W’L’  C’ox = CGS/S
ID = Kn(VGS - VTN)2  I’D = K’n(V’GS – V’TN)2  I’D = (SKn)(VGS/S - VTN/S)2  I’D = ID/S
Constant Field Scaling

E-MOSFET
176
Pros and Cons Types of MOSFET Scaling
 Increased component density
 Increased speed: in constant field scaling delay decreases by a factor of S
while in constant voltage scaling delay decreases by a factor of S²
 Power dissipation: Power dissipation in constant field scaling is reduced by a
factor of S² as P´= P/S² whereas the Power dissipation in constant voltage
scaling is increased by a factor of S
 Reliability of the scaled device: In constant field scaling the electric field as
well as the power density before and after the scaling remains the same
thereby improves the reliability of the scaled device. in constant voltage
scaling the power density is increased by a factor of S3. Also there occurs
increase in the peak electric fields. The combine effect eventually leads to
reliability problems such as oxide breakdown or elctro-migration.

E-MOSFET
177
1.With the help of structural diagram, drain characteristics and transfer
characteristics, explain the various regions of operation of n-channel EMOSFET.
2. Explain various non-ideal characteristics of n-MOSFET.
3. For the feedback bias configuration shown
(a) Determine IDQ, VGSQ and VDSQ.
(b) Cross verify the results by obtaining the
Transfer Characteristics and DC load line.
Question Bank

E-MOSFET
178
4. For the voltage-divider configuration
shown the parameters are: VDD = 12 V, RD
= 3 k, R1 = 300 k, R2 = 200 k, RS = 2k. and
RSi = 4k. The transistor parameters are:
VTN = 2 V, Kn = 1 mA/V2, and λ = 0.
a. Determine operating point and ac signal
parameters.
b. Draw the Frequency response and
explain the factors that cause the
reduction in gain at higher and lower
frequencies.

E-MOSFET
179
1.Explain how the MOSFET can be used as diode and active resistors. Explain
constant current mirror using MOSFET.
2. Explain the n-MOS inverter with active load and how the transfer
characteristics get affected by W/L ratios of driver and Load MOSFET.
3. Describe the operation of CMOS inverter. For a CMOS inverter with CL =2.2 pF
biased at VDD = 5 V determine the power dissipation in the inverter when it is
switched at f = 500 KHz.
4. Explain MOSFET scaling. Compare the pros and cons of constant field and
constant voltage scaling. Show that the power dissipation and power density in
constant voltage scaling get multiplied by S and S3 respectively.
Question Bank

MOSFET....complete PPT

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