This document summarizes research on verifying driver logic for the Advanced eXtensible Interface (AXI) protocol using the Universal Verification Methodology (UVM). It describes the AXI protocol and its advantages over other protocols. The research implemented a UVM verification environment for an AXI design with a master and slave agent. It verified the signaling of the five AXI channels: write address, write data, write response, read address, and read data. Address calculation formulas and the driver logic flow for each channel are presented. Simulation results showed the AXI design operated correctly according to the protocol.
Detecting Aspect Intertype Declaration Interference at Aspect Oriented Design...IJERA Editor
Implementing crosscutting concerns requires aspect oriented developers to be enabled to introduce some mem-bers to core concerns modules along with other. This may lead to a problem of interference among modules, either between classes and aspects or among aspects themselves. Such conflicts may cause program to crash at runtime. Interference problem is addressed but with complex solutions that become more complicated propor-tionally with the project size. In this work a relational database approach and relational algebra is used to detect intertype declaration interferences in aspect oriented design models in order to capture conflicts in an early stage before having it as runtime error. Detection is done in an approach not that complex as the previous ones.
VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVMVLSICS Design
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the
other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response,
read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.
VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVMVLSICS Design
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the
other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response,
read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.
Top Trending Article in Academia! - VLSI design & Communication Systems (VLSI...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
October 2020: Top Read Articles in VLSI design & Communication Systems - Arti...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
December 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
November 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
September 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
Detecting Aspect Intertype Declaration Interference at Aspect Oriented Design...IJERA Editor
Implementing crosscutting concerns requires aspect oriented developers to be enabled to introduce some mem-bers to core concerns modules along with other. This may lead to a problem of interference among modules, either between classes and aspects or among aspects themselves. Such conflicts may cause program to crash at runtime. Interference problem is addressed but with complex solutions that become more complicated propor-tionally with the project size. In this work a relational database approach and relational algebra is used to detect intertype declaration interferences in aspect oriented design models in order to capture conflicts in an early stage before having it as runtime error. Detection is done in an approach not that complex as the previous ones.
VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVMVLSICS Design
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the
other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response,
read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.
VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVMVLSICS Design
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the
other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response,
read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.
Top Trending Article in Academia! - VLSI design & Communication Systems (VLSI...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
October 2020: Top Read Articles in VLSI design & Communication Systems - Arti...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
December 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
November 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
September 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
Top Trending Articles - International Journal of VLSI design & Communication ...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
August 2021 -Top 10 Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
April 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
June 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
October 2020: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
May 2020: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
July 2020: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
This article presents the design and simulation of a 2.2GHz low noise amplifier (LNA) for wireless communication systems using Multisim. The LNA was designed using MGF1302 PHEMT transistor and optimized to achieve maximum gain and minimum noise figure. The design was simulated in Multisim and results showed a gain of 14.5dB and noise figure of 1.2dB at 2.2GHz, meeting the requirements for wireless applications. Testing the LNA design through simulation allows verification of the circuit's performance before implementation.
June 2020: Top Downloaded Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
March 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
May 2022: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
April 2022: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
June 2022: Top 10 Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
A Review On AMBA AHB Lite Protocol And Verification Using UVM MethodologyTodd Turner
This document provides an overview of the AMBA protocol and discusses the AMBA AHB-Lite protocol and verification using the UVM methodology. It classifies the different types of AMBA protocols and describes their features and specifications. It then discusses the AMBA AHB-Lite protocol in more detail, describing its operation and features as a high performance bus with one master and multiple slaves. Finally, it describes the need for verification, the evolution of verification techniques, and the advantages of the Universal Verification Methodology (UVM) over conventional verification methods.
Design and verification environment for amba axi protocol for soc integrationeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity
This document summarizes a research paper that proposes a synthesizable checker for the AMBA AXI protocol. The AXI protocol is commonly used for on-chip communication in system-on-chip (SoC) designs. The proposed checker contains 44 rules to verify AXI protocol compliance and was implemented using Verilog. Simulation results showed the checker design requires 70.7K gate counts and has a critical path of 4.13 ns, allowing it to operate at 242 MHz. The checker is intended to improve SoC integration by verifying correct protocol usage and helping debug communication issues.
This document summarizes a research paper that proposes a synthesizable AMBA AXI protocol checker to verify communication properties in a system-on-chip (SoC) design. It contains 44 rules to check the AMBA AXI protocol and provides verification of the AXI master, slave, and default slave protocols. The protocol checker uses a rule-based methodology and model simulation to thoroughly verify chip-level behaviors and help debug issues, improving design quality and reducing verification time and costs.
IRJET - Analysis of Different Arbitration Algorithms for Amba Ahb Bus Protoco...IRJET Journal
This document analyzes and compares different arbitration algorithms for the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance Bus (AHB) protocol used in System on Chip (SoC) designs. It describes the AMBA specification and AHB bus. It then examines three arbitration algorithms - static fixed priority, round robin, and modified round robin. Simulation results show the modified round robin algorithm provides the fastest response time to bus requests while using more logic than the other methods. Overall, the modified round robin algorithm is concluded to be the most efficient approach for handling multiple concurrent bus requests in terms of speed and performance.
April 2020: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
More Related Content
Similar to VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM
Top Trending Articles - International Journal of VLSI design & Communication ...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
August 2021 -Top 10 Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
April 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
June 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
October 2020: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
May 2020: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
July 2020: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
This article presents the design and simulation of a 2.2GHz low noise amplifier (LNA) for wireless communication systems using Multisim. The LNA was designed using MGF1302 PHEMT transistor and optimized to achieve maximum gain and minimum noise figure. The design was simulated in Multisim and results showed a gain of 14.5dB and noise figure of 1.2dB at 2.2GHz, meeting the requirements for wireless applications. Testing the LNA design through simulation allows verification of the circuit's performance before implementation.
June 2020: Top Downloaded Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
March 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
May 2022: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
April 2022: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
June 2022: Top 10 Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
A Review On AMBA AHB Lite Protocol And Verification Using UVM MethodologyTodd Turner
This document provides an overview of the AMBA protocol and discusses the AMBA AHB-Lite protocol and verification using the UVM methodology. It classifies the different types of AMBA protocols and describes their features and specifications. It then discusses the AMBA AHB-Lite protocol in more detail, describing its operation and features as a high performance bus with one master and multiple slaves. Finally, it describes the need for verification, the evolution of verification techniques, and the advantages of the Universal Verification Methodology (UVM) over conventional verification methods.
Design and verification environment for amba axi protocol for soc integrationeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity
This document summarizes a research paper that proposes a synthesizable checker for the AMBA AXI protocol. The AXI protocol is commonly used for on-chip communication in system-on-chip (SoC) designs. The proposed checker contains 44 rules to verify AXI protocol compliance and was implemented using Verilog. Simulation results showed the checker design requires 70.7K gate counts and has a critical path of 4.13 ns, allowing it to operate at 242 MHz. The checker is intended to improve SoC integration by verifying correct protocol usage and helping debug communication issues.
This document summarizes a research paper that proposes a synthesizable AMBA AXI protocol checker to verify communication properties in a system-on-chip (SoC) design. It contains 44 rules to check the AMBA AXI protocol and provides verification of the AXI master, slave, and default slave protocols. The protocol checker uses a rule-based methodology and model simulation to thoroughly verify chip-level behaviors and help debug issues, improving design quality and reducing verification time and costs.
IRJET - Analysis of Different Arbitration Algorithms for Amba Ahb Bus Protoco...IRJET Journal
This document analyzes and compares different arbitration algorithms for the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance Bus (AHB) protocol used in System on Chip (SoC) designs. It describes the AMBA specification and AHB bus. It then examines three arbitration algorithms - static fixed priority, round robin, and modified round robin. Simulation results show the modified round robin algorithm provides the fastest response time to bus requests while using more logic than the other methods. Overall, the modified round robin algorithm is concluded to be the most efficient approach for handling multiple concurrent bus requests in terms of speed and performance.
April 2020: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Similar to VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM (20)
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Software Engineering and Project Management - Introduction, Modeling Concepts...Prakhyath Rai
Introduction, Modeling Concepts and Class Modeling: What is Object orientation? What is OO development? OO Themes; Evidence for usefulness of OO development; OO modeling history. Modeling
as Design technique: Modeling, abstraction, The Three models. Class Modeling: Object and Class Concept, Link and associations concepts, Generalization and Inheritance, A sample class model, Navigation of class models, and UML diagrams
Building the Analysis Models: Requirement Analysis, Analysis Model Approaches, Data modeling Concepts, Object Oriented Analysis, Scenario-Based Modeling, Flow-Oriented Modeling, class Based Modeling, Creating a Behavioral Model.
Discover the latest insights on Data Driven Maintenance with our comprehensive webinar presentation. Learn about traditional maintenance challenges, the right approach to utilizing data, and the benefits of adopting a Data Driven Maintenance strategy. Explore real-world examples, industry best practices, and innovative solutions like FMECA and the D3M model. This presentation, led by expert Jules Oudmans, is essential for asset owners looking to optimize their maintenance processes and leverage digital technologies for improved efficiency and performance. Download now to stay ahead in the evolving maintenance landscape.
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.
An improved modulation technique suitable for a three level flying capacitor ...IJECEIAES
This research paper introduces an innovative modulation technique for controlling a 3-level flying capacitor multilevel inverter (FCMLI), aiming to streamline the modulation process in contrast to conventional methods. The proposed
simplified modulation technique paves the way for more straightforward and
efficient control of multilevel inverters, enabling their widespread adoption and
integration into modern power electronic systems. Through the amalgamation of
sinusoidal pulse width modulation (SPWM) with a high-frequency square wave
pulse, this controlling technique attains energy equilibrium across the coupling
capacitor. The modulation scheme incorporates a simplified switching pattern
and a decreased count of voltage references, thereby simplifying the control
algorithm.
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
DOI : 10.5121/vlsic.2018.9303 31
VERIFICATION OF DRIVER LOGIC USING AMBA-
AXI UVM
Bijal Thakkar1
and V Jayashree2
1
Department of Electronics Engineering, D.K.T.E, Ichalkaranji, Maharashtra,India
2
D.K.T.E.Ichalkaranji,Shivaji University,Kolhapur,Maharashtra, India
ABSTRACT
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of
its high performance and high-frequency operation without using complex bridges. AXI is also backward-
compatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is
presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the
other protocol but it is possible in AXI because it contains different write address and data channels and
AXI also supports out of order transfer based on the transaction ID which is generated at the start of the
transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification
Methodology (UVM).The signaling of the five channels such as write address, write data, write response,
read address, read data channel of AXI protocol are considered for verification. According to the AXI
protocol,the signals of these channels are driven to the interconnect and results are observed for single
master and single slave. The driver logic has been implemented and verified successfully according to AXI
protocol using the Rivera Pro. The results observed for single master and single slave have shown the
correctness of AMBA-AXI design in Verilog.
KEYWORDS
AMBA(Advance Microcontroller Bus Architecture),AXI(Advanced Extensible Interface),UVM(Universal
Verification Methodology),channel.
1. INTRODUCTION
AXI stands for (Advanced Extensible Interface) and it is an On-Chip communication protocol. It
is a part of the Advanced Microcontroller Bus Architecture (AMBA) developed by ARM
(Advanced RISC Machines) company. It provides high-frequency operation without using
complex bridges to meet the interface requirements of a wide range of components. It is suitable
for memory controllers with high initial access latency. AXI-UVM has separate address/control
and data phases. It supports for unaligned data transfers using byte strobes instead of supporting
burst based transactions with only start address issued. Also supports multiple outstanding
addresses without order response. Because of these features, AXI is the most commonly used on
chip bus protocols in the day-to-day high performance System On Chip (SOC’s).
In reference on AMBA AXI protocol specification, the signalling information and handshaking
signals and working of protocol from AMBA-AXI protocol has been reported[1].Gayathri M, and
RSA have reported, an efficient SV-UVM framework for the verification of Serial Gigabit Media
Independent Interface (SGMII) IP core, a single lane 1.25 Gbps data rate interface between
Ethernet Media Access Control (MAC) and Physical (PRY) layer[2].Rini Sebastian ,SGA
reported on benefits associated with Assertion Based Verification (ABV) which was successfully
applied to multiple levels of design abstraction . All simulations were carried out in NCsim and
waveforms were analysed in Simvision. All the assertions carried out were ensured without any
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
failure and shown the coverage capability
Independent Interface (SGMII) IP core[3]. Golla Mahesh, Sakthivel.S.M reported on Verification
IP for an AMBA-AXI Protocol using System Verilog using the questa sim tool. In the verification
environment mailbox are used for communication between the different classes have presented
the coverage driven verification environment with functional coverage of 100%[4].
Mahendra.B.M,Ramachandra.A.C,Bus Functional Model Verification IP Development of AXI
Protocol have verified the various features of the AXI such as out of burst transactions and out of
order transactions and they are verified using the questa sim simulator [5]. AnushaRanga, L.
HariVenkatesh, Venkanna, Design and Implementation of AMBA
for SOC Integration have presented the rules for verifying the SOC as SOC is the complex design
and contains various components and in that they have verified the AXI protocol using the model
sim simulator[6].
Taking the literature review into account we have attempted to implemented the reusable
verification environment UVM (Universal Verification Methodology) for testing slave agent of
AXI protocol using AMBA bus. Also coverage analysis has been used as a parameter for testing
and also to demonstrate its usefulness using various assertions.
architecture of the AXI-UVM is described
for AMBA-AXI with address calculation formulae
presented in sectionIV. Conclusion and future scope is explained in section V.
2. THEORETICAL BACKGROUND
AXI provide flexibility in the implementation of interconnect architectures and it is also
backward-compatible with existing AHB and APB interfaces because of this main features AXI
protocol is efficient protocol because of its ultra
viz.; write address, write data,write response, read address, read data channel of AXI protocol.
These are considered for verification. The
shown in Figure1. Universal Verification Methodolog
test. 2.2. Testblock having environ
under test or interconnect
2.1 TOP BLOCK HAVING TEST
The top block creates instances of the Device Under Test (DUT) of the test bench. Top interface
module holds all the signals of the DUT. This acts as a link to the monitor, the driver and the
DUT.
Figure. 1. Block diagram of AMBA AXI
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
failure and shown the coverage capability of ABV through a case study on Serial Gigabit Media
pendent Interface (SGMII) IP core[3]. Golla Mahesh, Sakthivel.S.M reported on Verification
AXI Protocol using System Verilog using the questa sim tool. In the verification
mailbox are used for communication between the different classes have presented
the coverage driven verification environment with functional coverage of 100%[4].
Mahendra.B.M,Ramachandra.A.C,Bus Functional Model Verification IP Development of AXI
col have verified the various features of the AXI such as out of burst transactions and out of
order transactions and they are verified using the questa sim simulator [5]. AnushaRanga, L.
HariVenkatesh, Venkanna, Design and Implementation of AMBA-AXI Protocol Using VHDL
for SOC Integration have presented the rules for verifying the SOC as SOC is the complex design
and contains various components and in that they have verified the AXI protocol using the model
nto account we have attempted to implemented the reusable
verification environment UVM (Universal Verification Methodology) for testing slave agent of
AXI protocol using AMBA bus. Also coverage analysis has been used as a parameter for testing
demonstrate its usefulness using various assertions. Accordingly in Section II, the
is described where as in section III the methodology implemented
AXI with address calculation formulae is presented. Results and observations are
presented in sectionIV. Conclusion and future scope is explained in section V.
ACKGROUND:ARCHITECTURE OF AXI-UVM
provide flexibility in the implementation of interconnect architectures and it is also
compatible with existing AHB and APB interfaces because of this main features AXI
because of its ultra-high-performance. It contains of f
write address, write data,write response, read address, read data channel of AXI protocol.
These are considered for verification. The implemented AMBA AXI-UVM block diagram as
shown in Figure1. Universal Verification Methodology consist three blocks. 2.1.Top block having
Testblock having environment with virtual sequence and 2.3. Environment and design
EST
The top block creates instances of the Device Under Test (DUT) of the test bench. Top interface
module holds all the signals of the DUT. This acts as a link to the monitor, the driver and the
Figure. 1. Block diagram of AMBA AXI-UVM
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
32
Serial Gigabit Media
pendent Interface (SGMII) IP core[3]. Golla Mahesh, Sakthivel.S.M reported on Verification
AXI Protocol using System Verilog using the questa sim tool. In the verification
mailbox are used for communication between the different classes have presented
the coverage driven verification environment with functional coverage of 100%[4].
Mahendra.B.M,Ramachandra.A.C,Bus Functional Model Verification IP Development of AXI
col have verified the various features of the AXI such as out of burst transactions and out of
order transactions and they are verified using the questa sim simulator [5]. AnushaRanga, L.
col Using VHDL
for SOC Integration have presented the rules for verifying the SOC as SOC is the complex design
and contains various components and in that they have verified the AXI protocol using the model
nto account we have attempted to implemented the reusable
verification environment UVM (Universal Verification Methodology) for testing slave agent of
AXI protocol using AMBA bus. Also coverage analysis has been used as a parameter for testing
Accordingly in Section II, the
where as in section III the methodology implemented
is presented. Results and observations are
UVM
provide flexibility in the implementation of interconnect architectures and it is also
compatible with existing AHB and APB interfaces because of this main features AXI
ins of five channels,
write address, write data,write response, read address, read data channel of AXI protocol.
UVM block diagram as
2.1.Top block having
Environment and design
The top block creates instances of the Device Under Test (DUT) of the test bench. Top interface
module holds all the signals of the DUT. This acts as a link to the monitor, the driver and the
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
33
2.2 TEST BLOCK HAVING ENVIRONMENT WITH VIRTUAL SEQUENCE
Test block is a top level block in UVM. It has two purposes first one is to create the environment
block and then to connect the sequencer to the sequence.
2.3 ENVIRONMENT AND DESIGN UNDER TEST OR INTERCONNECT
Environment consist of the five blocks viz, 2.3.1. Master agent 2.3.2 Slave agent
2.3.3 Scoreboard 2.3.4. Coverage 2.3.5. Virtual sequencer.
The environment is top most UVM verification environment.
2.3.1 MASTER AGENT
Master agent holds drivers, sequencer and monitors.Sequences signify the input to the DUT, such
as instructions, networking packets and bus transactions.
2.3.2 SLAVE AGENT
Slave agent holds drivers, sequencer and monitors. Monitors, sequencers and drivers can be used
independently.
2.3.3 SCOREBOARD
Scoreboard is built to check the response from the DUT against the expected response. It is done
by comparing them to the Reference Model.
2.3.4 COVERAGE
Functional coverage is the determination of how much functionality of the design has been
exercised by the verification environment.
2.3.5 VIRTUAL SEQUENCER
The virtual sequencer has the handles of physical sequencers which are pointed to physical
sequencers in the environment.
3. METHODOLOGY OF IMPLEMENTATION
Implementation of AXI-UVM is carried out using Rivera-Pro software. Rivera-Pro is tool
provided by aldec to deliver its customer innovative products in shorter time with high
performance simulation and containing supporting features that support verification libraries such
as UVM and also support verilog,system C and many more.The driver logic channels to be
verified for AXI-UVM are five which are mentioned as further.
3.1 Signals of write address channel
3.2 Signals of write data channel
3.3 Signals of write response channel
3.4 Signals of read address and control channel
3.5 Signals of read data and control channel
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
3.1. SIGNALS OF WRITE ADDRESS
During write logic transaction, the master asserts the AWVALID (
signifies availability of valid write address and control
drives valid address and control information. When asserted, AWVALID must remain
asserted until the rising clock edge after the slave asserts
ready indicates that slave is ready to accept an address
can be either HIGH or LOW. When AWREADY is HIGH the slave accepts any valid
address that is presented to it. The flowchart
address channel is as shown in figure 2.
Figure.2.Flow cha
Write Address calculation protocol is as shown below
i. Start Address = AxADDR
ii. Number of Bytes = 2 ^ AxSIZE
iii. Burst Length = AxLEN + 1
Here A stands for the AXI protocol
channels.
iv.
INT
v. The equation used to determine the address of the first transfer in a burst:
Address_1 = Start Address.
vi. For an INCR burst, and for a WRAP burst for which the address has not wrapped, this
equation (3) determines the address of any transfer after the first transfer in a burst:
AlignedAddress
! 1#$ %. '( )*+
vii. For a WRAP burst, the Wrap Boundary variable defines the wrapping boundary:
, -)%. * INT
x(No.ofBytes)x (Burst length)
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
DDRESS CHANNEL
During write logic transaction, the master asserts the AWVALID (Write address valid
signifies availability of valid write address and control information) signal only when it
drives valid address and control information. When asserted, AWVALID must remain
asserted until the rising clock edge after the slave asserts of AWREADY(Write address
slave is ready to accept an address). The default state of AWREADY
can be either HIGH or LOW. When AWREADY is HIGH the slave accepts any valid
address that is presented to it. The flowchart for implementation of Signals for write
is as shown in figure 2.
Figure.2.Flow chart of driver logic of write address channel
Write Address calculation protocol is as shown below
AxADDR
AxSIZE
+ 1
Here A stands for the AXI protocol and x stands for W for write channels and
// 011
23.34 56 01
7 $ %. %( 8*+ (1)
The equation used to determine the address of the first transfer in a burst:
Address_1 = Start Address.
For an INCR burst, and for a WRAP burst for which the address has not wrapped, this
determines the address of any transfer after the first transfer in a burst:
AlignedAddress
)*+
For a WRAP burst, the Wrap Boundary variable defines the wrapping boundary:
INT
// 011
23.34 56 01
)x Burstlength))
x(No.ofBytes)x (Burst length)
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
34
Write address valid
) signal only when it
drives valid address and control information. When asserted, AWVALID must remain
Write address
). The default state of AWREADY
can be either HIGH or LOW. When AWREADY is HIGH the slave accepts any valid
for implementation of Signals for write
x stands for W for write channels and R for read
(2)
For an INCR burst, and for a WRAP burst for which the address has not wrapped, this
determines the address of any transfer after the first transfer in a burst:
(3)
For a WRAP burst, the Wrap Boundary variable defines the wrapping boundary:
(4)
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
3.2. SIGNALS OF WRITE DATA
The flow chart for the write data channel is similar to the write address channel shown in Fig
2.The difference is AWVALID,AWREADY,AWID(write address ID signal is an identification
tag for write data) in the address channel are WVALID(write valid signal indicates that a valid
write data is available),WREADY (write ready signal signifies that slave can ac
data ) and WID (write ID tag signal is an ID tag of write data transfer) signals in the write data
channel. The master asserts the WVALID signal only when it drives valid write data. When
asserted, WVALID remains high until the rising cloc
WLAST (write last this indicates the last transfer in burst) signal while it is driving
transfer in the burst.
3.3 SIGNALS OF WRITE RESPONSE CHANNEL
As per the AXI protocol of driver logic, during write
BVALID(write response valid,this signal indicates that the channel signaling a valid response)
signal only when it drives valid write response. When asserted, BVALID remains asserted until
the rising clock edge after the master asserts BREADY (Response ready, signal indicates that
master can accept a write response). The default state of BREADY can be HIGH, but only if the
master can always accepts a write response in a single cycle. The implementation of Signals
write response channel is as shown in flowchart for of Figure 3.
Figure.3.Flow chart of driver logic of write response channel
3.4 SIGNALS OF READ ADDRESS CHANNEL
The flowchart of the read address channel is similar to the write address channel,th
difference is the signals AWVALID,AWREADY,AWID in the write address channel is replaced
by the ARVALID(read address valid signal indicates that slave is ready to accept an
address),ARREADY(Read address ready signal indicates that slave is ready to a
and ARID (Read address ID signal is the identification tag for read address signals) as shown in
figure 4. As per AXI protocol of driver logic, during read logic transaction the master asserts the
ARVALID signal only when it
ARVALID must remain asserted until the rising clock edge after the
signal. The default state of ARREADY can be either HIGH or LOW. This specification
recommends a default state of HIGH, provided the slave must be able to accept any valid address
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
IGNALS OF WRITE DATA CHANNEL
The flow chart for the write data channel is similar to the write address channel shown in Fig
difference is AWVALID,AWREADY,AWID(write address ID signal is an identification
write data) in the address channel are WVALID(write valid signal indicates that a valid
ble),WREADY (write ready signal signifies that slave can accept valid write
data ) and WID (write ID tag signal is an ID tag of write data transfer) signals in the write data
channel. The master asserts the WVALID signal only when it drives valid write data. When
WVALID remains high until the rising clock edge after the slave asserts WREADY.
WLAST (write last this indicates the last transfer in burst) signal while it is driving t
ONSE CHANNEL
As per the AXI protocol of driver logic, during write logic transaction,the slave asserts the
BVALID(write response valid,this signal indicates that the channel signaling a valid response)
signal only when it drives valid write response. When asserted, BVALID remains asserted until
er the master asserts BREADY (Response ready, signal indicates that
master can accept a write response). The default state of BREADY can be HIGH, but only if the
master can always accepts a write response in a single cycle. The implementation of Signals
write response channel is as shown in flowchart for of Figure 3.
Figure.3.Flow chart of driver logic of write response channel
ESS CHANNEL
The flowchart of the read address channel is similar to the write address channel,th
difference is the signals AWVALID,AWREADY,AWID in the write address channel is replaced
by the ARVALID(read address valid signal indicates that slave is ready to accept an
address),ARREADY(Read address ready signal indicates that slave is ready to accept an address)
and ARID (Read address ID signal is the identification tag for read address signals) as shown in
figure 4. As per AXI protocol of driver logic, during read logic transaction the master asserts the
ARVALID signal only when it drives valid address and control information. When asserted,
ARVALID must remain asserted until the rising clock edge after the slave asserts the ARREADY
signal. The default state of ARREADY can be either HIGH or LOW. This specification
recommends a default state of HIGH, provided the slave must be able to accept any valid address
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
35
The flow chart for the write data channel is similar to the write address channel shown in Fig
difference is AWVALID,AWREADY,AWID(write address ID signal is an identification
write data) in the address channel are WVALID(write valid signal indicates that a valid
cept valid write
data ) and WID (write ID tag signal is an ID tag of write data transfer) signals in the write data
channel. The master asserts the WVALID signal only when it drives valid write data. When
k edge after the slave asserts WREADY.
the final write
logic transaction,the slave asserts the
BVALID(write response valid,this signal indicates that the channel signaling a valid response)
signal only when it drives valid write response. When asserted, BVALID remains asserted until
er the master asserts BREADY (Response ready, signal indicates that
master can accept a write response). The default state of BREADY can be HIGH, but only if the
master can always accepts a write response in a single cycle. The implementation of Signals of
The flowchart of the read address channel is similar to the write address channel,the only
difference is the signals AWVALID,AWREADY,AWID in the write address channel is replaced
by the ARVALID(read address valid signal indicates that slave is ready to accept an
ccept an address)
and ARID (Read address ID signal is the identification tag for read address signals) as shown in
figure 4. As per AXI protocol of driver logic, during read logic transaction the master asserts the
address and control information. When asserted,
slave asserts the ARREADY
signal. The default state of ARREADY can be either HIGH or LOW. This specification
recommends a default state of HIGH, provided the slave must be able to accept any valid address
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
that is presented to it. The implementation of Sig
shown in flowchart of Fig.4.
Figure.4.Flow chart of driver logic of read address channel.
3.5 SIGNALS OF READ DATA AND CONTROL CHANNEL
The read data and control channel is similar to the write data channel
5,The slave assert the RVALID(Read valid signal indicates that the channel is signaling read data
) signal only when it drives valid read data. When asserted, RVALID must remain asserted until
the rising clock edge after the maste
accept read data and response information). Even if a slave has only one source of read data, it
asserts the RVALID signal only in response to a request for data. The master interface uses the
RREADY signal to indicate that it accepts the data. The implemented driver logic of read data
channel is as shown in flowchart of Fig.5
Figure.5.Flow chart of driver logic of read data channel
4 RESULTS AND OBSERVATION
Result for verification of AMBA
Rivera-Pro is presented as below
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
that is presented to it. The implementation of Signals of read address and control channel is as
Figure.4.Flow chart of driver logic of read address channel.
AND CONTROL CHANNEL
The read data and control channel is similar to the write data channel as shown in the flowchart
5,The slave assert the RVALID(Read valid signal indicates that the channel is signaling read data
) signal only when it drives valid read data. When asserted, RVALID must remain asserted until
the rising clock edge after the master asserts RREADY (Read ready signal indicates master can
accept read data and response information). Even if a slave has only one source of read data, it
asserts the RVALID signal only in response to a request for data. The master interface uses the
signal to indicate that it accepts the data. The implemented driver logic of read data
channel is as shown in flowchart of Fig.5
Figure.5.Flow chart of driver logic of read data channel
BSERVATION
Result for verification of AMBA-AXI for all five channels obtained from UVM environment of
Pro is presented as below
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
36
nals of read address and control channel is as
as shown in the flowchart
5,The slave assert the RVALID(Read valid signal indicates that the channel is signaling read data
) signal only when it drives valid read data. When asserted, RVALID must remain asserted until
r asserts RREADY (Read ready signal indicates master can
accept read data and response information). Even if a slave has only one source of read data, it
asserts the RVALID signal only in response to a request for data. The master interface uses the
signal to indicate that it accepts the data. The implemented driver logic of read data
all five channels obtained from UVM environment of
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
4.1. OUTPUT OF DRIVER L
Figure.6.Output of driver logic of write address channel
It is observed from Figure 6,for output of driver
AWVALID and AWREADY signal is high, then AWID and 32 bit AWADDR is generated as per
address calculation in the protocol.
4.2 OUTPUT OF DRIVER LOGIC
Figure.7.Output of write data channel driver
It is observed from the waveform of Figure 7,that write identification match, WID match is
found with AWID as per the requirement .When WVALID signal is asserted,then WDATA is
sent according to the WID and WLAST signal is seen to be asserted after
the burst.Here length of the data received is decided on the value of signal AWLEN
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
LOGIC OF WRITE ADDRESS CHANNEL
Figure.6.Output of driver logic of write address channel
It is observed from Figure 6,for output of driver logic of write address channel that, when
AWVALID and AWREADY signal is high, then AWID and 32 bit AWADDR is generated as per
address calculation in the protocol.
OGIC OF WRITE DATA CHANNEL
Figure.7.Output of write data channel driver logic
It is observed from the waveform of Figure 7,that write identification match, WID match is
found with AWID as per the requirement .When WVALID signal is asserted,then WDATA is
sent according to the WID and WLAST signal is seen to be asserted after receiving last signal in
the burst.Here length of the data received is decided on the value of signal AWLEN
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
37
logic of write address channel that, when
AWVALID and AWREADY signal is high, then AWID and 32 bit AWADDR is generated as per
It is observed from the waveform of Figure 7,that write identification match, WID match is
found with AWID as per the requirement .When WVALID signal is asserted,then WDATA is
receiving last signal in
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
4.3 OUTPUT OF DRIVER LOGIC
Figure.8. Output of driver logic of write response channel
It is observed from the waveform of Figure 8, on output driver logic of write response channel
that, after receiving all the data from the WDATA correctly, then BVALID signal has been
asserted. Though BREADY can be high or low, BREADY signal is found high as per
requirement of the protocol. Also match between BID, AWID and WID is seen as per
requirement after BVALID signal has arrived and the BRESP signal has gone low
4.4 OUTPUT OF DRIVER LOGIC
Figure.9.Output of driver logic of read address
It is observed from the waveform of Figure 9 that, the read address channel operations are same
as the write address channel. ARADDR and ARID are found to be generated when ARVALID
and ARREADY signal is high. The ARREADY can come before ARVALID o
ARVALID or both ARREADY and ARVALID both can occur at same time. ARVALID and
ARREADY are seen to occur at the same time in the verification of read address channel as an
effect of randomization .
4.5 OUTPUT OF DRIVER LOGI
Figure.10. Output of driver logic of read data channel
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
OGIC OF WRITE RESPONSE CHANNEL
Figure.8. Output of driver logic of write response channel
orm of Figure 8, on output driver logic of write response channel
that, after receiving all the data from the WDATA correctly, then BVALID signal has been
asserted. Though BREADY can be high or low, BREADY signal is found high as per
otocol. Also match between BID, AWID and WID is seen as per
requirement after BVALID signal has arrived and the BRESP signal has gone low.
OGIC OF READ ADDRESS CHANNEL
Figure.9.Output of driver logic of read address channel
It is observed from the waveform of Figure 9 that, the read address channel operations are same
as the write address channel. ARADDR and ARID are found to be generated when ARVALID
and ARREADY signal is high. The ARREADY can come before ARVALID or it can come after
ARVALID or both ARREADY and ARVALID both can occur at same time. ARVALID and
ARREADY are seen to occur at the same time in the verification of read address channel as an
UTPUT OF DRIVER LOGIC READ DATA AND CONTROL CHANNEL
Figure.10. Output of driver logic of read data channel
International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
38
orm of Figure 8, on output driver logic of write response channel
that, after receiving all the data from the WDATA correctly, then BVALID signal has been
asserted. Though BREADY can be high or low, BREADY signal is found high as per
otocol. Also match between BID, AWID and WID is seen as per
It is observed from the waveform of Figure 9 that, the read address channel operations are same
as the write address channel. ARADDR and ARID are found to be generated when ARVALID
r it can come after
ARVALID or both ARREADY and ARVALID both can occur at same time. ARVALID and
ARREADY are seen to occur at the same time in the verification of read address channel as an
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
39
It is seen from the waveform of Figure 10 that, according to the value of ARLEN signal the
length of the data is decided, the RID and ARID match is found as per protocol. RDATA signal
has come in output after receiving RVALID signal. Since RREADY signal can be high or it can
be low this RREADY signal is found to be high in the output as per required in the protocol also
RLAST(read last signal indicates the last transfer in read burst) signal is asserted after receiving
the last data in the burst and as decided according to the burst length.
5 CONCLUSION AND FUTURE SCOPE
In this paper the driver logic has been implemented and verified successfully according to the
protocol using the Rivera Pro and results are observed for single master and single slave. The
results have shown the correctness of AMBA-AXI protocol. Testing the design using coverage as
performance parameter and making it cacheable and bufferable are the future future scopes this
implemented design on AMBA AXI. This design can be used to implement the monitor logic in
which the signals driven by the channels can be collected in the monitor logic and can be
compared in the scoreboard in order to ensure the data driven and collected are exactly the same.
The axi can be used to observe the out of order transactions and out of burst transactions.
ACKNOWLEDGMENT
I would like to express my sincere gratitude towards Prof. Dr. Mrs.V.Jayashree Professor in
Electronics Engineering of DKTE Society's Textile & Engineering Institute, Ichalkaranji (An
Autonomous Institute) , who has been my supervisor. She has been my philosopher, mentor and
guide. She provided me with many helpful suggestions, important advice and constant
encouragement in this work.
REFERENCES
[1] Amba axi protocol specification, arm, 2011.
[2] Gayathri m, rini sebastian, silpa rose mary, anoop thomas, “a sv-uvm framework verification
of sgmii ip core with reusable axi to wb bridge uvc”, ieee ,3rd international on advance
computing and communication systems,jan 22 & 23 ,2016 ,coimbatore, india.
[3] Rini sebastian, silpa rose mary, gayathri m, anoop thomas, “assertion based verification of
sgmii ip core incorporating axi transaction verification model”, ieee,international conference
on control, communication & computing india (iccc), 19-21 november 2015 , trivandrum.
[4] Golla mahesh, sakthivel.s.m, verification ip for an amba-axi protocol using system verilog,
international journal ofengineering research and general science, volume 3, issue 1, january-
february, 2015.
[5] Mahendra.b.m,ramachandra.a.c, bus functional model verification ip development of axi
protocol, international journal ofengineeringresearch andgeneral science, volume 3, special
issue 1, february, 2014
[6] Anusharanga, l. harivenkatesh, venkanna, design and implementation of amba-axi protocol
using vhdl for soc integration, international journal of engineering research and general
science, vol. 2, issue4, july-august 20,2012.
AUTHORS
Bijal Thakkar is currently pursuing her M.Tech in Electronics from Shivaji University,
Ichalkarnji .Doing project in DKTE Society’s Textile & Engineering Institute. She
Obtained her bachelor’s degree in Electronics and communication engineering from
Shivaji University,Kolhapur.Her interest includes,digital circuits design and Verification.