The document summarizes two proposed structures for compact branch-line couplers (BLCs) using miniaturization techniques. The first structure uses open stubs and meandering transmission lines, reducing the area to 61.8% of a conventional design. The second uses open stub and stepped impedance unit cells, reducing the area to 50.8%. Simulation results show the first structure achieves return losses and isolation of -27.8 dB and -27.9 dB respectively with a 312 MHz bandwidth. The second structure achieves comparable performance to previously published measured results. Both miniaturized designs achieve good size reduction while maintaining BLC performance compared to a conventional design.
In this paper, a low pass filter based on T-Shaped resonator is presented. The T-Shaped resonator consists of meandered lines and rectangular patches. Also, the LC model and transfer function of the proposed resonator is presented. For suppression of spurious harmonics, a bandstop structure consists of hexangular patches and open stubs has been utilized. Finally, the wide stopband microstrip lowpass filter with cutoff frequency 2.72 GHz has been simulated, fabricated and measured. The LPF has good characteristics such as wide stopband and insertion loss lower than 0.18 dB in the passband region. The rejection level is less than -20 dB from 2.98 up to 21.3 GHz. The filter size is 10.5 mm×12.7 mm, or 0.131 λg× 0.158 λg, where λg is the guided wavelength. The measured and simulated results of the filter is in good agreement with each other, which show the merits of low insertion loss and wide stopband.
This document describes a compact dual-band bandpass filter using stub-loaded spiral stepped-impedance resonators. The filter operates at 0.35 GHz and 0.9 GHz with a small size of 0.06λg × 0.09λg. It provides good selectivity for both passbands through the generation of eight transmission zeros. Simulated and measured results show the filter achieves high selectivity and improved stopband performance up to 3 GHz compared to other dual-band filter designs.
Wideband Branch Line Coupler with Open Circuit Coupled Lines IJECEIAES
This paper focuses on the design of a Wideband Branch Line Coupler by using open circuits coupled lines technique. The design is implemented by adding four open circuits coupled lines to the structure of the Conventional Branch Line Coupler. The proposed design of Wideband Branch Line C 3 z -3 orts. The prototype is fabricated and measured to validate the simulated results. A similar Wide Bandwidth is observed on simulation and measurement. The structure achieved a fractional bandwidth of 42.63%, and return loss of 21 dB compared to the Conventional Branch Line Coupler (BLC).
Photonic not and_nor_gates_based_on_a_siTamer Saleh
This document proposes and analyzes photonic NOT and NOR logic gates based on a single photonic crystal ring resonator (PCRR). The PCRR is formed by removing rods along the ΓM direction in a square lattice photonic crystal structure. Beam interference theory and 2D FDTD simulations are used to analyze the logic gate behavior. The simulations show the gates can function as NOT and NOR gates without requiring nonlinear materials. An output intensity greater than 50% is defined as logic 1, and less than 50% as logic 0. This approach could potentially be used to integrate photonic logic circuits on a chip.
A Low Phase-Noise VCO Using an Electronically Tunable Substrate Integrated Wa...fanfan he
This document describes the design and testing of a low phase noise voltage-controlled oscillator (VCO) using an electronically tunable substrate integrated waveguide (SIW) resonator. Key points:
- An SIW cavity resonator was designed with a varactor diode coupled to allow electronic tuning of the resonant frequency from 9.32 GHz to 9.95 GHz as the bias voltage was changed.
- A VCO circuit was developed using the tunable SIW resonator and a pHEMT transistor. It achieved a frequency tuning range of 460 MHz and a phase noise of -88 dBc/Hz at 100 kHz offset across the tuning range.
- Measured results demonstrated the potential of
Dualfrequency oshaped 3 way bagley power divider based on tltprjpublications
This document summarizes a research paper published in the International Journal of Electronics and Communication Engineering Research and Development. The paper describes the design of a dual-frequency O-shaped 3-way Bagley power divider. A transmission line transformer is used to achieve equal power splitting at 1 GHz and 2 GHz. The design is simulated and tested, with good agreement between simulation and measurement results. Measurements showed input port matching of -35dB and -30dB at 1GHz and 2GHz respectively, and transmission responses close to the theoretical -4.77dB value. The divider was fabricated on an FR-4 substrate using standard PCB fabrication techniques.
Design and simulation of broadband rectangular microstrip antennaBASIM AL-SHAMMARI
Abstract
In this work, many techniques are suggested and analyses for
rectangular microstrip antenna (RMSA) operating in X-band for 10 GHz
center frequency. These approaches are: lowering quality factor, shifting
feeding point , using reactive loading and modification of the patch shape.
The design of a RMSA is made to several dielectric materials, and the
selection is based upon which material gives a better antenna performance
with reduced surface wave loss. Duroid 5880 and Quartz are the best materials
for proposed design to achieve a broader Bandwidth (BW) and better
mechanical characteristics than using air. The overall antenna BW for RMSA
is increased by 11.6 % with Duroid 5880 with shifted feeding point and with
central shorting pin (Reactive loading) while that for Quartz is 17.4 %.
Modification of patch shape with similar improving techniques gives an
overall increasing VSWR bandwidth of 26.2 % for Duroid 5880 and a
bandwidth of 30.9 % for Quartz. These results are simulated using Microwave
Office package version 3.22, 2000.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This document summarizes a research paper that proposes a new low power dual-edge triggered static D flip-flop (DETFF) design. The proposed DETFF architecture uses two latches connected in parallel to sample data on both the rising and falling clock edges. Simulation results show the proposed DETFF has lower power dissipation (improved by 36-48%), lower power-delay product (improved by 24-42%), and smaller layout area (improved by 63-73%) compared to other conventional DETFF designs. Therefore, the proposed DETFF is well-suited for low power and small area applications.
In this paper, a low pass filter based on T-Shaped resonator is presented. The T-Shaped resonator consists of meandered lines and rectangular patches. Also, the LC model and transfer function of the proposed resonator is presented. For suppression of spurious harmonics, a bandstop structure consists of hexangular patches and open stubs has been utilized. Finally, the wide stopband microstrip lowpass filter with cutoff frequency 2.72 GHz has been simulated, fabricated and measured. The LPF has good characteristics such as wide stopband and insertion loss lower than 0.18 dB in the passband region. The rejection level is less than -20 dB from 2.98 up to 21.3 GHz. The filter size is 10.5 mm×12.7 mm, or 0.131 λg× 0.158 λg, where λg is the guided wavelength. The measured and simulated results of the filter is in good agreement with each other, which show the merits of low insertion loss and wide stopband.
This document describes a compact dual-band bandpass filter using stub-loaded spiral stepped-impedance resonators. The filter operates at 0.35 GHz and 0.9 GHz with a small size of 0.06λg × 0.09λg. It provides good selectivity for both passbands through the generation of eight transmission zeros. Simulated and measured results show the filter achieves high selectivity and improved stopband performance up to 3 GHz compared to other dual-band filter designs.
Wideband Branch Line Coupler with Open Circuit Coupled Lines IJECEIAES
This paper focuses on the design of a Wideband Branch Line Coupler by using open circuits coupled lines technique. The design is implemented by adding four open circuits coupled lines to the structure of the Conventional Branch Line Coupler. The proposed design of Wideband Branch Line C 3 z -3 orts. The prototype is fabricated and measured to validate the simulated results. A similar Wide Bandwidth is observed on simulation and measurement. The structure achieved a fractional bandwidth of 42.63%, and return loss of 21 dB compared to the Conventional Branch Line Coupler (BLC).
Photonic not and_nor_gates_based_on_a_siTamer Saleh
This document proposes and analyzes photonic NOT and NOR logic gates based on a single photonic crystal ring resonator (PCRR). The PCRR is formed by removing rods along the ΓM direction in a square lattice photonic crystal structure. Beam interference theory and 2D FDTD simulations are used to analyze the logic gate behavior. The simulations show the gates can function as NOT and NOR gates without requiring nonlinear materials. An output intensity greater than 50% is defined as logic 1, and less than 50% as logic 0. This approach could potentially be used to integrate photonic logic circuits on a chip.
A Low Phase-Noise VCO Using an Electronically Tunable Substrate Integrated Wa...fanfan he
This document describes the design and testing of a low phase noise voltage-controlled oscillator (VCO) using an electronically tunable substrate integrated waveguide (SIW) resonator. Key points:
- An SIW cavity resonator was designed with a varactor diode coupled to allow electronic tuning of the resonant frequency from 9.32 GHz to 9.95 GHz as the bias voltage was changed.
- A VCO circuit was developed using the tunable SIW resonator and a pHEMT transistor. It achieved a frequency tuning range of 460 MHz and a phase noise of -88 dBc/Hz at 100 kHz offset across the tuning range.
- Measured results demonstrated the potential of
Dualfrequency oshaped 3 way bagley power divider based on tltprjpublications
This document summarizes a research paper published in the International Journal of Electronics and Communication Engineering Research and Development. The paper describes the design of a dual-frequency O-shaped 3-way Bagley power divider. A transmission line transformer is used to achieve equal power splitting at 1 GHz and 2 GHz. The design is simulated and tested, with good agreement between simulation and measurement results. Measurements showed input port matching of -35dB and -30dB at 1GHz and 2GHz respectively, and transmission responses close to the theoretical -4.77dB value. The divider was fabricated on an FR-4 substrate using standard PCB fabrication techniques.
Design and simulation of broadband rectangular microstrip antennaBASIM AL-SHAMMARI
Abstract
In this work, many techniques are suggested and analyses for
rectangular microstrip antenna (RMSA) operating in X-band for 10 GHz
center frequency. These approaches are: lowering quality factor, shifting
feeding point , using reactive loading and modification of the patch shape.
The design of a RMSA is made to several dielectric materials, and the
selection is based upon which material gives a better antenna performance
with reduced surface wave loss. Duroid 5880 and Quartz are the best materials
for proposed design to achieve a broader Bandwidth (BW) and better
mechanical characteristics than using air. The overall antenna BW for RMSA
is increased by 11.6 % with Duroid 5880 with shifted feeding point and with
central shorting pin (Reactive loading) while that for Quartz is 17.4 %.
Modification of patch shape with similar improving techniques gives an
overall increasing VSWR bandwidth of 26.2 % for Duroid 5880 and a
bandwidth of 30.9 % for Quartz. These results are simulated using Microwave
Office package version 3.22, 2000.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This document summarizes a research paper that proposes a new low power dual-edge triggered static D flip-flop (DETFF) design. The proposed DETFF architecture uses two latches connected in parallel to sample data on both the rising and falling clock edges. Simulation results show the proposed DETFF has lower power dissipation (improved by 36-48%), lower power-delay product (improved by 24-42%), and smaller layout area (improved by 63-73%) compared to other conventional DETFF designs. Therefore, the proposed DETFF is well-suited for low power and small area applications.
This paper presents a new structure to implement compact narrowband high-rejection microstrip band-stop filter (BSF). This structure is the combination of two traditional BSFs: Spurline filter and BSF using defected ground structure (DGS). Due to inherently compact characteristics of both Spurline and interdigital capacitance (used as DGS), the proposed filter shows a better rejection performance than Spurline filter and open stub conventional BSF without increasing the circuit size. From, the proposed BSF has a rejection of better than 20dB and the maximum rejection level of 41dB.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORSVLSICS Design
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document summarizes research on novel photonic crystal fiber (PCF) structures with elliptical holes whose dimensions are derived from Dolph Tschebysheff polynomials. Three new PCF structures are proposed and their propagation characteristics are analyzed using simulations. The simulations show that the proposed structures exhibit negligible waveguide dispersion over a wide wavelength range, making them suitable for long distance communications. However, the birefringence of the structures is higher than PCF structures based on Pascal's triangle. The confinement losses of the proposed structures are also slightly higher. In conclusion, the PCF structures derived from Dolph Tschebysheff polynomials show potential for applications requiring low dispersion, but have increased birefringence and losses compared
Design and analysis of microstrip antenna with zig-zag feeder for wireless co...journalBEEI
This document describes the design and analysis of a microstrip antenna with a zig-zag feeder for wireless communication applications. The proposed antenna is designed to have a wide bandwidth of 2-14 GHz. It consists of a zig-zag microstrip feedline connected to a tuning stub printed on one side of a substrate. On the other side of the substrate is a ground plane with zig-zag slots. Parametric analysis was performed to optimize the dimensions for wide bandwidth and acceptable gain between 7.448-5.928 dB. The zig-zag feedline and tuning stub with elliptical slots help improve the impedance matching for wide bandwidth operation suitable for UWB applications. Simulation results for radiation patterns, current distribution, and
This document describes the design and simulation of an ultra-wideband balanced bandpass filter. Key points:
1) The filter uses defected ground structures (DGS) to provide common mode rejection. It has three sections - a pair of UWB filtering units for the differential lines, U-shaped and H-shaped DGSs for lower band suppression, and dumbbell-shaped DGSs for upper band suppression.
2) An equivalent lumped element model is developed and parameters are extracted to represent the common mode response of each section.
3) Simulation results show the filter provides good differential mode propagation and common mode suppression from DC to 18GHz, meeting the requirements for modern communication systems
Compact Stepped Impedance Resonator Bandpass Filter with Tunable Transmission...TELKOMNIKA JOURNAL
This paper proposes a compact microstrip bandpass filter (BPF) with tunable transmission zero,
narrow bandwidth and low insertion loss. Transmission zeros are the key to improve the band rejection
and filter frequency selectivity. A λ/4 stepped impedance resonator (SIR) with two additional via holes has
been adopted to obtain a compact size and a pair of transmission zero (TZ). The BPF is designed to
operate at 3.5 GHz with fractional bandwidth (FBW) of 7.2%.Furthermore, three techniques have been
developed to create a pair of controllable transmission zeros on both side of each passband. The TZ can
be controlled by adjusting either magnetic or electric coupling. The measured return losses and insertion
lossis larger than 18 dB and 2.2 dB respectively. The overall size of the proposed design filter is 5.3mm x
5.5mm without considering the feeding lines.
In this paper, UWB technology operating in broad
frequency range of 3.1-10.6 GHz has shown great achievement
for high- speed wireless communications. to satisfy the UWB
system requirements, a band pass filter with a broad pass
band width, low insertion loss, and high stop-band suppression.
UWB band-pass filter (BPF) with wireless local area network
(WLAN) notch at 5.8 GHz and 3-dB fractional bandwidth of
108% using a microstrip structure is presented. Initially a
two transmission pole UWB band pass filter in the frequency
range 3.1-10.6 GHz is achieved by design a parallel-coupled
microstrip line with defective ground plane structure using
GML 1000 substrate with specification: dielectric constant 3.2
and thickness 0.762 mm at centre frequency 6.85 GHz. In this
structure a ë/4 open circuited stub is introduced to achieve the
notch at 5.8 GHz to avoid the interference with WLAN
frequency with lies the desired UWB band. The design
structure was simulated on electromagnetic circuit simulation
software and fabricated by microwave integrated circuit
technique. The measured VNA results show the close
agreement with simulated results.
A new look on CSI imperfection in downlink NOMA systemsjournalBEEI
- The document analyzes the performance of downlink non-orthogonal multiple access (NOMA) systems under imperfect channel state information (CSI) and Nakagami-m fading.
- It derives closed-form expressions for the outage probability of two users in such NOMA systems considering the joint impact of imperfect CSI and Nakagami-m fading.
- Monte Carlo simulations are conducted to verify the accuracy of the analytical outage probability expressions derived for the two users under the system and channel models considered.
This document describes a proposed new dual edge-triggered D-type flip-flop circuit design with low power consumption. The design achieves dual edge-triggering using two parallel data paths that operate on opposite clock phases. It uses a latch circuit structure with differential input data signals, which reduces capacitance on the clock line. Simulation results show the proposed design has lower power consumption than several existing dual edge-triggered flip-flop designs under different operating conditions, making it well-suited for low-power applications.
DUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTIONijcsit
In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design achieves dual edge-triggered with two parallel data paths work in opposite phases of the clock single. Among them, a latch circuit structure employs differential input data signals which deposits very little capacitance on the clock line is accomplished. For fair comparison, four previously reported DET flipflops along with the proposed DETFF (DET flip-flop) are compared in terms of power consumption and power-delay product (PDP), under different data activities and different data rates. Several HSPICE simulation results show that the proposed DETFF is superior in power reduction at different parameters as compared to the existing DETFFs. Hence, the proposed DETFF is well suited for low power applications.
A novel compact CPW tunable stop band filter using a new Z-DGS-resonator for ...TELKOMNIKA JOURNAL
The paper presents a novel very compact CPW bandstop filter. The designed structure consists of one unit of new Z-DGS resonator, placed on top layer of ground plane between the input and output this structure, which is excited by 50-ohm coplanar line. The designed filter can be used in X-Band applications as the band stop can be shifted to any other desired frequency by tuning the length of the Z-DGS. The proposed filter topology has as benefits good performances in terms of wide stop-band rejection, low insertion loss, high return loss, simple design and more small size (17.908×10 mm2) compared to other previous works those reported in literature. The stop-band width is from 3.96 GHz to 6.21 GHz, exhibits a 22.25-dB rejection bandwidth of 45% with high selectivity characteristic at the center frequency of 5.05 GHz.
Investigation of Integrated Rectangular SIW Filter and Rectangular Microstrip...IJASCSE
This paper presents an investigation based on the resonant circuit approach to characterize an integrated microwave filter and antenna from a lumped element prototype. This approach is used to design an integrated filter and antenna to reduce the overall size of the physical dimensions of the RF/microwave front-end subsystem. This study focuses on the integration of a rectangular Substrate Integrated Waveguide (SIW) filter with a rectangular microstrip patch antenna to produce a filtering and radiating element in a single device. The physical layouts of the SIW filter and rectangular microstrip patch antenna based on single- and dual-mode will be developed. To prove the concept, the integrated microwave filter and antenna at a center frequency of 2 GHz is demonstrated and validated through simulation and laboratory experiments. The experimental performance yielded promising results that were in good agreement with the simulated results. This study is beneficial for microwave systems, given that the reduction of the complexity of design and physical dimension as well as cost are important for applications such as base stations and multiplexers in wireless communication systems.
Performance analysis of beam divergence propagation through rainwater and sno...journalBEEI
In the present work the future communication requirements need to fulfill with high data rate, FSO (free space optic) with it is tremendous potential is the solution. This research observed the effectiveness analysis of FSO systems by modifying one of the most important FSO parameters beam divergence, under the most affected weather attenuating condition Rainwater and snow pack. The simulation is obtained and analyzed under single channels CSRZ-FSO (carrier-suppressed return-to-zero/free space optical) systems having capacity of 40 Gbps between two transceivers with variable distance. The connection is presently under 5 meteorological turbulences (light rain, medium rain, wet snow, heavy rain and dry snow). The results show the heavy rain and dry snow have a very high attenuation carried out in terms of Q-factor. this result led us to conclude that small divergence offers significant performance improvement for FSO link and this performance decrease every time the beam divergence increase, Therefore, to build inexpensive and reliable transmission media, we go with new method that still in the experiment area called hybrid RF/FSO (radio frequency/free space optical) that compatible with atmospherically status.
Substrate integrated waveguide bandpass filter for short range device applica...IJECEIAES
The substrate integrated waveguide (SIW) structure is the candidate for many application in microwave, terahertz and millimeter wave application. It because of SIW structure can integrate with any component in one substrate than others structure. A kind components using SIW structure is a filter component, especially bandpass filter. This research recommended SIW bandpass filter using rectangular open loop resonator for giving more selectivity of filter. It can be implemented for short range device (SRD) application in frequency region 2.4-2.483 GHz. Two types of SIW bandpass filter are proposed. First, SIW bandpass filter is proposed using six rectangular open loop resonators while the second SIW bandpass filter used eight rectangular open loop resonators. The simulation results for two kinds of the recommended rectangular open loop resonators have insertion loss (S 21 parameter) below 2 dB and return loss (S 11 parameter) more than 10 dB. Fabrication of the recommended two kind filters was validated by Vector Network Analyzer. The measurement results for six rectangular open loop resonators have 1.32 dB for S 21 parameter at 2.29 GHz while the S 11 parameter more than 18 dB at 2.26 GHz – 2.32 GHz. While the measurement results has good agreement for eight rectangular open loop resonators. It has S 21 below 2.2 dB at 2.41-2.47 GHz and S 11 16.27 dB at 2.38 GHz and 11.5 dB at 2.47 GHz.
3D FSS with multiple transmission zeros and pseudo elliptic responsejournalBEEI
The three-dimensional frequency selective surface (3D FSS) with band reject multiple transmission zeros and pseudo-elliptic response is designed from two-dimensional (2D) periodic array of shielded micro strip lines to realize wide out-of–band radio wave rejection. The 3D FSS array consists of multimode cavities whose coupling with air can be controlled to obtain a desired frequency range. The proposed FSS with shorting via to ground exhibits pseudo-elliptic band-reject response in the frequency range from 6GHz to 14GHz. As the plane wave of linear polarization incidents perpendicularly to the shielded micro strip line with perfect electric conductor (PEC) and perfect magnetic conductor (PMC) boundary walls, two quasi-TEM modes are obtained known as air mode and substrate mode. The first 3D FSS design is a combination of two or more resonators. Furthermore, second 3D FSS design with three shorting vias result more elliptic band reject frequency response and a pass band transmission pole. All in phase resonators of design give transmission poles and out of phase combination of resonators give transmission zeros respectively. The proposed 3D FSS is designed and simulated using Ansys HFSS software. These designs exhibit an improved performance for many practical applications such as antenna sub-reflector, and spatial filters.
DESIGN AND ANALYSIS OF COMPACT UWB BAND PASS FILTERijeljournal
This paper presents design, implementation and analysis of an ultra-wideband (UWB) band-pass-filter using parallel-coupled microstrip line with defective ground plane and a uniform multi-mode resonator. The structure of the filter is designed on microwave substrate GML 1000 of dielectric constant 3.2 and height is 0.762 mm. Simulation is carried out by CST MSW software and optimized structure is fabricated. The frequency response is measured on vector analyzer and measured results show close approximation with simulation results. In this article modeling of the proposed filter is also reported. The electric model of the filter is analyzed by circuit theory and MATLAB. This model is validated by comparing the results with the CST simulation and VNA measured results. This filter is compact in size of dimension 30˟1.87 mm2 may be useful for modern wireless application of communication.
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
This document summarizes a research paper that proposes a new low-power full adder cell design using carbon nanotube field-effect transistors (CNTFETs) in 32 nanometer technology. Simulation results show that the design, which uses 24 CNTFETs, reduces power consumption compared to previous CNTFET full adder designs. The power and power-delay product increase with supply voltage but are largely unaffected by temperature. Compared to previous designs, the proposed cell has lower power, delay, and power-delay product, especially at 0.65V supply voltage, demonstrating its improved energy efficiency.
Design of miniaturized patch crossover based on superformula slot shapesIJECEIAES
In this paper, miniaturized microstrip crossover circuits are proposed using slots shapes obtained using the superformula. The design starts by using a conventional half-wavelength square patch crossover. For miniaturization purposes, different superformula slot shapes are introduced on the square patch. The proposed crossovers are designed to operate at 2.4 GHz using a 0.8 mm thick FR-4 substrate with a relative permittivity of 4.4. The designs are simulated using the high frequency structure simulator (HFSS). One of the miniaturized designs is fabricated and its scattering parameters are measured using a vector network analyzer. Simulated and measured results agree very well. At the design frequency, the measured input port matching is better than ˗19 dB, while 𝑆12, 𝑆13 and 𝑆14 have the values of ˗12 dB, ˗2.2 dB and ˗10 dB, respectively. Furthermore, a 71% size reduction is achieved as compared to the conventional crossover area.
LOW POWER-AREA DESIGNS OF 1BIT FULL ADDER IN CADENCE VIRTUOSO PLATFORMVLSICS Design
The document describes several proposed low-power, area-efficient 1-bit full adder designs implemented using Cadence Virtuoso. It summarizes previous work on full adder designs and introduces three new proposed designs: a 12-transistor design that generates the carry using GDI technique and sum using a 3T XOR module; a 10-transistor design that generates the carry using a pass transistor logic multiplexer; and an 8-transistor design that generates the carry using pass transistors. The designs aim to reduce power consumption by utilizing tri-state inverters and pass transistor logic. Simulation results on a 180nm process show up to 93.1% power savings compared to a conventional 28-trans
MICROSTRIP COUPLED LINE FILTER DESIGN FOR ULTRA WIDEBAND APPLICATIONSjmicro
A compact microstrip parallel coupled line filter for ultra wide band applications by means of combining a network of coupled line and defected ground is proposed. The design equations for three and five interconnected networks are derived and implemented. Simulations for three different configurations for filters are optimized. Then three prototype circuits are constructed, a bandpass filter with center frequency 2.25 GHz and two different bandpass filters (in terms of perturbations) with center frequencies 2.33GHz.
For 2.25 GHz circuit wide fractional bandwidth of about 90% is obtained but undesired high return loss existed. For 2.33GHz circuit with grooves in sides fractional bandwidth of about 60% is obtained at about 3.4 GHz center frequency. However undesired return loss existed for this circuit whereas good out off or 2.33GHz circuit with grooves in whole sections the center frequency got shifted to about 3.4 GHz and about 50% fractional bandwidth is obtained with very good out off band performance observed.
This paper presents a new structure to implement compact narrowband high-rejection microstrip band-stop filter (BSF). This structure is the combination of two traditional BSFs: Spurline filter and BSF using defected ground structure (DGS). Due to inherently compact characteristics of both Spurline and interdigital capacitance (used as DGS), the proposed filter shows a better rejection performance than Spurline filter and open stub conventional BSF without increasing the circuit size. From, the proposed BSF has a rejection of better than 20dB and the maximum rejection level of 41dB.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORSVLSICS Design
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document summarizes research on novel photonic crystal fiber (PCF) structures with elliptical holes whose dimensions are derived from Dolph Tschebysheff polynomials. Three new PCF structures are proposed and their propagation characteristics are analyzed using simulations. The simulations show that the proposed structures exhibit negligible waveguide dispersion over a wide wavelength range, making them suitable for long distance communications. However, the birefringence of the structures is higher than PCF structures based on Pascal's triangle. The confinement losses of the proposed structures are also slightly higher. In conclusion, the PCF structures derived from Dolph Tschebysheff polynomials show potential for applications requiring low dispersion, but have increased birefringence and losses compared
Design and analysis of microstrip antenna with zig-zag feeder for wireless co...journalBEEI
This document describes the design and analysis of a microstrip antenna with a zig-zag feeder for wireless communication applications. The proposed antenna is designed to have a wide bandwidth of 2-14 GHz. It consists of a zig-zag microstrip feedline connected to a tuning stub printed on one side of a substrate. On the other side of the substrate is a ground plane with zig-zag slots. Parametric analysis was performed to optimize the dimensions for wide bandwidth and acceptable gain between 7.448-5.928 dB. The zig-zag feedline and tuning stub with elliptical slots help improve the impedance matching for wide bandwidth operation suitable for UWB applications. Simulation results for radiation patterns, current distribution, and
This document describes the design and simulation of an ultra-wideband balanced bandpass filter. Key points:
1) The filter uses defected ground structures (DGS) to provide common mode rejection. It has three sections - a pair of UWB filtering units for the differential lines, U-shaped and H-shaped DGSs for lower band suppression, and dumbbell-shaped DGSs for upper band suppression.
2) An equivalent lumped element model is developed and parameters are extracted to represent the common mode response of each section.
3) Simulation results show the filter provides good differential mode propagation and common mode suppression from DC to 18GHz, meeting the requirements for modern communication systems
Compact Stepped Impedance Resonator Bandpass Filter with Tunable Transmission...TELKOMNIKA JOURNAL
This paper proposes a compact microstrip bandpass filter (BPF) with tunable transmission zero,
narrow bandwidth and low insertion loss. Transmission zeros are the key to improve the band rejection
and filter frequency selectivity. A λ/4 stepped impedance resonator (SIR) with two additional via holes has
been adopted to obtain a compact size and a pair of transmission zero (TZ). The BPF is designed to
operate at 3.5 GHz with fractional bandwidth (FBW) of 7.2%.Furthermore, three techniques have been
developed to create a pair of controllable transmission zeros on both side of each passband. The TZ can
be controlled by adjusting either magnetic or electric coupling. The measured return losses and insertion
lossis larger than 18 dB and 2.2 dB respectively. The overall size of the proposed design filter is 5.3mm x
5.5mm without considering the feeding lines.
In this paper, UWB technology operating in broad
frequency range of 3.1-10.6 GHz has shown great achievement
for high- speed wireless communications. to satisfy the UWB
system requirements, a band pass filter with a broad pass
band width, low insertion loss, and high stop-band suppression.
UWB band-pass filter (BPF) with wireless local area network
(WLAN) notch at 5.8 GHz and 3-dB fractional bandwidth of
108% using a microstrip structure is presented. Initially a
two transmission pole UWB band pass filter in the frequency
range 3.1-10.6 GHz is achieved by design a parallel-coupled
microstrip line with defective ground plane structure using
GML 1000 substrate with specification: dielectric constant 3.2
and thickness 0.762 mm at centre frequency 6.85 GHz. In this
structure a ë/4 open circuited stub is introduced to achieve the
notch at 5.8 GHz to avoid the interference with WLAN
frequency with lies the desired UWB band. The design
structure was simulated on electromagnetic circuit simulation
software and fabricated by microwave integrated circuit
technique. The measured VNA results show the close
agreement with simulated results.
A new look on CSI imperfection in downlink NOMA systemsjournalBEEI
- The document analyzes the performance of downlink non-orthogonal multiple access (NOMA) systems under imperfect channel state information (CSI) and Nakagami-m fading.
- It derives closed-form expressions for the outage probability of two users in such NOMA systems considering the joint impact of imperfect CSI and Nakagami-m fading.
- Monte Carlo simulations are conducted to verify the accuracy of the analytical outage probability expressions derived for the two users under the system and channel models considered.
This document describes a proposed new dual edge-triggered D-type flip-flop circuit design with low power consumption. The design achieves dual edge-triggering using two parallel data paths that operate on opposite clock phases. It uses a latch circuit structure with differential input data signals, which reduces capacitance on the clock line. Simulation results show the proposed design has lower power consumption than several existing dual edge-triggered flip-flop designs under different operating conditions, making it well-suited for low-power applications.
DUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTIONijcsit
In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design achieves dual edge-triggered with two parallel data paths work in opposite phases of the clock single. Among them, a latch circuit structure employs differential input data signals which deposits very little capacitance on the clock line is accomplished. For fair comparison, four previously reported DET flipflops along with the proposed DETFF (DET flip-flop) are compared in terms of power consumption and power-delay product (PDP), under different data activities and different data rates. Several HSPICE simulation results show that the proposed DETFF is superior in power reduction at different parameters as compared to the existing DETFFs. Hence, the proposed DETFF is well suited for low power applications.
A novel compact CPW tunable stop band filter using a new Z-DGS-resonator for ...TELKOMNIKA JOURNAL
The paper presents a novel very compact CPW bandstop filter. The designed structure consists of one unit of new Z-DGS resonator, placed on top layer of ground plane between the input and output this structure, which is excited by 50-ohm coplanar line. The designed filter can be used in X-Band applications as the band stop can be shifted to any other desired frequency by tuning the length of the Z-DGS. The proposed filter topology has as benefits good performances in terms of wide stop-band rejection, low insertion loss, high return loss, simple design and more small size (17.908×10 mm2) compared to other previous works those reported in literature. The stop-band width is from 3.96 GHz to 6.21 GHz, exhibits a 22.25-dB rejection bandwidth of 45% with high selectivity characteristic at the center frequency of 5.05 GHz.
Investigation of Integrated Rectangular SIW Filter and Rectangular Microstrip...IJASCSE
This paper presents an investigation based on the resonant circuit approach to characterize an integrated microwave filter and antenna from a lumped element prototype. This approach is used to design an integrated filter and antenna to reduce the overall size of the physical dimensions of the RF/microwave front-end subsystem. This study focuses on the integration of a rectangular Substrate Integrated Waveguide (SIW) filter with a rectangular microstrip patch antenna to produce a filtering and radiating element in a single device. The physical layouts of the SIW filter and rectangular microstrip patch antenna based on single- and dual-mode will be developed. To prove the concept, the integrated microwave filter and antenna at a center frequency of 2 GHz is demonstrated and validated through simulation and laboratory experiments. The experimental performance yielded promising results that were in good agreement with the simulated results. This study is beneficial for microwave systems, given that the reduction of the complexity of design and physical dimension as well as cost are important for applications such as base stations and multiplexers in wireless communication systems.
Performance analysis of beam divergence propagation through rainwater and sno...journalBEEI
In the present work the future communication requirements need to fulfill with high data rate, FSO (free space optic) with it is tremendous potential is the solution. This research observed the effectiveness analysis of FSO systems by modifying one of the most important FSO parameters beam divergence, under the most affected weather attenuating condition Rainwater and snow pack. The simulation is obtained and analyzed under single channels CSRZ-FSO (carrier-suppressed return-to-zero/free space optical) systems having capacity of 40 Gbps between two transceivers with variable distance. The connection is presently under 5 meteorological turbulences (light rain, medium rain, wet snow, heavy rain and dry snow). The results show the heavy rain and dry snow have a very high attenuation carried out in terms of Q-factor. this result led us to conclude that small divergence offers significant performance improvement for FSO link and this performance decrease every time the beam divergence increase, Therefore, to build inexpensive and reliable transmission media, we go with new method that still in the experiment area called hybrid RF/FSO (radio frequency/free space optical) that compatible with atmospherically status.
Substrate integrated waveguide bandpass filter for short range device applica...IJECEIAES
The substrate integrated waveguide (SIW) structure is the candidate for many application in microwave, terahertz and millimeter wave application. It because of SIW structure can integrate with any component in one substrate than others structure. A kind components using SIW structure is a filter component, especially bandpass filter. This research recommended SIW bandpass filter using rectangular open loop resonator for giving more selectivity of filter. It can be implemented for short range device (SRD) application in frequency region 2.4-2.483 GHz. Two types of SIW bandpass filter are proposed. First, SIW bandpass filter is proposed using six rectangular open loop resonators while the second SIW bandpass filter used eight rectangular open loop resonators. The simulation results for two kinds of the recommended rectangular open loop resonators have insertion loss (S 21 parameter) below 2 dB and return loss (S 11 parameter) more than 10 dB. Fabrication of the recommended two kind filters was validated by Vector Network Analyzer. The measurement results for six rectangular open loop resonators have 1.32 dB for S 21 parameter at 2.29 GHz while the S 11 parameter more than 18 dB at 2.26 GHz – 2.32 GHz. While the measurement results has good agreement for eight rectangular open loop resonators. It has S 21 below 2.2 dB at 2.41-2.47 GHz and S 11 16.27 dB at 2.38 GHz and 11.5 dB at 2.47 GHz.
3D FSS with multiple transmission zeros and pseudo elliptic responsejournalBEEI
The three-dimensional frequency selective surface (3D FSS) with band reject multiple transmission zeros and pseudo-elliptic response is designed from two-dimensional (2D) periodic array of shielded micro strip lines to realize wide out-of–band radio wave rejection. The 3D FSS array consists of multimode cavities whose coupling with air can be controlled to obtain a desired frequency range. The proposed FSS with shorting via to ground exhibits pseudo-elliptic band-reject response in the frequency range from 6GHz to 14GHz. As the plane wave of linear polarization incidents perpendicularly to the shielded micro strip line with perfect electric conductor (PEC) and perfect magnetic conductor (PMC) boundary walls, two quasi-TEM modes are obtained known as air mode and substrate mode. The first 3D FSS design is a combination of two or more resonators. Furthermore, second 3D FSS design with three shorting vias result more elliptic band reject frequency response and a pass band transmission pole. All in phase resonators of design give transmission poles and out of phase combination of resonators give transmission zeros respectively. The proposed 3D FSS is designed and simulated using Ansys HFSS software. These designs exhibit an improved performance for many practical applications such as antenna sub-reflector, and spatial filters.
DESIGN AND ANALYSIS OF COMPACT UWB BAND PASS FILTERijeljournal
This paper presents design, implementation and analysis of an ultra-wideband (UWB) band-pass-filter using parallel-coupled microstrip line with defective ground plane and a uniform multi-mode resonator. The structure of the filter is designed on microwave substrate GML 1000 of dielectric constant 3.2 and height is 0.762 mm. Simulation is carried out by CST MSW software and optimized structure is fabricated. The frequency response is measured on vector analyzer and measured results show close approximation with simulation results. In this article modeling of the proposed filter is also reported. The electric model of the filter is analyzed by circuit theory and MATLAB. This model is validated by comparing the results with the CST simulation and VNA measured results. This filter is compact in size of dimension 30˟1.87 mm2 may be useful for modern wireless application of communication.
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
This document summarizes a research paper that proposes a new low-power full adder cell design using carbon nanotube field-effect transistors (CNTFETs) in 32 nanometer technology. Simulation results show that the design, which uses 24 CNTFETs, reduces power consumption compared to previous CNTFET full adder designs. The power and power-delay product increase with supply voltage but are largely unaffected by temperature. Compared to previous designs, the proposed cell has lower power, delay, and power-delay product, especially at 0.65V supply voltage, demonstrating its improved energy efficiency.
Design of miniaturized patch crossover based on superformula slot shapesIJECEIAES
In this paper, miniaturized microstrip crossover circuits are proposed using slots shapes obtained using the superformula. The design starts by using a conventional half-wavelength square patch crossover. For miniaturization purposes, different superformula slot shapes are introduced on the square patch. The proposed crossovers are designed to operate at 2.4 GHz using a 0.8 mm thick FR-4 substrate with a relative permittivity of 4.4. The designs are simulated using the high frequency structure simulator (HFSS). One of the miniaturized designs is fabricated and its scattering parameters are measured using a vector network analyzer. Simulated and measured results agree very well. At the design frequency, the measured input port matching is better than ˗19 dB, while 𝑆12, 𝑆13 and 𝑆14 have the values of ˗12 dB, ˗2.2 dB and ˗10 dB, respectively. Furthermore, a 71% size reduction is achieved as compared to the conventional crossover area.
LOW POWER-AREA DESIGNS OF 1BIT FULL ADDER IN CADENCE VIRTUOSO PLATFORMVLSICS Design
The document describes several proposed low-power, area-efficient 1-bit full adder designs implemented using Cadence Virtuoso. It summarizes previous work on full adder designs and introduces three new proposed designs: a 12-transistor design that generates the carry using GDI technique and sum using a 3T XOR module; a 10-transistor design that generates the carry using a pass transistor logic multiplexer; and an 8-transistor design that generates the carry using pass transistors. The designs aim to reduce power consumption by utilizing tri-state inverters and pass transistor logic. Simulation results on a 180nm process show up to 93.1% power savings compared to a conventional 28-trans
MICROSTRIP COUPLED LINE FILTER DESIGN FOR ULTRA WIDEBAND APPLICATIONSjmicro
A compact microstrip parallel coupled line filter for ultra wide band applications by means of combining a network of coupled line and defected ground is proposed. The design equations for three and five interconnected networks are derived and implemented. Simulations for three different configurations for filters are optimized. Then three prototype circuits are constructed, a bandpass filter with center frequency 2.25 GHz and two different bandpass filters (in terms of perturbations) with center frequencies 2.33GHz.
For 2.25 GHz circuit wide fractional bandwidth of about 90% is obtained but undesired high return loss existed. For 2.33GHz circuit with grooves in sides fractional bandwidth of about 60% is obtained at about 3.4 GHz center frequency. However undesired return loss existed for this circuit whereas good out off or 2.33GHz circuit with grooves in whole sections the center frequency got shifted to about 3.4 GHz and about 50% fractional bandwidth is obtained with very good out off band performance observed.
This paper proposes a novel planar three-way power divider circuit that addresses limitations of existing Wilkinson power divider designs. The proposed circuit has a planar structure compared to the 3D Wilkinson design, reducing complexity. It also has improved RF performance in return loss, insertion loss, and isolation. The circuit dimensions are reduced, improving integration for printed circuit boards and MMICs. Simulation results show the design meets specifications for return loss, insertion loss, and isolation at its operating frequency of 2.4GHz.
Simulation Tool: AWR Microwave Office
•This project is an implementation of an IEEE paper "Design of Dual Band Cross-Coupled Branch Line Coupler" by Myun-joo Park and Byungje Lee.
• Designed and simulated Dual Band Cross-Coupled Branch Line Coupler for the operating frequency of 1.5Ghz and 3Ghz.
•The cross coupling in the branches introduce more design freedom.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
Non-radiative wireless energy transfer with single layer dual-band printed sp...journalBEEI
Accomplishing equilibrium in terms of transfer efficiency for dual-band wireless energy transfer (WET) system remains as one of key concerns particularly in the implementation of a single transmitter device which supports simultaneous energy and data transfer functionality. Three stages of design method are discussed in addressing the aforementioned concern. A single layer dual-band printed spiral resonator for non-radiative wireless energy transfer operating at 6.78 MHz and 13.56 MHz is presented. By employing multi-coil approach, measured power transfer efficiency for a symmetrical link separated at axial distance of 30 mm are 72.34% and 74.02% at the respective frequency bands. When operating distance is varied between 30 mm to 38 mm, consistency of simulated peak transfer efficiency above 50% is achievable.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document analyzes the energy dissipation of digital half band filters operated in the sub-threshold region with throughput constraints. It explores various architectures of a 12-bit half band filter including the basic implementation and unfolded structures. Simulation results show that the unfolded by 2 architecture dissipates 22% less energy per sample compared to the original filter, making it the most energy efficient. The unfolded by 4 architecture best meets throughput requirements of 120K-1M samples/sec, dissipating less energy than other implementations in this speed range.
This document summarizes an IC chip called RTB that functions as a full-duplex transceiver for wideband digital systems. The chip contains four independent transceivers that can transmit and receive data through the same transmission line. It uses feedback to subtract the transmitted signal from the combined transmitted and received signal on the line in order to recover the received data. Simulation and testing showed the chip could reliably transmit and receive signals at data rates up to 100 Mbps over transmission lines up to several tens of meters.
DESIGNING HIGH-SPEED, LOW-POWER FULL ADDER CELLS BASED ON CARBON NANOTUBE TEC...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
This document summarizes a research paper that designed, modeled, and characterized an integrated cascode cell for compact Ku-band power amplifiers.
The integrated cascode cell was designed to decrease the size of individual power cells while maintaining performance. It combines two transistors in a cascode configuration, effectively doubling the output power and gain compared to a single transistor. Modeling of the cell was performed using a distributed approach.
Measurements showed good agreement with the model. Using the new integrated cascode cells, the researcher was able to design a 2W Ku-band power amplifier MMIC that occupied 40% less area than previous designs using single transistors, demonstrating the effectiveness of the integrated cascode cell topology.
Wideband frequency reconfigurable metamaterial antenna design with double H s...journalBEEI
This paper presents the design of wideband frequency reconfigurable metamaterial antenna with double H slots. The design is based on the idea of composite right/left-handed transmission line (CRLH-TL) technique. Bandwidth enhancement was achieved by utilizing series left-handed capacitor CL transmission line parameter. The design has several outstanding advantages which include efficient bandwidth to cover many lower Application bands with multi frequency operation characteristics. A comprehensive analysis and simulation were done by using computer simulation technology (CST) software to determine the performance and efficiency of the proposed antenna. From the result obtained, the antenna aquired bandwidth range which covered (2.3-5.2) GHz which is equivalent to 77% fractional bandwidth. The wideband antenna was reconfigured by using frequency reconfiguration technique. From the reconfiguration results, the antenna can be switch from wideband to two single bands which resonate at 2.4 GHz and 4.2 GHz and to dual band which resonate at 2.4 GHz and 4.2 GHz. The realized peak gain at 2.4 GHz is 2.28 dBi and 2.58 dBi for E and H field respectively. The maximum efficiency of 96% was obtained. The antenna can be use for WLAN, proposed lower 5G band and cognitive radio system for frequency sencing.
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
A new hybrid method for mutual coupling minimization of an antenna array IJECEIAES
In this paper, a simultaneous application of geometric modification on patch elements and electromagnetic band gap (EBG) electromagnetic bandgap structures (hybrid method) has been suggested for 3.5 GHz wireless communication applications, to minimize the mutual coupling between radiating elements of microstrip array antennas. The suggested EBG slotted structure is composed of a one square ring and three squares placed on Rogers RO3010 having 10.2 and h=1.27 mm which presents respectively its dielectric constant and thickness. In this approach, the patch elements are geometrically modified, while also employing EBG structures, formed by four EBG cells, placed between the array elements at a near distance. The modification of the geometry of the antenna and the introduction of EBG reduces the mutual coupling of an array antenna with approximately 33 dB on the one hand and improves the antenna gain by approximately 0.43 dB on the other hand. Initially, slots are introduced in the patch geometry and then four EBG unit cells are inserted between two patches, operating at 3.5 GHz. The antenna array design parameters were optimized.
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MINIATURIZATION OF BRANCH-LINE COUPLERS USING OPEN STUBS AND STEPPED IMPEDANCE UNIT CELLS WITH MEANDERING TRANSMISSION LINES
1. Circuits and Systems: An International Journal (CSIJ), Vol. 1, No.3, July 2014
13
MINIATURIZATION OF BRANCH-LINE COUPLERS
USING OPEN STUBS AND STEPPED IMPEDANCE
UNIT CELLS WITH MEANDERING TRANSMISSION
LINES
Siddig Gomha1
, EL-Sayed M. El-Rabaie1
, Abdel Aziz T. Shalaby1
, and Ahmed S.
Elkorany1
1
Department of Electronics and Electrical Communications Engineering, Faculty of
Electronic Engineering, Menouf, 32952, Egypt.
ABSTRACT
In this paper, two proposed structures of the compact Branch-Line Couplers BLCs are designed and
simulated. Three different technologies of miniaturization BLC are used together, open ended stubs,
meandering transmission lines, and stepped impedance. The results of the two designed BLC are compared
to previously published results work at the same frequency 1.8GHz, the two proposed structures are
designed and simulated using CST full wave simulator. The first and second structures are occupied only
61.8% and 50.8%, respectively, from the area of the conventional design. The paper presents a
comparative study between simulated results of the two proposed designs and the measured results, the
results show good agreement especially in the stepped impedance BLC.
KEYWORDS
Branch-Line Couplers BLCs, open ended stubs, meandering transmission lines, stepped impedance.
1.INTRODUCTION
Branch-line coupler is a passive microwave device used in the many communication systems,
such as power dividers, power combiners, balance amplifiers, and balance mixtures. BLC is
also known as a 3dB quadrature hybrid coupler. It has two main transmission lines with
characteristic impedance ܼ √2⁄ , and two shunt transmission lines with characteristic
impedance ܼ, As shown in Figure. 1, the area of the device is ߣ 4⁄ × ߣ 4⁄ , which occupies
large space in the low frequency range [1, 2], hence the size reduction of the BLC becomes an
important issue. The dimension of the device depends mainly on the operating frequency, so
that at low frequencies the size of the BLC becomes very large, and not suitable to fabricate by
PCB planner micro strip technology. There are many techniques have been used to solve the
size problem for the conventional BLC, the most popular techniques are using stepped
impedance [3] – [5], using stubs on the transmission line [6] – [9], meandering transmission
line [10] and using lumped components in conjunction with high-impedance transmission lines
[11, 12].
2. Circuits and Systems: An International Journal (CSIJ), Vol. 1, No.3, July 2014
14
In this paper, we focus on the miniaturization of BLC, with maintaining the performance of
the device. The strategy is based on design one unit cell of the open ended stub which is
extensively presented in [9], the first proposed structure of the compact BLC based on using
open stubs and meandering transmission lines, and the second one is based on using open
stubs and stepped impedance unit cells. The two proposed structures of the BLC are designed
and simulated using CST full wave EM simulator [13]. The optimum structure design is
compared to the previously published measured result [8]. The comparison shows very good
agreement between both results. All of the proposed BLCs are designed to operate at 1.8GHz,
which is suitable for GSM 1800 application.
The paper is organized as follows: section II discusses the size reduction of the BLC using
open ended stubs, Section III design, compact BLC using open ended stub unit cells and
meandering TL, Section IV design, compact BLC using stepped impedance unit cells and
meandering TL, followed by the conclusion and relevant references.
Figure 1. Conventional branch-line coupler.
2. MINIMIZE THE CIRCUIT AREA OF THE BLC USING OPEN ENDED STUB
UNIT CELLS
Many studies have been presented to reduce the size of the BLC, can be classified into two main
categories: classical and new techniques. In this paper, we will discuss some of the classical
techniques, and the new techniques based on the advanced materials (e.g. metamaterials, HTS,
and ferroelectric) are not covering here. In the classical methods, the size reduction can be done
using lumped components in conjunction with high-impedance transmission lines, meandering
transmission lines of the structure, using stepped impedance ,and using both short and open
ended stubs to represent distributed inductors and capacitors.
The open ended stubs are positioned on the conventional transmission line TL to make load
capacitance which is lead to the small size of the modified TL, the derivation of the design
equations are presented in [9], Figure. 2 (a), shows one unit cell of the design, l, W,
represent the length and the width of the unit cell, respectively, lୗ୲୳ୠ , ܹௌ௧௨ represent the length
and the width of the open stub unit cell, respectively. Fig.2 (b) depicts the Branch-line coupler
with open ended stubs. Table 1, shows the design specification of the one unit cell of the open
ended stubs BLC.
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Table 1, design specifications of the open ended stubs BLC.
Zୗ = 35 Ω Zୗ = 50 Ω
N 5 5
w (mm) 1.9 1.3
l (mm) 3.6 4.2
wୱ୲୳ୠ ( mm) 1.8 2
lୱ୲୳ୠ (mm) 6.7 3.7
Figure 2. (a) One unit cell (b) Branch-line coupler with open ended stubs.
The dimension of a conventional BLC occupy large area, according to the length of the TL which
is always ߣ 4⁄ of the operating frequency, ߣ is so long at low frequencies rang. When we use open
ended stubs the dimension of the new BLC is reduced compared to the conventional design at the
same dielectric substrate (ߝ = 2.2) and thickness (h = 0.7874 mm) to works at frequency 1.8
GHz. Figure 3, shows comparison between two designs, red line for conventional design and
black lines for open ended stubs design with different number of stubs (N) from (1 - 10), as
shown in this figure, at frequency range (1-2 GHz) there are a good size reduction in the design
area of the open ended stubs BLC, at the operating frequency 1.8 GHz the design area is reduced
from 11 ܿ݉ଶ
(conventional BLC) to 7.17 ܿ݉ଶ
(open stubs BLC) [9].
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Figure 3. Comparison between the design area ܿ݉ଶ
of the open ended stubs and conventional BLC.
The performance of the two designs are presented in the Figure 4, and summarized in Table 2,
which is shows open stubs BLC with different number of stubs (e.g. 2,5, and 8). When the
number of stubs N=5 (grey shadow column),the open ended stubs BLC gives an optimum
performance, the return loss (ܵଵଵ) and isolation (ܵଵସ) is about -35dB and -37dB respectively, and
ܵଵଶ=ܵଵଷ= -3 dB, that means the signal output is divided equally through the two output ports,
However, this performance is stable only in the narrow bandwidth, about (130 MHz),and the
design area of the structure is reduced from 11 ܿ݉ଶ
to 7.17ܿ݉ଶ
.
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Figure 4. Magnitudes of the scattering parameters for the conventional BLC (a), and open stubs BLC (b).
Table 2, Comparison the performance of the open ended stubs (in case of N=2, 5, and8) , and conventional
BLC.
Open Ended Stubs Design Conventional Design
N 2 5 8 0
݂ GHz 1.75 1.77 1.77 1.8
(S11) dB @ ݂ -21.8 -35.9 -28.9 -52
(S14) dB @ ݂ -22.9 -37.9 -30 -52
(S12) dB @ ݂ -2.8 -3.1 -2.9 -3
(S13) dB @ ݂ -3.5 -3 -3.2 -3
BW MHz @ -15dB 280 130 314 320
BW % 15.5 % 7.2% 17.4% 17.7%
Design Area ( ܿ݉ଶ
) 7.3 7.17 6.5 11
(a)
(b)
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3. SIZE REDUCTION OF THE BLC USING OPEN ENDED STUBS AND
MEANDERING TRANSMISSION LINES
In the previous structure of the BLC, open ended stubs are placed on the both (main, and
shunted) transmission lines, and in this structure that shown in Figure. 5, the open ended stubs
are placed only on the main transmission line, but the shunt transmission line was meandered
inside the free space of the BLC to achieve more small size. The design parameters of the
structure are explained in Table 3.
Figure 5. Branch-line coupler with open stubs unit cells and meandering transmission line
Table 3, Design specifications of the proposed structure BLC based on open ended stubs unit cell, and
meandering lines (ߝ = 2.2 , h=0.7874 mm).
Main TL (open stub unit cells), Z = 35
Ω
Shunt TL (meander lines), Z = 50 Ω
N 5 TL width 2.4 mm
w 1.9 mm TL length 31 mm
l 3.7 mm
wୱ୲୳ୠ 1.3 mm
lୱ୲୳ୠ 9 mm
The proposed BLC Figure. 5, is designed and simulated by CST, the design is compared to the
previous published work [8], and conventional BLC designed on the same substrate (ߝ = 2.2,
h=0. 7874 mm), and frequency work 1.8GHz. Figure. 6, shows the scattering parameters of the
three structures, Table 4, shows comparative study between the performances of the three
different designs. The proposed BLC shows very good size reduction compared to the
conventional design, also the bandwidth of the proposed BLC is up to 312 MHz, where the
bandwidth of the previous published BLC [8] is up to 300 MHz, and the conventional design is
up to 338 MHz.
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Figure 6. Comparison between S-parameters, magnitude of the proposed design (simulated by CST),
conventional design (simulated by CST), and measured results [8], (a) for the magnitudes of (Sଵଵ, Sଵଶ), and
(b) for the magnitudes of (Sଵଷ, Sଵସ).
(a)
(b)
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Table 4, Performance comparison for the three BLC types, proposed BLC based on open stubs and
meandering TL, measured results [8], and conventional BLC.
Parameters
Proposed
Design
Measured results
[8]
Conventional BLC
Center Freq.(GHz) 1.8 1.75 1.8
(Sଵଵ) dB @ ݂ -27.8 -31 -38
(Sଵସ) dB @ ݂ -27.9 -31.9 -38
(Sଵଶ) dB @ ݂ -3 -3.1 -2.9
(Sଵଷ) dB @ ݂ -3 -3 -3.1
Bandwidth (MHz) 312 300 338
Percentage (%) of
Bandwidth
@ Sଵଵ = −15݀ܤ
17.8% 16.7% 18.9%
Design Area ܿ݉ଶ
7.6 ܿ݉ଶ
6.87 ܿ݉ଶ
12.3 ܿ݉ଶ
4. SIZE REDUCTION OF THE BLC USING STEPPED IMPEDANCE AND
MEANDERING TRANSMISSION LINES
Open ended stub unit cells sometimes take place inside and outside of the BLC circuit area, as
shown in Figure 5, and occupies large space, for this reason the open ended stub unit cells have
been transformed into the stepped impedance unit cells, which will be suitable and take less space
than the open ended stub unit cells. Figure. 7 (a), shows one unit cell of the open ended stub,
where, ߠଵ, and ܼଵ represent the electrical length and characteristic impedance, respectively, of
the open ended stub unit cell. Figure. 7 (b), shows one unit cell of the stepped impedance, where,
ߠଵଵ, and ܼଵଵ represent the electrical length and characteristic impedance, respectively, for the
lower section of the stepped impedance unit cell, ߠଵଶ, and ܼଵଶ represent the electrical length
and characteristic impedance, respectively, for the upper section of the stepped impedance unit
cell.
Figure 7. (a) One unit cell of the open stub (b) One unit cell of the stepped impedance.
The input impedance of the Figure 7. (a), is given by [2]:
ܼ_ = − ݆
బభ
୲ୟ୬(ఏబభሻ
(1)
And the input impedance of the Figure 7. (b) is given by:
9. Circuits and Systems: An International Journal (CSIJ), Vol. 1, No.3, July 2014
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ܼ_ = − ݆ܼଵଵ
బభమି బభభ ୲ୟ୬(ఏబభభሻ ୲ୟ୬(ఏబభమሻ
బభభ ୲ୟ୬(ఏబభమሻାబభమ ୲ୟ୬(ఏబభభሻ
(2)
When we apply the equality between equation (1) and (2) we get:
ߠଵଶ = ݊ܽݐିଵ
ቂ
୲ୟ୬(ఏబభሻି ெ ௧(ఏబభభሻ
ெା ௧(ఏబభభሻ௧(ఏబభሻ
ቃ (3)
Where,ܭ = ܼଵଶ ܼଵଵ⁄ , and ܯ = ܼଵ ܼଵଵ⁄ , Figure. 8, shows the relationship between the total
length of the stepped impedance (θଵଵ+ θଵଶ) in (mm) and (ܯ = ܼଵ ܼଵଵ⁄ ), with different
values of (ܭ = ܼଵଶ ܼଵଵ⁄ ), from equation (3) we can calculate the value of (ߠଵଶ), however,
only two parameters are given from open stub unit cell (ߠଵ ܽ݊݀ ܼଵ), the optimum values of the
un known parameters can be selected from the plots shown in (Fig. 8, 9, and 10),the total length
of the stepped impedance is inversely proportional to the value of (K), to get small length of the
stepped impedance we must chose small values of (K) and (M).
Figure 8. Relation between total length of the stepped impedance (ߠଵଵ+ ߠଵଶ) in (mm) and (M) with
different values of (K).
Figure. 9, depicts the relationship between the upper (θଵଶ), and the lower (θଵଵ) section of the
stepped impedance unit cell with different values of (K), the electrical length (θଵଶ) is changes
slightly with electrical length (θଵଵ), especially when the value of (K) is small, and the electrical
length of the lower section (θଵଵ) of the stepped impedance must be taken precisely, to avoid
coupling between the upper section (θଵଶ) of the stepped impedance unit cells and the main
transmission line, also we can take equal lengths for the lower and upper sections, as in our
design case is (e.g. θଵଵ = θଵଶ = 2.3 mm).
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Figure 9. Relation between upper (ߠଵଶ) and lower (ߠଵଵ) sections of the stepped impedance unit cell, with
different values of (K).
Figure 10, shows the relationship between (ܼଵଵ, andܼଵଶ), with different values of (M), the
characteristic impedance of the lower section (ܼଵଵ) must be very high impedance than the upper
section (ܼଵଶ), also we observe that, the upper section (ܼଵଶ) characteristic impedance increases
with increasing the lower section (ܼଵଵ) characteristic impedance.
Figure 10. Relation between the characteristic impedance of the upper (ܼଵଶ) and lower (ܼଵଵ) sections of
the stepped impedance unit cell, with different values of (M).
According to the above consideration, a new proposed BLC composed of stepped impedance
unit cells and meandering TL is designed, as shown in Figure. 11, the stepped impedance unit
cells are used instead of conventional TL with impedance Z = 35 Ω, while the other TL is
meandered inside the free space of the BLC, Table5, shows the design specification.
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Figure 11. Branch-line coupler with stepped impedance unit cells and meandering transmission lines.
Table 5, Design specifications of the proposed structure BLC based on stepped impedance unit
cell, and meandering lines (ߝ = 2.2 , h=0.7874 mm).
Main TL (stepped impedance unit
cells),
Z = 35 Ω
Shunt TL (meander lines), Z = 50 Ω
Upper side section length
ߠଵଶ
2.3 mm TL width 2.4 mm
Upper side section width
ܹଵଶ
9 mm TL length 31 mm
Lower side section length
ߠଵଵ
2.3 mm
Lower side section width
ܹଵଵ
1 mm
The proposed BLC shows in Figure. 11, is based on stepped impedance and meandering TL, the
structure is designed and simulated by CST, the proposed design is compared to the previous
published results [8], and conventional BLC; designed on the same substrate (ߝ = 2.2, h=0.
7874 mm), and frequency work 1.8GHz, as shown in Figure. 12, the scattering parameters of the
three structures show good agreement, Table 6, shows comparative study between the
performances of the three designs, the return loss (ܵଵଵ) and isolation (ܵଵସ) of the proposed BLC is
about -26.7 dB and -26.1 dB respectively, and ܵଵଶ=ܵଵଷ= -3 dB, that means the signal output is
divided equally through the two output ports, also the proposed BLC shows the smallest design
area compared to the conventional design and the previous published BLC [8], and the
bandwidth of the proposed BLC is about 275 MHz.
ߠଵଶ
ܹଵଶ
ߠଵଵ
ܹଵଵ
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Figure 12.Comparison between S-parameters, magnitude of the proposed design (simulated by CST),
conventional design (simulated by CST), and measured results [8], (a) for the magnitudes of (ܵଵଵ&ܵଵଶ) and
(b) for the magnitudes of (ܵଵଷ&ܵଵସ).
(a)
(b)
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Table 6, Performance comparison of the three BLC types, proposed BLC based on stepped impedance and
meandering TL, measured results [8], and conventional BLC.
Parameters
Proposed
Design
Measured results
[20]
Conventional BLC
Center Freq.(GHz) 1.8 1.75 1.8
(Sଵଵ) dB @ ݂ -26.7 -31 -38
(Sଵସ) dB @ ݂ -26.1 -31.9 -38
(Sଵଶ) dB @ ݂ -2.9 -3.1 -2.9
(Sଵଷ) dB @ ݂ -3 -3 -3.1
Bandwidth (MHz) 275 300 338
Percentage (%) of
Bandwidth
@ Sଵଵ = −15݀ܤ
15.3% 16.7% 18.9%
Design Area ܿ݉ଶ 6.25
ܿ݉ଶ 6.87 ܿ݉ଶ
12.3 ܿ݉ଶ
5. CONCLUSIONS
Miniaturization of the branch-line coupler BLC have been studied, two new compact structures of
the BLC were designed and simulated, the performance of the two designs show good agreement
when compared to the previously published results and conventional BLC on the same substrate.
In the first structure, open ended stub unit cells with meandered TL have been used to design
compact BLC, the proposed design shows good size reduction when compared to the
conventional design, and occupies only 61.8% area of the conventional design, also the
bandwidth of the proposed BLC is up to 312 MHz, where the bandwidth of the previous
published BLC [8] is up to 300 MHz, and the conventional design is up to 338 MHz.
In the second structure, stepped impedance unit cells with meandered TL have been used to
design compact BLC, the proposed design shows the smaller design area when compared to the
conventional design, and occupies only 50.8% area of the conventional design, but the bandwidth
of the proposed BLC is decreased to 275 MHz.
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