Microprocessors-based systems (under graduate course) Lecture 8 of 9 Randa Elanwar
This document provides an overview of the 8086/8088 instruction set as presented in a lecture by Dr. Randa Elanwar. It discusses machine control and flag manipulation instructions, string manipulation instructions, loop instructions, input/output ports and interfacing instructions. Specific instructions are explained, such as MOVS, CMPS, SCAS, LODS, STOS, IN, and OUT. Examples are provided to illustrate how to move a byte string, find a byte in a string, and continuously check the status of external ports using interrupts. The document aims to explain the various instruction types and their applications in microprocessor-based systems.
Microprocessors-based systems (under graduate course) Lecture 5 of 9 Randa Elanwar
The document discusses RISC and CISC architectures, memory segmentation, address decoding, and instruction codes. It provides details on:
- RISC vs CISC characteristics including number of instructions, addressing modes, and instruction formats
- How microprocessors use internal registers and external memory, with memory divided into segments accessed via offsets
- How memory is addressed through decoding the address lines to select individual memory locations
- Instruction codes for operations like INC and MOV, which can be 1-4 bytes long
Microprocessors-based systems (under graduate course) Lecture 8 of 9 Randa Elanwar
This document provides an overview of the 8086/8088 instruction set as presented in a lecture by Dr. Randa Elanwar. It discusses machine control and flag manipulation instructions, string manipulation instructions, loop instructions, input/output ports and interfacing instructions. Specific instructions are explained, such as MOVS, CMPS, SCAS, LODS, STOS, IN, and OUT. Examples are provided to illustrate how to move a byte string, find a byte in a string, and continuously check the status of external ports using interrupts. The document aims to explain the various instruction types and their applications in microprocessor-based systems.
Microprocessors-based systems (under graduate course) Lecture 5 of 9 Randa Elanwar
The document discusses RISC and CISC architectures, memory segmentation, address decoding, and instruction codes. It provides details on:
- RISC vs CISC characteristics including number of instructions, addressing modes, and instruction formats
- How microprocessors use internal registers and external memory, with memory divided into segments accessed via offsets
- How memory is addressed through decoding the address lines to select individual memory locations
- Instruction codes for operations like INC and MOV, which can be 1-4 bytes long
The document discusses different methods of input/output (I/O) operations in microprocessors, including programmed I/O, interrupt I/O, and direct memory access (DMA). Programmed I/O involves the microprocessor executing instructions to transfer data via I/O ports. Interrupt I/O allows external devices to trigger an interrupt service routine. DMA allows data transfers directly between memory and external devices without microprocessor involvement using a DMA controller.
This document discusses the internal architecture of microprocessors. It begins by listing group members from the University of Gujrat in Pakistan. It then covers several topics regarding microprocessor architecture, including:
1. Internal structures of single-core and dual-core microprocessors.
2. Program visible and invisible programming models and how registers are accessed.
3. Details about general purpose registers like RAX, RBX, RCX, RDX and segment registers.
4. Special purpose registers including flags, instruction pointer, and stack pointer.
The document describes the 8051 microcontroller, its features which include 4 I/O ports, 2 timers, serial communication interface, and interrupts. It discusses the internal architecture such as memory organization, registers, and oscillator circuit. The document also provides details on the ports, timers, serial communication, and power modes of the 8051 microcontroller.
Detailed Explanation of Pin Description of 8085 microprocessorRamesh Dabhole
The document describes the pin diagram and functions of the 40 pins in the 8085 microprocessor. It discusses 14 groups of pins: 1) clock input pins, 2) reset output pin, 3) serial I/O pins, 4) interrupt pins, 5) address/data pins, 6) power/ground pins, 7) address output pins, 8) status/control pins, 9) interrupt pin, 10) interrupt acknowledgement pin, 11) address/data pins, 12) ground pin, 13) higher-order address pins, and 14) power input pin. Each group of pins has a specific role in executing instructions and transferring data in the 8085 microprocessor.
The document discusses various concepts related to microprocessors including:
1. It defines a microprocessor as a program controlled semiconductor device that fetches, decodes and executes instructions. The basic units of a microprocessor are an ALU, registers and a control unit.
2. A bus is defined as a group of conducting lines that carries data, address and control signals. The data bus is bi-directional to allow the microprocessor to read from and write to memory or I/O devices.
3. A machine cycle is the time required to complete one memory, I/O or acknowledge operation and may consist of 3-6 T-states. A T-state is one clock period subdivision of
The document describes the architecture and instruction set of the 8051 microcontroller. It includes details about the memory map, internal data memory organization, special function registers, addressing modes, and common instructions. The 8051 has 4KB of on-chip ROM, 128 bytes of internal RAM, 21 special function registers, and supports operations on bytes, bits, and 16-bit data using various addressing modes like register, direct, indirect, and immediate addressing. Instructions allow data transfer, arithmetic, logic, and program control operations.
The document discusses specifications and pinouts of the 8086 and 8088 microprocessors. It describes that both are 16-bit processors packaged in 40-pin DIP packages, with the 8086 having a 16-bit data bus and the 8088 having an 8-bit data bus. It also discusses the 8284A clock generator chip used with these processors, providing clock signals, reset synchronization and ready synchronization. The document outlines the bus timing of the processors over four clock cycles and how the ready pin inserts wait states for slower memory and I/O components.
The Intel 8257 is a 4-channel DMA controller that allows peripheral devices to directly access memory without involving the CPU. It has priority logic to handle requests from peripherals and issues memory addresses for read/write operations. Each channel has programmable address and count registers and can perform read, write, or verify transfers of up to 64kb of data independently. It uses a master/slave mode and rotating or fixed priority schemes to efficiently manage DMA requests and bus access for high-speed data transfers between peripherals and memory.
The document discusses the memory organization and registers of the 8051 microcontroller. It describes the program memory and data memory, which are implemented using EPROM and RAM respectively. It then discusses the different registers of the 8051 including the accumulator, B register, data pointer register, stack pointer register, and special function registers. The special function registers are used for tasks like timer control and interrupt control.
Flag registers, addressing modes, instruction setaviban
This document provides an agenda and details for a discussion on the 8086 microprocessor. It includes sections on flag registers, addressing modes, and the instruction set. The flag register is described as a 16-bit register containing status flags like carry, parity, auxiliary, zero, and sign flags as well as control flags like trap, interrupt, and direction flags. Various addressing modes are explained for accessing operands in memory using registers, offsets, and displacements. The instruction set section lists common instructions and their purposes. Registers on the 8086 like the general purpose, index, stack pointer, and segment registers are defined along with the instruction execution cycle.
The document discusses the instruction set of the 8051 microcontroller. It describes that the 8051 has 255 total instructions divided into categories like arithmetic, branch, data transfer, logic, and bit-oriented instructions. It provides details on the operation and syntax of common instructions like ADD, SUB, MOV, JMP, CALL and others. It also gives some basic programming problems as examples to perform operations like subtraction, data exchange and addition using 8051 instructions.
The 8051 microcontroller has an 8-bit CPU, 64KB program memory, 64KB data memory, 4KB onboard program memory, 128 bytes onboard data RAM, 32 I/O lines, two 16-bit timers/counters, a full duplex UART, and a 6-source interrupt structure. It consists of a CPU, two memory sections, I/O ports, special function registers, and control logic connected via an 8-bit internal data bus. The 8051 has 40 pins, with some pins having alternate functions.
This document is a tutorial on the 8051 microcontroller. It includes chapters that overview the 8051 architecture, provide a design example, and cover topics like interrupts, timers/counters, and the serial port. Reference materials are provided, such as books, websites, and a server location for additional information. A comparison is made between the low-power 8051 and more powerful Pentium processors. The 8051 chip features like two timers/counters and I/O ports are also detailed.
The document provides information about the Intel 8085 microprocessor system. It discusses the history of Intel microprocessors before 8085 including the 4004, 8008, and 8080. It then provides details about the 8085 such as its year of release, number of transistors, clock speed, pin configuration, and functions of the pins. The document also describes the architecture of the 8085 including its functional blocks like registers, ALU, data/address buffer, and interrupt control. It explains the different instruction word sizes and addressing modes in the 8085.
The document discusses the Intel 8086 microprocessor. It provides details about its introduction, architecture, registers, addressing modes, and operation. Specifically:
- The Intel 8086 is a 16-bit microprocessor introduced in 1978 that gave rise to the x86 architecture. It has approximately 29,000 transistors and a 16-bit data bus.
- The architecture is divided into two units - the Bus Interface Unit which handles fetching and memory/I/O operations, and the Execution Unit which decodes/executes instructions.
- It has segment registers to address memory segments, general purpose registers like AX, BX, CX and DX, and a flag register. Addressing modes include register, direct
The document provides information on the architecture of the 8085 microprocessor. It discusses the different busses used - the address bus, data bus and control bus. It describes the internal architecture of the 8085 including registers like the accumulator, flags, program counter and stack pointer. It also discusses the different types of operations like memory read/write, I/O read/write. Memory organization and addressing are explained along with the concept of memory mapping.
The document discusses interrupts in computing systems. It defines an interrupt as either a hardware-generated call from an external signal or a software-generated call from an instruction. The main purposes of interrupts are to halt normal program execution and divert processing to an interrupt service routine in response to external events. It then provides details on different types of interrupts, including hardware interrupts from devices and software interrupts from instructions. It lists and describes the most common interrupt types and their associated vector numbers.
The stack is a group of memory locations used for temporary storage of data during program execution. Data is stored onto the stack in reverse order using PUSH instructions and retrieved using POP instructions. The stack pointer register (SP) points to the top of the stack. Subroutines use the stack to store the return address by pushing it onto the stack with a CALL instruction and popping it back into the program counter with a RET instruction. Conditional and restart CALL instructions transfer program flow based on flag settings or to fixed memory locations.
The document discusses different methods of input/output (I/O) operations in microprocessors, including programmed I/O, interrupt I/O, and direct memory access (DMA). Programmed I/O involves the microprocessor executing instructions to transfer data via I/O ports. Interrupt I/O allows external devices to trigger an interrupt service routine. DMA allows data transfers directly between memory and external devices without microprocessor involvement using a DMA controller.
This document discusses the internal architecture of microprocessors. It begins by listing group members from the University of Gujrat in Pakistan. It then covers several topics regarding microprocessor architecture, including:
1. Internal structures of single-core and dual-core microprocessors.
2. Program visible and invisible programming models and how registers are accessed.
3. Details about general purpose registers like RAX, RBX, RCX, RDX and segment registers.
4. Special purpose registers including flags, instruction pointer, and stack pointer.
The document describes the 8051 microcontroller, its features which include 4 I/O ports, 2 timers, serial communication interface, and interrupts. It discusses the internal architecture such as memory organization, registers, and oscillator circuit. The document also provides details on the ports, timers, serial communication, and power modes of the 8051 microcontroller.
Detailed Explanation of Pin Description of 8085 microprocessorRamesh Dabhole
The document describes the pin diagram and functions of the 40 pins in the 8085 microprocessor. It discusses 14 groups of pins: 1) clock input pins, 2) reset output pin, 3) serial I/O pins, 4) interrupt pins, 5) address/data pins, 6) power/ground pins, 7) address output pins, 8) status/control pins, 9) interrupt pin, 10) interrupt acknowledgement pin, 11) address/data pins, 12) ground pin, 13) higher-order address pins, and 14) power input pin. Each group of pins has a specific role in executing instructions and transferring data in the 8085 microprocessor.
The document discusses various concepts related to microprocessors including:
1. It defines a microprocessor as a program controlled semiconductor device that fetches, decodes and executes instructions. The basic units of a microprocessor are an ALU, registers and a control unit.
2. A bus is defined as a group of conducting lines that carries data, address and control signals. The data bus is bi-directional to allow the microprocessor to read from and write to memory or I/O devices.
3. A machine cycle is the time required to complete one memory, I/O or acknowledge operation and may consist of 3-6 T-states. A T-state is one clock period subdivision of
The document describes the architecture and instruction set of the 8051 microcontroller. It includes details about the memory map, internal data memory organization, special function registers, addressing modes, and common instructions. The 8051 has 4KB of on-chip ROM, 128 bytes of internal RAM, 21 special function registers, and supports operations on bytes, bits, and 16-bit data using various addressing modes like register, direct, indirect, and immediate addressing. Instructions allow data transfer, arithmetic, logic, and program control operations.
The document discusses specifications and pinouts of the 8086 and 8088 microprocessors. It describes that both are 16-bit processors packaged in 40-pin DIP packages, with the 8086 having a 16-bit data bus and the 8088 having an 8-bit data bus. It also discusses the 8284A clock generator chip used with these processors, providing clock signals, reset synchronization and ready synchronization. The document outlines the bus timing of the processors over four clock cycles and how the ready pin inserts wait states for slower memory and I/O components.
The Intel 8257 is a 4-channel DMA controller that allows peripheral devices to directly access memory without involving the CPU. It has priority logic to handle requests from peripherals and issues memory addresses for read/write operations. Each channel has programmable address and count registers and can perform read, write, or verify transfers of up to 64kb of data independently. It uses a master/slave mode and rotating or fixed priority schemes to efficiently manage DMA requests and bus access for high-speed data transfers between peripherals and memory.
The document discusses the memory organization and registers of the 8051 microcontroller. It describes the program memory and data memory, which are implemented using EPROM and RAM respectively. It then discusses the different registers of the 8051 including the accumulator, B register, data pointer register, stack pointer register, and special function registers. The special function registers are used for tasks like timer control and interrupt control.
Flag registers, addressing modes, instruction setaviban
This document provides an agenda and details for a discussion on the 8086 microprocessor. It includes sections on flag registers, addressing modes, and the instruction set. The flag register is described as a 16-bit register containing status flags like carry, parity, auxiliary, zero, and sign flags as well as control flags like trap, interrupt, and direction flags. Various addressing modes are explained for accessing operands in memory using registers, offsets, and displacements. The instruction set section lists common instructions and their purposes. Registers on the 8086 like the general purpose, index, stack pointer, and segment registers are defined along with the instruction execution cycle.
The document discusses the instruction set of the 8051 microcontroller. It describes that the 8051 has 255 total instructions divided into categories like arithmetic, branch, data transfer, logic, and bit-oriented instructions. It provides details on the operation and syntax of common instructions like ADD, SUB, MOV, JMP, CALL and others. It also gives some basic programming problems as examples to perform operations like subtraction, data exchange and addition using 8051 instructions.
The 8051 microcontroller has an 8-bit CPU, 64KB program memory, 64KB data memory, 4KB onboard program memory, 128 bytes onboard data RAM, 32 I/O lines, two 16-bit timers/counters, a full duplex UART, and a 6-source interrupt structure. It consists of a CPU, two memory sections, I/O ports, special function registers, and control logic connected via an 8-bit internal data bus. The 8051 has 40 pins, with some pins having alternate functions.
This document is a tutorial on the 8051 microcontroller. It includes chapters that overview the 8051 architecture, provide a design example, and cover topics like interrupts, timers/counters, and the serial port. Reference materials are provided, such as books, websites, and a server location for additional information. A comparison is made between the low-power 8051 and more powerful Pentium processors. The 8051 chip features like two timers/counters and I/O ports are also detailed.
The document provides information about the Intel 8085 microprocessor system. It discusses the history of Intel microprocessors before 8085 including the 4004, 8008, and 8080. It then provides details about the 8085 such as its year of release, number of transistors, clock speed, pin configuration, and functions of the pins. The document also describes the architecture of the 8085 including its functional blocks like registers, ALU, data/address buffer, and interrupt control. It explains the different instruction word sizes and addressing modes in the 8085.
The document discusses the Intel 8086 microprocessor. It provides details about its introduction, architecture, registers, addressing modes, and operation. Specifically:
- The Intel 8086 is a 16-bit microprocessor introduced in 1978 that gave rise to the x86 architecture. It has approximately 29,000 transistors and a 16-bit data bus.
- The architecture is divided into two units - the Bus Interface Unit which handles fetching and memory/I/O operations, and the Execution Unit which decodes/executes instructions.
- It has segment registers to address memory segments, general purpose registers like AX, BX, CX and DX, and a flag register. Addressing modes include register, direct
The document provides information on the architecture of the 8085 microprocessor. It discusses the different busses used - the address bus, data bus and control bus. It describes the internal architecture of the 8085 including registers like the accumulator, flags, program counter and stack pointer. It also discusses the different types of operations like memory read/write, I/O read/write. Memory organization and addressing are explained along with the concept of memory mapping.
The document discusses interrupts in computing systems. It defines an interrupt as either a hardware-generated call from an external signal or a software-generated call from an instruction. The main purposes of interrupts are to halt normal program execution and divert processing to an interrupt service routine in response to external events. It then provides details on different types of interrupts, including hardware interrupts from devices and software interrupts from instructions. It lists and describes the most common interrupt types and their associated vector numbers.
The stack is a group of memory locations used for temporary storage of data during program execution. Data is stored onto the stack in reverse order using PUSH instructions and retrieved using POP instructions. The stack pointer register (SP) points to the top of the stack. Subroutines use the stack to store the return address by pushing it onto the stack with a CALL instruction and popping it back into the program counter with a RET instruction. Conditional and restart CALL instructions transfer program flow based on flag settings or to fixed memory locations.
(a)Suppose the main memory of the Pep8 were completely filled with .docxajoy21
The document provides information about the Pep/8 computer system including its hardware components, memory structure, instruction set format, and individual instruction specifications. It then asks three questions:
(a) If the main memory was filled with unary instructions, it could hold 65,536 instructions.
(b) If filled with non-unary instructions, it could hold 32,768 instructions.
(c) If filled equally with unary and non-unary instructions, it could hold 49,152 total instructions.
The document discusses stack operations in the 8085 microprocessor. It contains the following key points:
1. The 8085 uses a last-in, first-out (LIFO) stack implemented in RAM. It has two stack instructions: PUSH pushes data onto the stack, and POP pops data off the stack into registers.
2. The stack pointer (SP) register points to the top of the stack. It is decremented by PUSH and incremented by POP.
3. Subroutines use the stack to store the return address by pushing the program counter before branching to the subroutine. The return instruction POPs the address back to resume the main program.
4. T
The document discusses stacks and subroutines in 8085 microprocessors. It describes how the stack is an area of memory used for temporary storage of information in a LIFO manner using a stack pointer register. Information is stored on the stack using the PUSH instruction and retrieved using POP. Subroutines allow commonly used code to be executed from different locations in a program by using the CALL instruction to transfer program flow to the subroutine and the RET instruction to return to the main program. Parameters can be passed between the main program and subroutines using registers or memory locations.
The document discusses stack and subroutines in assembly language programs. It explains that stack is used to store return addresses and save register contents. Subroutines allow breaking programs into modules and use CALL and RET instructions. An example program adds two numbers stored in memory locations and returns the result.
The document discusses concepts related to instruction addressing and execution in computer architecture. It explains that programs are loaded into separate code, data, and stack segments in memory. When an *.exe file is loaded, it places the program after a 256-byte Program Segment Prefix on a paragraph boundary, and loads the segment registers with the starting addresses of code, data, and stack. It then provides examples of instruction fetching and decoding, showing how the segment and instruction pointers are used to determine memory addresses for instruction execution.
This document discusses procedures, macros, and stack operations in assembly language. It explains that procedures allow repetitive code to be written once and called multiple times to save memory. Procedures use stack operations to push return addresses and data onto the stack. Macros simplify programming by reducing repetitive code. Procedures are called at runtime, while macro calls are replaced with their body at assembly time.
The 8086 CPU has two functional units - the Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and writes data to memory or ports. It uses an instruction queue to pre-fetch up to 6 bytes to improve execution speed. The EU decodes instructions and performs operations using its 16-bit ALU. The 8086 has general purpose registers including AX, BX, CX and DX and segment registers for addressing memory. It uses flags to indicate the result of operations.
The 8086 CPU is a 16-bit microprocessor with a 16-bit data bus, 20-bit address bus, and includes an ALU, BIU, and EU. The BIU fetches instructions and data from memory using segment registers and address pointers, while the EU decodes and executes instructions using general purpose registers like AX, BX, CX, DX, and flags. Memory is divided into segments of up to 64KB that can overlap. The 8086 supports various addressing modes to access memory locations.
The document discusses assembly language programming. It begins by explaining that assembly language is a low-level programming language useful for embedded systems and device drivers due to its close correspondence to machine code and ability to optimize for speed and size. The document then provides details on memory organization, addressing modes, interrupts, and an example program to test the program status word register in assembly language.
The document provides an overview of the 8085 microprocessor architecture and its assembly language programming. It discusses the 8085 block diagram, instruction set, sample assembly programs, use of counters and delays, stack and subroutines. It then introduces the 8086 and x86 architectures. The next class will cover the 8086 architecture in more detail, advanced 32-bit architectures, the x86 programming model, 8086 assembly language programming, and x86 assemblers.
The document provides an overview of the 8085 microprocessor architecture and its assembly language programming. It discusses the 8085 block diagram, instruction set, sample assembly programs, use of counters and delays, stack and subroutines. It then introduces the 8086 and x86 architectures. The next class will cover the 8086 architecture in more detail, advanced 32-bit architectures, the x86 programming model, 8086 assembly language programming, and x86 assemblers.
The document discusses the instruction set of the 8086 microprocessor. It is divided into 7 sections that cover: 1) data transfer instructions like MOV, IN, OUT, PUSH, and POP; 2) arithmetic/logical instructions; 3) branch instructions; 4) shift and rotate instructions; 5) string manipulation instructions; 6) flag manipulation and processor control instructions; and 7) machine control instructions. Examples are provided for each type of instruction to illustrate their operation and effect on registers or memory locations.
Introduction to Processor Design and ARM ProcessorDarling Jemima
The document discusses computer architecture and the MU0 processor. It provides details on MU0's instruction set, which uses 1-address instructions and has a small set of instructions including LDA, STA, ADD, SUB, JMP, JGE, JNE, and STP. The document also explains MU0's design, which has a program counter, accumulator, instruction register, and arithmetic logic unit. It describes how MU0 executes sample instructions in a step-by-step fashion.
This document discusses procedures in assembly language. It covers defining procedures, calling procedures using the CALL and RET instructions, passing parameters to procedures, and managing the runtime stack. Procedures use stack frames to access parameters passed on the stack and allocate space for local variables. Examples are provided of procedures that pass arguments by value and by reference.
This document provides an introduction to NASM assembly language programming. It covers basics of computer organization including the processor, registers, buses, and memory. It then discusses specifics of NASM like instruction syntax, data types, and I/O. The document is intended as a reference for students learning NASM assembly programming and was updated by multiple authors under the guidance of professors at NIT Calicut.
The document discusses the central processing unit (CPU) of a computer. It describes the three major parts of the CPU - the control unit, the arithmetic logic unit (ALU), and the register set. The control unit supervises operations and instructs the ALU. The register set stores intermediate data. The ALU performs arithmetic and logic operations to execute instructions. Memory units and instruction formats are also discussed.
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الجزء السادس ماذا ستقدم لعميلك ريادة الأعمال خطوة بخطوةRanda Elanwar
فى هذه السلسلة (السلسلة الثانية) نستكمل تقديم أساسيات علم ريادة الأعمال التجارية Business Entrepreneurship التى تحتاج أن تتعلمها قبل أن تقوم ببناء شركتك أو مؤسستك الهادفة للربح؛ حتى تتعرف على الخطوات الأولية للعمل وكيفية تنفيذها، وتكتشف المفاهيم الخاطئة السائدة، ثم تقوم فى النهاية ببناء تجارتك على أساس صحيح من وجهة نظر العميل، وليس من وجهة نظرك كصاحب العمل. هذه السلسلة هى ملخص للدروس المستفادة من دورة ريادة الأعمال المفتوحة التى يقدمها معهد ماساتشوستس للتقنية MIT على منصة Edx بعنوان MITx: 15.390.2x Entrepreneurship 102: What can you do for your customer?
رابط الدورة: https://www.edx.org/course/entrepreneurship-102-what-can-you-do-mitx-15-390-2x
الجزء الرابع ماذا ستقدم لعميلك ريادة الأعمال خطوة بخطوةRanda Elanwar
فى هذه السلسلة (السلسلة الثانية) نستكمل تقديم أساسيات علم ريادة الأعمال التجارية Business Entrepreneurship التى تحتاج أن تتعلمها قبل أن تقوم ببناء شركتك أو مؤسستك الهادفة للربح؛ حتى تتعرف على الخطوات الأولية للعمل وكيفية تنفيذها، وتكتشف المفاهيم الخاطئة السائدة، ثم تقوم فى النهاية ببناء تجارتك على أساس صحيح من وجهة نظر العميل، وليس من وجهة نظرك كصاحب العمل. هذه السلسلة هى ملخص للدروس المستفادة من دورة ريادة الأعمال المفتوحة التى يقدمها معهد ماساتشوستس للتقنية MIT على منصة Edx بعنوان MITx: 15.390.2x Entrepreneurship 102: What can you do for your customer?
رابط الدورة: https://www.edx.org/course/entrepreneurship-102-what-can-you-do-mitx-15-390-2x
الجزء الثاني ماذا ستقدم لعميلك ريادة الأعمال خطوة بخطوةRanda Elanwar
فى هذه السلسلة (السلسلة الثانية) نستكمل تقديم أساسيات علم ريادة الأعمال التجارية Business Entrepreneurship التى تحتاج أن تتعلمها قبل أن تقوم ببناء شركتك أو مؤسستك الهادفة للربح؛ حتى تتعرف على الخطوات الأولية للعمل وكيفية تنفيذها، وتكتشف المفاهيم الخاطئة السائدة، ثم تقوم فى النهاية ببناء تجارتك على أساس صحيح من وجهة نظر العميل، وليس من وجهة نظرك كصاحب العمل. هذه السلسلة هى ملخص للدروس المستفادة من دورة ريادة الأعمال المفتوحة التى يقدمها معهد ماساتشوستس للتقنية MIT على منصة Edx بعنوان MITx: 15.390.2x Entrepreneurship 102: What can you do for your customer?
رابط الدورة: https://www.edx.org/course/entrepreneurship-102-what-can-you-do-mitx-15-390-2x
تدريب مدونة علماء مصر على الكتابة الفنية (الترجمة والتلخيص )_Pdf5of5Randa Elanwar
The document discusses translation, including what translation is, why we translate, and what is translated. It covers the different types of translation including literal, faithful, and free translation. It provides examples of fields that use translation such as diplomacy, industry, culture, science, history, economics, and politics. Translation is important for sharing knowledge and opening communication between peoples. The summary provides a high-level overview of the key topics and concepts discussed in the original Arabic document in 3 sentences.
تدريب مدونة علماء مصر على الكتابة الفنية (القصة القصيرة والخاطرة والأخطاء ال...Randa Elanwar
مرحبا بكم فى التدريب الأساسى لمدونى علماء مصر
التدريب الأساسى هو فقط مقدمة شاملة لتوسيع المدارك، وتصحيح المفاهيم الخاطئة، ولا يهدف إلى تدريب متخصص فى أى المحاور التى يتناولها
أولا: المقدمة وفيها تعريف بأبواب المدونة وأمثلة للمواضيع الفرعية التى يمكنك الكتابة فيها ومحاور التدريب
ثانيا: المحور الأول وفيه تدريب على هدف وهيكل المقالات المبنية على البحث واختيار الكلمات المفتاحية مع أمثلة
ثالثا: المحور الثانى وفيه تدريب على هدف وهيكل المقالات الإخبارية مع أمثلة
رابعا: المحور الثالث وفيه تدريب على هدف وهيكل مقالات الموارد مع أمثلة
خامسا: المحور الرابع وفيه تدريب على فنيات الكتابة للمقالات والقصة القصيرة والخاطرة وتلخيص للأخطاء اللغوية والإملائية الشائعة وعلامات الترقيم
سادسا المحور الخامس وفيه تدريب على كيفية الترجمة والتلخيص وأهم النصائح والأدوات
تدريب مدونة علماء مصر على الكتابة الفنية (مقالات الموارد )_Pdf3of5Randa Elanwar
مرحبا بكم فى التدريب الأساسى لمدونى علماء مصر
التدريب الأساسى هو فقط مقدمة شاملة لتوسيع المدارك، وتصحيح المفاهيم الخاطئة، ولا يهدف إلى تدريب متخصص فى أى المحاور التى يتناولها
أولا: المقدمة وفيها تعريف بأبواب المدونة وأمثلة للمواضيع الفرعية التى يمكنك الكتابة فيها ومحاور التدريب
ثانيا: المحور الأول وفيه تدريب على هدف وهيكل المقالات المبنية على البحث واختيار الكلمات المفتاحية مع أمثلة
ثالثا: المحور الثانى وفيه تدريب على هدف وهيكل المقالات الإخبارية مع أمثلة
رابعا: المحور الثالث وفيه تدريب على هدف وهيكل مقالات الموارد مع أمثلة
خامسا: المحور الرابع وفيه تدريب على فنيات الكتابة للمقالات والقصة القصيرة والخاطرة وتلخيص للأخطاء اللغوية والإملائية الشائعة وعلامات الترقيم
سادسا المحور الخامس وفيه تدريب على كيفية الترجمة والتلخيص وأهم النصائح والأدوات
تدريب مدونة علماء مصر على الكتابة الفنية (المقالات الإخبارية )_Pdf2of5Randa Elanwar
مرحبا بكم فى التدريب الأساسى لمدونى علماء مصر
التدريب الأساسى هو فقط مقدمة شاملة لتوسيع المدارك، وتصحيح المفاهيم الخاطئة، ولا يهدف إلى تدريب متخصص فى أى المحاور التى يتناولها
أولا: المقدمة وفيها تعريف بأبواب المدونة وأمثلة للمواضيع الفرعية التى يمكنك الكتابة فيها ومحاور التدريب
ثانيا: المحور الأول وفيه تدريب على هدف وهيكل المقالات المبنية على البحث واختيار الكلمات المفتاحية مع أمثلة
ثالثا: المحور الثانى وفيه تدريب على هدف وهيكل المقالات الإخبارية مع أمثلة
رابعا: المحور الثالث وفيه تدريب على هدف وهيكل مقالات الموارد مع أمثلة
خامسا: المحور الرابع وفيه تدريب على فنيات الكتابة للمقالات والقصة القصيرة والخاطرة وتلخيص للأخطاء اللغوية والإملائية الشائعة وعلامات الترقيم
سادسا المحور الخامس وفيه تدريب على كيفية الترجمة والتلخيص وأهم النصائح والأدوات
تدريب مدونة علماء مصر على الكتابة الفنية (المقالات المبنية على البحث )_Pdf1of5Randa Elanwar
Egyptian scientists are developing a program called "Writing Skills" to help bloggers improve their writing abilities. The program covers various topics such as researching topics and sources for articles, structuring articles, citing sources, concluding articles, editing and reviewing articles, establishing the writer's point of view, and ending with a conclusion paragraph. Some key characteristics of a well-written article include being engaging, having a moderate length, clear language, an intriguing style, original ideas for readers, high-quality presentation of ideas, and supporting details and examples.
تعريف بمدونة علماء مصر ومحاور التدريب على الكتابة للمدونينRanda Elanwar
مرحبا بكم فى التدريب الأساسى لمدونى علماء مصر
التدريب الأساسى هو فقط مقدمة شاملة لتوسيع المدارك، وتصحيح المفاهيم الخاطئة، ولا يهدف إلى تدريب متخصص فى أى المحاور التى يتناولها
أولا: المقدمة وفيها تعريف بأبواب المدونة وأمثلة للمواضيع الفرعية التى يمكنك الكتابة فيها ومحاور التدريب
ثانيا: المحور الأول وفيه تدريب على هدف وهيكل المقالات المبنية على البحث واختيار الكلمات المفتاحية مع أمثلة
ثالثا: المحور الثانى وفيه تدريب على هدف وهيكل المقالات الإخبارية مع أمثلة
رابعا: المحور الثالث وفيه تدريب على هدف وهيكل مقالات الموارد مع أمثلة
خامسا: المحور الرابع وفيه تدريب على فنيات الكتابة للمقالات والقصة القصيرة والخاطرة وتلخيص للأخطاء اللغوية والإملائية الشائعة وعلامات الترقيم
سادسا المحور الخامس وفيه تدريب على كيفية الترجمة والتلخيص وأهم النصائح والأدوات
فى هذه السلسلة نقدم لك أساسيات علم ريادة الأعمال التجارية
Business Entrepreneurship
التى تحتاج أن تتعلمها قبل أن تقوم ببناء شركتك أو مؤسستك الهادفة للربح؛ حتى تتعرف على الخطوات الأولية للعمل وكيفية تنفيذها، وتكتشف المفاهيم الخاطئة السائدة، ثم تقوم فى النهاية ببناء تجارتك على أساس صحيح من وجهة نظر العميل، وليس من وجهة نظرك كصاحب العمل. هذه السلسلة هى ملخص للدروس المستفادة من دورة ريادة الأعمال المفتوحة التى يقدمها معهد ماساتشوستس للتقنية
MIT
على منصة
Edx
بعنوان
MITx: 15.390.1x Entrepreneurship 101: Who is your customer?
رابط الدورة:
https://www.edx.org/course/entrepreneurship-101-who-customer-mitx-15-390-1x#.VL-MN0eUfHA
فى هذه السلسلة نقدم لك أساسيات علم ريادة الأعمال التجارية
Business Entrepreneurship
التى تحتاج أن تتعلمها قبل أن تقوم ببناء شركتك أو مؤسستك الهادفة للربح؛ حتى تتعرف على الخطوات الأولية للعمل وكيفية تنفيذها، وتكتشف المفاهيم الخاطئة السائدة، ثم تقوم فى النهاية ببناء تجارتك على أساس صحيح من وجهة نظر العميل، وليس من وجهة نظرك كصاحب العمل. هذه السلسلة هى ملخص للدروس المستفادة من دورة ريادة الأعمال المفتوحة التى يقدمها معهد ماساتشوستس للتقنية
MIT
على منصة
Edx
بعنوان
MITx: 15.390.1x Entrepreneurship 101: Who is your customer?
رابط الدورة:
https://www.edx.org/course/entrepreneurship-101-who-customer-mitx-15-390-1x#.VL-MN0eUfHA
فى هذه السلسلة نقدم لك أساسيات علم ريادة الأعمال التجارية
Business Entrepreneurship
التى تحتاج أن تتعلمها قبل أن تقوم ببناء شركتك أو مؤسستك الهادفة للربح؛ حتى تتعرف على الخطوات الأولية للعمل وكيفية تنفيذها، وتكتشف المفاهيم الخاطئة السائدة، ثم تقوم فى النهاية ببناء تجارتك على أساس صحيح من وجهة نظر العميل، وليس من وجهة نظرك كصاحب العمل. هذه السلسلة هى ملخص للدروس المستفادة من دورة ريادة الأعمال المفتوحة التى يقدمها معهد ماساتشوستس للتقنية
MIT
على منصة
Edx
بعنوان
MITx: 15.390.1x Entrepreneurship 101: Who is your customer?
رابط الدورة:
https://www.edx.org/course/entrepreneurship-101-who-customer-mitx-15-390-1x#.VL-MN0eUfHA
فى هذه السلسلة نقدم لك أساسيات علم ريادة الأعمال التجارية
Business Entrepreneurship
التى تحتاج أن تتعلمها قبل أن تقوم ببناء شركتك أو مؤسستك الهادفة للربح؛ حتى تتعرف على الخطوات الأولية للعمل وكيفية تنفيذها، وتكتشف المفاهيم الخاطئة السائدة، ثم تقوم فى النهاية ببناء تجارتك على أساس صحيح من وجهة نظر العميل، وليس من وجهة نظرك كصاحب العمل. هذه السلسلة هى ملخص للدروس المستفادة من دورة ريادة الأعمال المفتوحة التى يقدمها معهد ماساتشوستس للتقنية
MIT
على منصة
Edx
بعنوان
MITx: 15.390.1x Entrepreneurship 101: Who is your customer?
رابط الدورة:
https://www.edx.org/course/entrepreneurship-101-who-customer-mitx-15-390-1x#.VL-MN0eUfHA
هي قصة مشوار بدأ ولم ينتهِ بعد. سيكون فيها كل يوم شيءٌ جديد. سأتعلم وسأحكي لكم ما تعلمته. ربما وفّرت عليك التجربة لتُغيّرَ كثيرًا من قناعات لديك.
إن كنت طالبًا، أو حديث التخرج، وتنوي عمل دراسات عليا بمصر، فدعني أعرّفك قليلًا على أشياء خارج توقعاتك، إن لم يكن لديك فكرة. وإن كنت قد اتخذت خطواتك الأولى بالفعل فربما تجد في قصّتي ما يفسر ألغازك، ويهوّن عليك المفاجآت. لن أقول لك الآن ما مجال دراستي، فرغم احتمال أن تكون دارسًا لتخصصٍ آخر يختلف عني، ولكنني أثق أن لديك نفس الأسئلة، ونفس الشكوى
هي قصة مشوار بدأ ولم ينتهِ بعد. سيكون فيها كل يوم شيءٌ جديد. سأتعلم وسأحكي لكم ما تعلمته. ربما وفّرت عليك التجربة لتُغيّرَ كثيرًا من قناعات لديك.
إن كنت طالبًا، أو حديث التخرج، وتنوي عمل دراسات عليا بمصر، فدعني أعرّفك قليلًا على أشياء خارج توقعاتك، إن لم يكن لديك فكرة. وإن كنت قد اتخذت خطواتك الأولى بالفعل فربما تجد في قصّتي ما يفسر ألغازك، ويهوّن عليك المفاجآت. لن أقول لك الآن ما مجال دراستي، فرغم احتمال أن تكون دارسًا لتخصصٍ آخر يختلف عني، ولكنني أثق أن لديك نفس الأسئلة، ونفس الشكوى.
Information and Communication Technology in EducationMJDuyan
(𝐓𝐋𝐄 𝟏𝟎𝟎) (𝐋𝐞𝐬𝐬𝐨𝐧 2)-𝐏𝐫𝐞𝐥𝐢𝐦𝐬
𝐄𝐱𝐩𝐥𝐚𝐢𝐧 𝐭𝐡𝐞 𝐈𝐂𝐓 𝐢𝐧 𝐞𝐝𝐮𝐜𝐚𝐭𝐢𝐨𝐧:
Students will be able to explain the role and impact of Information and Communication Technology (ICT) in education. They will understand how ICT tools, such as computers, the internet, and educational software, enhance learning and teaching processes. By exploring various ICT applications, students will recognize how these technologies facilitate access to information, improve communication, support collaboration, and enable personalized learning experiences.
𝐃𝐢𝐬𝐜𝐮𝐬𝐬 𝐭𝐡𝐞 𝐫𝐞𝐥𝐢𝐚𝐛𝐥𝐞 𝐬𝐨𝐮𝐫𝐜𝐞𝐬 𝐨𝐧 𝐭𝐡𝐞 𝐢𝐧𝐭𝐞𝐫𝐧𝐞𝐭:
-Students will be able to discuss what constitutes reliable sources on the internet. They will learn to identify key characteristics of trustworthy information, such as credibility, accuracy, and authority. By examining different types of online sources, students will develop skills to evaluate the reliability of websites and content, ensuring they can distinguish between reputable information and misinformation.
Andreas Schleicher presents PISA 2022 Volume III - Creative Thinking - 18 Jun...EduSkills OECD
Andreas Schleicher, Director of Education and Skills at the OECD presents at the launch of PISA 2022 Volume III - Creative Minds, Creative Schools on 18 June 2024.
Temple of Asclepius in Thrace. Excavation resultsKrassimira Luka
The temple and the sanctuary around were dedicated to Asklepios Zmidrenus. This name has been known since 1875 when an inscription dedicated to him was discovered in Rome. The inscription is dated in 227 AD and was left by soldiers originating from the city of Philippopolis (modern Plovdiv).
Elevate Your Nonprofit's Online Presence_ A Guide to Effective SEO Strategies...TechSoup
Whether you're new to SEO or looking to refine your existing strategies, this webinar will provide you with actionable insights and practical tips to elevate your nonprofit's online presence.
Level 3 NCEA - NZ: A Nation In the Making 1872 - 1900 SML.pptHenry Hollis
The History of NZ 1870-1900.
Making of a Nation.
From the NZ Wars to Liberals,
Richard Seddon, George Grey,
Social Laboratory, New Zealand,
Confiscations, Kotahitanga, Kingitanga, Parliament, Suffrage, Repudiation, Economic Change, Agriculture, Gold Mining, Timber, Flax, Sheep, Dairying,
How to Setup Default Value for a Field in Odoo 17Celine George
In Odoo, we can set a default value for a field during the creation of a record for a model. We have many methods in odoo for setting a default value to the field.
Gender and Mental Health - Counselling and Family Therapy Applications and In...PsychoTech Services
A proprietary approach developed by bringing together the best of learning theories from Psychology, design principles from the world of visualization, and pedagogical methods from over a decade of training experience, that enables you to: Learn better, faster!
A Free 200-Page eBook ~ Brain and Mind Exercise.pptxOH TEIK BIN
(A Free eBook comprising 3 Sets of Presentation of a selection of Puzzles, Brain Teasers and Thinking Problems to exercise both the mind and the Right and Left Brain. To help keep the mind and brain fit and healthy. Good for both the young and old alike.
Answers are given for all the puzzles and problems.)
With Metta,
Bro. Oh Teik Bin 🙏🤓🤔🥰
2. Lecture Content
• Memory access: Fetch-Decode-Execution
• Tracing Program Codes
• Application Examples
2
Microprocessor-Based Systems Dr. Randa Elanwar
3. Memory segmentation, address decoding
and direct access
• Since both the program and any subroutine use the same ALSU and
internal microprocessor registers, therefore, the current contents
may be destroyed. Thus, a copy of the contents should be saved in
stack to be re-copied back in sequence after the subroutine is
executed PUSH instruction
3
Microprocessor-Based Systems Dr. Randa Elanwar
CALL 600
CALL 7000
Main program
Subroutine 1
Subroutine 2
2000:120
2000:123
2000:600
650
653
7000
.
.
.
.
.
.
.
.
0653
0123
Stack
(memory
locations)
Stack
Pointer
4. 8086/8088 instruction set (CALL)
Unconditional Branch Instructions
• CALL: Unconditional Call: This instruction is used to call a subroutine from a
main program.
• In case of assembly language programming, the term procedure is used
interchangeably with subroutine. The address of the procedure may be
specified directly or indirectly depending upon the addressing mode.
• There are again two types of procedures depending upon whether it is
available in the same segment (Near CALL, i.e ± 32K displacement) or in
another segment (Far CALL, i.e. anywhere outside the segment).
• The modes for them are respectively called as intrasegment and
intersegment addressing modes. This instruction comes under
unconditional branch instructions and can be described as shown with the
coding formats.
• On execution, this instruction stores the incremented IP (i.e. address of the
next instruction) and CS onto the stack along with the flags and loads the CS
and IP registers, respectively, with the segment and offset addresses of the
procedure to be called.
4
Microprocessor-Based Systems Dr. Randa Elanwar
5. 8086/8088 instruction set (RET)
• Unconditional Branch Instructions
• RET: Return from the Procedure: At each CALL instruction, the IP
and CS of the next instruction is pushed onto stack, before the
control is transferred to the procedure.
• At the end of the procedure, the RET instruction must be
executed.
• When it is executed, the previously stored content of IP and CS
along with flags are retrieved into the CS, IP and flag registers from
the stack and the execution of the main program continues
further.
5
Microprocessor-Based Systems Dr. Randa Elanwar
6. 8086/8088 instruction set (PUSH-POP)
Data Copy/Transfer Instructions:
• PUSH: Push to Stack This instruction pushes the contents of the
specified register/memory location on to the stack.
• The stack pointer is decremented by 2, after each execution of
the instruction. The actual current stack-top is always occupied
by the previously pushed data. Hence, the push operation
decrements SP by two and then stores the two byte contents of
the operand onto the stack.
• The higher byte is pushed first and then the lower byte. Thus
out of the two decremented stack addresses the higher byte
occupies the higher address and the lower byte occupies the
lower address.
6
Microprocessor-Based Systems Dr. Randa Elanwar
7. 8086/8088 instruction set (PUSH-POP)
Data Copy/Transfer Instructions:
• POP: Pop from Stack This instruction when executed loads
the specified register/memory location with the contents of
the memory location of which the address is formed using
the current stack segment and stack pointer as usual.
• The stack pointer is incremented by 2. The POP instruction
serves exactly opposite to the PUSH instruction.
7
Microprocessor-Based Systems Dr. Randa Elanwar
8. 8086/8088 instruction set (PUSH-POP)
Data Copy/Transfer Instructions:
• PUSHF: Push Flags to Stack The push flag instruction pushes the
flag register on to the stack; first the upper byte and then the
lower byte will be pushed on to the stack. The SP is
decremented by 2, for each push operation. The general
operation of this instruction is similar to the PUSH operation.
• POPF: Pop Flags from Stack The pop flags instruction loads the
flag register completely (both bytes) from the word contents of
the memory location currently addressed by SP and SS. The SP
is incremented by 2 for each pop operation.
8
Microprocessor-Based Systems Dr. Randa Elanwar
9. Memory access: Fetch-Decode-Execution
9
Microprocessor-Based Systems Dr. Randa Elanwar
Programs
(Instruction
codes)
Data
Stack
External memory
divisions
SS: Stack segment register, holds the upper 16 bits
of the starting address for the program stack
SP: Stack pointer register, holds the offset of the
last location in the stack that has recently been
used for storage (top of the stack)
Example: main program
Address Instruction code meaning
2000:0111 E8 EC 00 CALL 200
2000:0114 ……. …….
.
.
.
2000:0200 50 PUSH AX
SS:SP
10. Memory access: Fetch-Decode-Execution
10
Microprocessor-Based Systems Dr. Randa Elanwar
Address Instruction code meaning
2000:0111 E8 EC 00 CALL 200
2000:0114 ……. …….
.
.
.
2000:0200 50 PUSH AX
Note 1: Data direction is either TO or FROM
microprocessor
TO: means the microprocessor reads/gets data
on the bus
FROM: means the microprocessor
writes/sends data to the memory
Note 2: the instruction code status is either
FETCHED or EXECUTED
It is first FETCHED till all bytes are stored in
instruction registers then becomes EXECUTED.
Tracing the micro-operations:
Address Data To/from Microprocessor Fetch/Execute
2000:0111 E8 To (stored in IR0) FETCH
2000:0112 EC To (stored in IR1) FETCH
2000:0113 00 To (stored in IR2) FETCH
SS:SP-1 01(higher byte) From (store return add. in memory) EXECUTE
SS:SP-2 14(lower byte) From (store return add. in memory) EXECUTE
2000:0200 50 To (stored in IR0) FETCH
11. Memory access: Fetch-Decode-Execution
• The PUSH instruction saves the content of a 16 bits register into
the stack. For example, saving AX will require saving AH first
(decrement SP) then saving AL in the location on the top of it.
• AH has to be saved even if the microprocessor is operating in the
8-bit mode.
• The POP instruction restores the content of a 16 bits register from
the stack. For example, restoring AX will require restoring AL first
(8 bits) then restoring AH from the location next to it (increment
SP).
• The POP instruction restores data from the memory location which
offset is stored in SP.
• BP: Base Pointer, allows navigation within the stack to take copies
of the stored data without messing up with the data storage order.
11
Microprocessor-Based Systems Dr. Randa Elanwar
12. Memory access: Fetch-Decode-Execution
• Important note:
• For more than 1 register, if we PUSH in some sequence we
POP in the reversed sequence.
• Example:
PUSH AX
PUSH DX
.
.
.
POP DX
POP AX
12
Microprocessor-Based Systems Dr. Randa Elanwar
13. Tracing Programs
13
Microprocessor-Based Systems Dr. Randa Elanwar
Main Program (11 instructions, 28 bytes)
140E:100 8C C8 MOV AX, CS
140E:102 8E DO MOV SS, AX
140E:104 BC FF FF MOV SP, FFFF
140E:107 0E PUSH CS
140E:108 1F POP DS
140E:109 8B 0F 03 06 MOV CX, [0603]
140E:10D BE 05 06 MOV SI, 0605
140E:110 E8 ED 00 CALL 200
140E:113 A3 01 06 MOV [0601], AX
140E:116 88 1E 00 06 MOV [0600],BL
140E:11A CD 20 INT 20
Subroutine 1 (13 instructions, 21 bytes)
140E:200 56 PUSH SI
140E:201 51 PUSH CX
140E:202 31 C0 XOR AX, AX
140E:204 02 04 ADD AL, [SI]
140E:206 80 D4 00 ADC AH, 0
140E:209 49 DEC CX
140E:20A E3 03 J CX Z 20F
140E:20C 46 INC SI
140E:20D EB F5 JMP 204
140E:20F E8 EE 00 CALL 300
140E:212 59 POP CX
140E:213 5E POP SI
140E:214 C3 RET
Subroutine 2 (6 instructions, 11 bytes)
140E:300 3C 40 00 CMP AX, 0040
140E:303 77 03 JA 308
140E:305 B3 00 MOV BL, 00
140E:307 C3 RET
140E:308 B3 01 MOV BL, 01
140E:30A C3 RET
14. Tracing Programs
• The aim of this program is to add the N elements of an array
(vector) and comparing the sum with 40 (Hex):
– If the sum > 40 store 1 in the memory location with offset 600
– If the sum < 40 store 0 in the memory location with offset 600
• The number of elements (array length) is stored in 2 bytes (603
and 604)
• In this example: the program, data and the stack are located in
the segment (140E), i.e., DS = SS = CS
thus we can differentiate between them through the range of
offsets:
Instructions (100 600), data (600 x) and stack (x FFFF)
14
Microprocessor-Based Systems Dr. Randa Elanwar
15. Tracing Programs
• The microprocessor to execute this program needs the
following:
1. Initialization to define the location of instructions, data and
stack
2. Know the number of array elements
3. Know the content of array
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Microprocessor-Based Systems Dr. Randa Elanwar
16. Tracing Programs
• Instructions from offset 104 to 105 forces the stack pointer to point
to the bottom of the stack (here the last location of the memory
segment 140E:FFFF)
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Microprocessor-Based Systems Dr. Randa Elanwar
MOV AX, CS
MOV SS, AX or
MOV DS, AX
MOV AX, CS
MOV SS, AX
PUSH CS
POP DS
Instructions from offset 100 to
108 store the value 140E in CS,
SS and DS (initialization)
MOV SS, CS Invalid instruction
This operation can be done by
one of two methods
Main Program (11 instructions, 28 bytes)
140E:100 8C C8 MOV AX, CS
140E:102 8E DO MOV SS, AX
140E:104 BC FF FF MOV SP, FFFF
140E:107 0E PUSH CS
140E:108 1F POP DS
140E:109 8B 0F 03 06 MOV CX, [0603]
140E:10D BE 05 06 MOV SI, 605
140E:110 E8 ED 00 CALL 200
140E:113 A3 01 06 MOV [0601], AX
140E:116 88 1E 00 06 MOV [0600],BL
140E:11A CD 20 INT 20
17. Tracing Programs
• Let the data stored in memory:
140E:600 xx xx xx 02 00 14 3C ………
• We need a counter = number of elements that is decremented on
each time we perform summation. Thus summation stops when the
counter = 0
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Microprocessor-Based Systems Dr. Randa Elanwar
8B 0F 03 06
MOV CX [0603]
The instructions from 109 to 10C
set the counter to the value
stored in the memory location
[0603]
[603] CL and [604] CH i.e.,
CL = 02 and CH = 00
Main Program (11 instructions, 28 bytes)
140E:100 8C C8 MOV AX, CS
140E:102 8E DO MOV SS, AX
140E:104 BC FF FF MOV SP, FFFF
140E:107 0E PUSH CS
140E:108 1F POP DS
140E:109 8B 0F 03 06 MOV CX, [0603]
140E:10D BE 05 06 MOV SI, 605
140E:110 E8 ED 00 CALL 200
140E:113 A3 01 06 MOV [0601], AX
140E:116 88 1E 00 06 MOV [0600],BL
140E:11A CD 20 INT 20
18. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
•We need the SI register to be
the source of data thus we
store the location of the first
array element in SI
(instructions from 10D to 10F)
•The instructions from 110 to
112 call a subroutine which
perform addition.
Main Program (11 instructions, 28 bytes)
140E:100 8C C8 MOV AX, CS
140E:102 8E DO MOV SS, AX
140E:104 BC FF FF MOV SP, FFFF
140E:107 0E PUSH CS
140E:108 1F POP DS
140E:109 8B 0F 03 06 MOV CX, [0603]
140E:10D BE 05 06 MOV SI, 605
140E:110 E8 ED 00 CALL 200
140E:113 A3 01 06 MOV [0601], AX
140E:116 88 1E 00 06 MOV [0600],BL
140E:11A CD 20 INT 20
•The instructions from 113 to 115 saves the final result of addition in the
location 140E:601 and 602 after the subroutines execution.
•The instruction 116 saves the result comparison in the location
140E:600 after the subroutines execution.
19. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
Subroutine 1 steps:
•The instructions from 200 to 201 save
the contents of SI and CX in the stack
to avoid changes
•The instructions 202 and 203 clear the
content of AX
•The instructions 204 and 205 add the
contents of SI to AL and puts the result
back into AL
•The instructions from 206 to 208 add
with carry the contents of AH to zero
•The instruction 209 decrements the
counter CX (holding the number of
elements)
Subroutine 1 (13 instructions, 21 bytes)
140E:200 56 PUSH SI
140E:201 51 PUSH CX
140E:202 31 C0 XOR AX, AX
140E:204 02 04 ADD AL, [SI]
140E:206 80 D4 00 ADC AH, 0
140E:209 49 DEC CX
140E:20A E3 03 J CX Z 20F
140E:20C 46 INC SI
140E:20D EB F5 JMP 204
140E:20F E8 EE 00 CALL 300
140E:212 59 POP CX
140E:213 5E POP SI
140E:214 C3 RET
20. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
Subroutine 1 steps:
•The instructions from 20A to 20B
checks if the counter CX value = zero
(i.e., end of array)
•If not yet, the instructions from 20C to
20D increment SI and jump back to 204
(i.e., repeat addition)
•If the counter CX value = zero (i.e.,
addition complete), the instructions
from 20F to 211 call the subroutine 2 to
compare the sum with 40 H
•The instructions 212 and 213 restore
the initial values of CX and SI
•The instructions 214 returns to the
main program
Subroutine 1 (13 instructions, 21 bytes)
140E:200 56 PUSH SI
140E:201 51 PUSH CX
140E:202 31 C0 XOR AX, AX
140E:204 02 04 ADD AL, [SI]
140E:206 80 D4 00 ADC AH, 0
140E:209 49 DEC CX
140E:20A E3 03 J CX Z 20F
140E:20C 46 INC SI
140E:20D EB F5 JMP 204
140E:20F E8 EE 00 CALL 300
140E:212 59 POP CX
140E:213 5E POP SI
140E:214 C3 RET
21. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
Subroutine 2 steps:
•The instructions from 300 to 302
compare the contents of AX to 0040
•If the sum is below 40, the
instructions from 305 to 306 make BL
content = zeros and return to
subroutine 1
•If the sum is above 40, the
instructions 303 jump to instruction
308 and the instructions from 308 to
309 make BL content = 01 and return
to subroutine 1
Subroutine 2 (6 instructions, 11 bytes)
140E:300 3C 40 00 CMP AX, 0040
140E:303 77 03 JA 308
140E:305 B3 00 MOV BL, 00
140E:307 C3 RET
140E:308 B3 01 MOV BL, 01
140E:30A C3 RET
22. Tracing Programs
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Microprocessor-Based Systems Dr. Randa Elanwar
FETCH EXECUTE (From
memory)
RESULT
MOV AX, CS 2R IR0, IR1 --- AX=140E
MOV SS, AX 2R IR0, IR1 --- SS=140E
MOV SP, FFFF 3R IR0, IR1, IR2 --- SP=FFFF
PUSH CS 1R IR0 2W to stack 140E:FFFE= 14
140E:FFFD= 0E
SP=FFFD
POP DS 1R IR0 2R from stack DS=140E
SP=FFFF
MOV CX, [0603] 4R IR0, IR1, IR2, IR3 2R [0603 is an offset] CX=0002
MOV SI, 605 3R IR0, IR1, IR2 --- 605 is a number SI = 0605
CALL 200 3R IR0, IR1, IR2 2W Ret. Add. In stack SP=FFFD
PUSH SI 1R IR0 2W to stack SP=FFFB
PUSH CX 1R IR0 2W to stack SP=FFF9