This document provides an overview of ECE2030 Introduction to Computer Engineering course. It introduces the instructor, Prof. Hsien-Hsin Sean Lee, and lists course details such as materials, assignments, exams, grading policy. It outlines the course objectives which include digital design principles like number systems, Boolean algebra, combinational and sequential logic. The focus will be on levels below system architecture like microarchitecture, gates and transistor levels.

1. ECE2030
Introduction to Computer Engineering
Lecture 1: Overview
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
Georgia TechGeorgia Tech

2. • Instructor: Prof. Hsien-Hsin “Sean” Lee
• Email: leehs@gatech.edu
• Course web: http://www.ece.gatech.edu/~leehs/ECE2030
• My office: Klaus 2318
• Teaching Materials:
– Morris Mano and Charles Kime, “Logic and Computer Design
Fundamentals,” the 3rd
edition
– Course notes and handouts (check out course web)
– TA: to be announced later
• Attending classes is important !!
ECE2030 Syllabus

3. ECE2030 Syllabus
• Grading policy
– 3 Homework assignment: 5% each
– 1 Programming assignment: 10%
– 3 in-class exams: 15% each
– 1 final exam: 30%
– [100,90]=A; (90,80]=B; (80,70]=C,(70,55]=D,(55,0]=F
• All homework: turn-in in the first 5 minutes “in
class” of the due day
• All exams: closed books, closed notes, no calculator
• Honor code
• Use webct (http://webct.gatech.edu) for your
homework and exam grades

4. Objective: Digital Design Principle
• Number systems
• Boolean algebra
• Switch and CMOS design
• Combinational logic
– Logic gates
– Building blocks: de/mux, de/encoder, shifters,
adder/subtractor, multiplier
– Logic minimization
– Mixed logic
• Sequential logic
– Latches, Flip-flops
– Counters
– State machines: Mealy/Moore machines

5. Objective: Digital Design Principle
• Memory and Programmable Devices
– Register, RAM, ROM, PLA, PAL
• Architectural concept
– Instruction set architecture (ISA)
– Stored-Program Computer and Sequential Control
(von Neumann architecture)
– Datapath
– Branches
• Processor and Software Convention
– MIPS ISA
– Procedural calls: Stack

6. Hierarchy of Computation
ProblemProblemProblemProblem AlgorithmAlgorithm
ss
AlgorithmAlgorithm
ss
Programming inProgramming in
High-Level LanguageHigh-Level Language
Programming inProgramming in
High-Level LanguageHigh-Level Language
Compiler/Assembler/Compiler/Assembler/
LinkerLinker
Compiler/Assembler/Compiler/Assembler/
LinkerLinker
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA) BinaryBinaryBinaryBinary
System architectureSystem architectureSystem architectureSystem architecture
Target MachineTarget Machine
(one implementation)(one implementation)
Target MachineTarget Machine
(one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architecture
Functional units/Functional units/
Building blocksBuilding blocks
Functional units/Functional units/
Building blocksBuilding blocks
Gates LevelGates Level
DesignDesign
Gates LevelGates Level
DesignDesign
TransistorsTransistorsTransistorsTransistors ManufacturingManufacturingManufacturingManufacturing

7. Hierarchy of Computation
ProblemProblemProblemProblem AlgorithmAlgorithm
ss
AlgorithmAlgorithm
ss
Programming inProgramming in
High-Level LanguageHigh-Level Language
Programming inProgramming in
High-Level LanguageHigh-Level Language
Compiler/Assembler/Compiler/Assembler/
LinkerLinker
Compiler/Assembler/Compiler/Assembler/
LinkerLinker
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA) BinaryBinaryBinaryBinary
System architectureSystem architectureSystem architectureSystem architecture
Target MachineTarget Machine
(one implementation)(one implementation)
Target MachineTarget Machine
(one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architecture
Functional units/Functional units/
Building blocksBuilding blocks
Functional units/Functional units/
Building blocksBuilding blocks
Gates LevelGates Level
DesignDesign
Gates LevelGates Level
DesignDesign
TransistorsTransistorsTransistorsTransistors ManufacturingManufacturingManufacturingManufacturing
System LevelSystem LevelSystem LevelSystem Level
Human LevelHuman LevelHuman LevelHuman Level
RTL LevelRTL LevelRTL LevelRTL Level
Logic LevelLogic LevelLogic LevelLogic Level
Circuit LevelCircuit LevelCircuit LevelCircuit Level
Silicon LevelSilicon LevelSilicon LevelSilicon Level

8. Our Focus in 2030
Hierarchy of Computation
ProblemProblemProblemProblem AlgorithmAlgorithm
ss
AlgorithmAlgorithm
ss
Programming inProgramming in
High-Level LanguageHigh-Level Language
Programming inProgramming in
High-Level LanguageHigh-Level Language
Compiler/Assembler/Compiler/Assembler/
LinkerLinker
Compiler/Assembler/Compiler/Assembler/
LinkerLinker
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA) BinaryBinaryBinaryBinary
System architectureSystem architectureSystem architectureSystem architecture
Target MachineTarget Machine
(one implementation)(one implementation)
Target MachineTarget Machine
(one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architecture
Functional units/Functional units/
Building blocksBuilding blocks
Functional units/Functional units/
Building blocksBuilding blocks
Gates LevelGates Level
DesignDesign
Gates LevelGates Level
DesignDesign
TransistorsTransistorsTransistorsTransistors ManufacturingManufacturingManufacturingManufacturing
System LevelSystem LevelSystem LevelSystem Level
Human LevelHuman LevelHuman LevelHuman Level
RTL LevelRTL LevelRTL LevelRTL Level
Logic LevelLogic LevelLogic LevelLogic Level
Circuit LevelCircuit LevelCircuit LevelCircuit Level
Silicon LevelSilicon LevelSilicon LevelSilicon Level

9. Zoom-in a System Component

10. 0
Moore’s Law
Exponential growthExponential growth
2,250
Transistor count will be doubled every 18 monthsTransistor count will be doubled every 18 months
 Gordon Moore, Intel co-founder
42millions
1.7 billions
Montecito
10 μm
13.5mm2
0.09 μm
596 mm2

11. 1
Integrated Circuit Complexity
Source: Intel

12. 2
Minimum Feature Size
We are currently at 0.065µm (65nm) and moving towards 0.045µm

13. 3
Average Transistor Price per year
Source: Dataquest

14. 4
Processor Market Segmentation
High PerformanceHigh Performance
(e.g. IBM Power5, G5, Intel 32/64, Itanium, Pentium4, Sun T1, etc)(e.g. IBM Power5, G5, Intel 32/64, Itanium, Pentium4, Sun T1, etc)
High PerformanceHigh Performance
(e.g. IBM Power5, G5, Intel 32/64, Itanium, Pentium4, Sun T1, etc)(e.g. IBM Power5, G5, Intel 32/64, Itanium, Pentium4, Sun T1, etc)
Embedded / low-powerEmbedded / low-power
(e.g. Intel Xscale, ARM, MIPS)(e.g. Intel Xscale, ARM, MIPS)
Embedded / low-powerEmbedded / low-power
(e.g. Intel Xscale, ARM, MIPS)(e.g. Intel Xscale, ARM, MIPS)
Special purposeSpecial purpose
(e.g. DSP, NVidia GForce)(e.g. DSP, NVidia GForce)
Special purposeSpecial purpose
(e.g. DSP, NVidia GForce)(e.g. DSP, NVidia GForce)

15. 5
Analog Signal vs. Digital
• So, why Digital?

16. 6
Binary Signals
• So, why Binary?

17. 7
Voltage Range of Binary Signals
0.0 Volts
1.0 Volts
2.0 Volts
3.0 Volts
4.0 Volts
5.0 Volts
INPUTINPUT OUTPUTOUTPUT
HIGH (1)HIGH (1)
LOW (0)LOW (0)
HIGH (1)HIGH (1)
LOW (0)LOW (0)

18. BACKUP

19. 9
A Generic Intel-based PC System
Your CPU hereYour CPU here

20. 0
Dual-Core Itanium 2 (Montecito)